Allwinner technology A20 User manual

A20

User Manual

Revision 1.1

Sep. 17, 2013

CONFIDENTIAL

Declaration

THIS A20 USER MANUAL IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY

(“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF

ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.

THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER

RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME

WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR

FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM

ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS

OF ALLWINNER. THIS DOCUMENTATION NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING

FITNESS FOR ANY PARTICULAR APPLICATION.

THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE

SOLELY RESPONSIBLE TO OBTAINALLAPPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL

NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY

LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO

MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.

CONFIDENTIAL

Revision History

Revision

Date

Description

1.0

March 22, 2013

Initial version

1.1

Septermber 17, 2013

Modify TVD and TVE description

CONFIDENTIAL

Table of Contents

Declaration ....................................................................................................................................................2

Revision History.............................................................................................................................................3

Table of Contents...........................................................................................................................................4

Chapter 1 System.....................................................................................................................................9

1.1. Overview................................................................................................................................10

1.2. A20 Block Diagram................................................................................................................17

1.3. Memory Mapping...................................................................................................................18

1.4. CPU Configuration.................................................................................................................22

1.4.1. Overview ........................................................................................................................22

1.4.2. CPU Configuration Register List....................................................................................23

1.4.3. CPUCFG Register Description ......................................................................................24

1.5. CCU.......................................................................................................................................33

1.5.1. Overview ........................................................................................................................33

1.5.2. Clock Tree Diagram .......................................................................................................34

1.5.3. CCU Register List...........................................................................................................34

1.5.4. CCU Register Description..............................................................................................37

1.6. System Boot..........................................................................................................................94

1.6.1. Overview ........................................................................................................................94

1.6.2. System Boot Diagram....................................................................................................95

1.7. System Control......................................................................................................................96

1.7.1. Overview ........................................................................................................................96

1.7.2. System Control Register List .........................................................................................97

1.7.3. System Control Register................................................................................................97

1.8. PWM....................................................................................................................................101

1.8.1. Overview ......................................................................................................................101

1.8.2. PWM Register List........................................................................................................102

1.8.3. PWM Register Description...........................................................................................102

1.9. Timer....................................................................................................................................107

1.9.1. Overview ......................................................................................................................107

1.9.2. Timer Register List.......................................................................................................108

1.9.3. Timer Register Description...........................................................................................109

1.10. High Speed Timer................................................................................................................133

1.10.1. Overview...............................................................................................................133

1.10.2. High Speed Timer Register List............................................................................134

1.10.3. High Speed Timer Controller Register..................................................................135

1.11. GIC ......................................................................................................................................146

1.11.1. Interrupt Source............................................................................................................146

1.12. DMA.....................................................................................................................................151

1.12.1. Overview...............................................................................................................151

1.12.2. DMARegister List.................................................................................................152

1.12.3. DMAController Register Description....................................................................153

1.13. Audio Codec........................................................................................................................170

1.13.1. Overview...............................................................................................................170

1.13.2. Audio Codec Block Diagram.................................................................................171

1.13.3. Audio Codec Register List....................................................................................171

1.13.4. Audio Codec Register Description........................................................................172

1.14. LRADC.................................................................................................................................189

CONFIDENTIAL

1.14.1. Overview...............................................................................................................189

1.14.2. LRADC Block Diagram .........................................................................................190

1.14.3. LRADC Register List.............................................................................................190

1.14.4. LRADC Register Description................................................................................191

1.15. TP........................................................................................................................................198

1.15.1. Overview...............................................................................................................198

1.15.2. Typical Application Circuit.....................................................................................199

1.15.3. TP Clock Tree .......................................................................................................199

1.15.4. A/D Conversion Time............................................................................................199

1.15.5. Principle of Operation ...........................................................................................201

1.15.6. TP Register List.....................................................................................................206

1.15.7. TP Register Description........................................................................................207

1.16. Security System...................................................................................................................217

1.16.1. Overview...............................................................................................................217

1.16.2. Security System Block Diagram ...........................................................................218

1.16.3. Security System Register List...............................................................................218

1.16.4. Security System Register Description..................................................................219

1.17. Security JTAG .....................................................................................................................227

1.17.1. Overview...............................................................................................................227

1.17.2. Security JTAG Register List..................................................................................228

1.17.3. Security JTAG Register Description.....................................................................228

1.18. Security ID...........................................................................................................................230

1.18.1. Overview...............................................................................................................230

1.18.2. SID Block Diagram................................................................................................231

1.18.3. Security System Register List...............................................................................231

1.18.4. Security ID Register Description...........................................................................232

1.19. Port Controller .....................................................................................................................238

1.19.1. Port Description ....................................................................................................238

1.19.2. Port Configuration Table .......................................................................................239

1.19.3. Port Register List ..................................................................................................245

1.19.4. Port Register Description......................................................................................246

Chapter 2 Memory................................................................................................................................305

2.1. DRAM..................................................................................................................................306

2.1.1. Overview ......................................................................................................................306

2.2. NAND Flash.........................................................................................................................307

2.2.1. Overview ......................................................................................................................307

2.2.2. Nand Flash Block Diagram..........................................................................................308

2.2.3. NFC Timing Diagram....................................................................................................309

2.2.4. NFC Operation Guide ..................................................................................................314

Chapter 3 Graphic................................................................................................................................317

3.1. Mixer Processor...................................................................................................................318

3.1.1. Overview ......................................................................................................................318

3.1.2. Mixer Processor Block Diagram...................................................................................319

3.1.3. MP Register List...........................................................................................................319

3.1.4. MP Register Description ..............................................................................................321

Chapter 4 Image...................................................................................................................................361

4.1. CSI0.....................................................................................................................................362

4.1.1. Overview ......................................................................................................................362

4.1.2. CSI0 Block Diagram.....................................................................................................363

4.1.3. CSI0 Description ..........................................................................................................363

4.1.4. CSI0 Register List........................................................................................................366

4.1.5. CSI0 Register Description............................................................................................368

4.2. CSI1.....................................................................................................................................396

4.2.1. Overview ......................................................................................................................396

CONFIDENTIAL

4.2.2. CSI1 Block Diagram.....................................................................................................397

4.2.3. CSI1 Description ..........................................................................................................397

4.2.4. CSI1 Timing Diagram...................................................................................................397

4.2.5. CSI1 Register List........................................................................................................398

4.2.6. CSI1 Register Description............................................................................................399

4.3. TV Decoder..........................................................................................................................411

4.3.1. Overview ......................................................................................................................411

Chapter 5 Display.................................................................................................................................412

5.1. TCON...................................................................................................................................414

5.1.1. Overview ......................................................................................................................414

5.1.2. TCON Block Diagram...................................................................................................415

5.1.3. TCON Register List......................................................................................................416

5.1.4. TCON Register Description..........................................................................................418

5.2. HDMI....................................................................................................................................444

5.2.1. Overview ......................................................................................................................444

5.2.2. HDMI Block Diagram....................................................................................................445

5.2.3. HDMI Control Register Description..............................................................................445

5.2.4. HDMI Register Description...........................................................................................447

5.3. Display Engine Frontend.....................................................................................................485

5.3.1. Overview ......................................................................................................................485

5.3.2. DEFE Block Diagram...................................................................................................486

5.3.3. DEFE Register List.......................................................................................................486

5.3.4. DEFE Register Description..........................................................................................490

5.4. Display Engine Backend .....................................................................................................536

5.4.1. Overview ......................................................................................................................536

5.4.2. Display Engine Block Diagram.....................................................................................537

5.4.3. DEBE Register list........................................................................................................537

5.4.4. DEBE Register Description..........................................................................................540

5.5. TV Encoder..........................................................................................................................582

5.5.1. Overview ......................................................................................................................582

Chapter 6 Interface...............................................................................................................................583

6.1. SD3.0...................................................................................................................................584

6.1.1. Overview ......................................................................................................................584

6.1.2. SD3.0 Timing Diagram.................................................................................................584

6.2. TWI......................................................................................................................................585

6.2.1. Overview ......................................................................................................................585

6.2.2. TWI Controller Timing Diagram....................................................................................586

6.2.3. TWI Controller Register List.........................................................................................586

6.2.4. TWI Register Description.............................................................................................587

6.2.5. TWI Controller Special Requirement............................................................................595

6.3. SPI.......................................................................................................................................597

6.3.1. Overview ......................................................................................................................597

6.3.2. SPI Timing Diagram.....................................................................................................598

6.3.3. SPI Register List...........................................................................................................599

6.3.4. SPI Register Description..............................................................................................600

6.3.5. SPI Special Requirement.............................................................................................614

6.4. UART...................................................................................................................................615

6.4.1. Overview ......................................................................................................................615

6.4.2. UART Timing Diagram .................................................................................................616

6.4.3. UART Register List.......................................................................................................616

6.4.4. UART Register Description..........................................................................................617

6.4.5. UART Special Requirement.........................................................................................635

6.5. PS2......................................................................................................................................638

6.5.1. Overview ......................................................................................................................638

CONFIDENTIAL

6.5.2. PS2 Block Diagram......................................................................................................639

6.5.3. PS2 Timing Diagram....................................................................................................639

6.5.4. PS2 Register List..........................................................................................................641

6.5.5. PS2 Register Description.............................................................................................641

6.5.6. PS2 Special Requirements ..........................................................................................649

6.6. IR .........................................................................................................................................650

6.6.1. Overview ......................................................................................................................650

6.6.2. IR Block Diagram .........................................................................................................651

6.6.3. IR Register List.............................................................................................................651

6.6.4. IR Register Description................................................................................................652

6.7. USB OTG.............................................................................................................................665

6.7.1. Overview ......................................................................................................................665

6.7.2. USB OTG Timing Diagram...........................................................................................665

6.8. USB Host.............................................................................................................................666

6.8.1. Overview ......................................................................................................................666

6.8.2. USB Host Block Diagram.............................................................................................667

6.8.3. USB Host Timing Diagram...........................................................................................667

6.8.4. USB Host Register List ................................................................................................667

6.8.5. EHCI Register Description...........................................................................................668

6.8.6. OHCI Register List.......................................................................................................687

6.8.7. OHCI Register Description...........................................................................................688

6.8.8. USB Host Special Requirement...................................................................................705

6.9. Digital Audio Interface .........................................................................................................706

6.9.1. Overview ......................................................................................................................706

6.9.2. Digital Audio Interface Block Diagram..........................................................................707

6.9.3. Digital Audio Interface Timing Diagram........................................................................707

6.9.4. Digital Audio Interface Register List.............................................................................709

6.9.5. Digital Audio Interface Register Description ................................................................709

6.9.6. Digital Audio Interface Special Requirement................................................................726

6.10. AC97 Interface.....................................................................................................................729

6.10.1. Overview...............................................................................................................729

6.10.2. AC97 Block diagram.............................................................................................730

6.10.3. AC97 Interface Clock Tree....................................................................................731

6.10.4. AC Link Frame Format..........................................................................................731

6.10.5. AC97 Interface Timing Diagram............................................................................732

6.10.6. AC97 Interface Register List.................................................................................736

6.10.7. AC97 Interface Register Description....................................................................737

6.10.8. AC97 Interface Special Requirement ...................................................................747

6.11. EMAC ..................................................................................................................................748

6.11.1. Overview ......................................................................................................................748

6.11.2. EMAC Block Diagram ..................................................................................................749

6.11.3. EMAC Operation Diagram ...........................................................................................750

6.12. GMAC..................................................................................................................................753

6.12.1. Overview...............................................................................................................753

6.12.2. GMAC Block Diagram...........................................................................................754

6.13. Transport Stream.................................................................................................................755

6.13.1. Overview...............................................................................................................755

6.13.2. Transport Stream Block Diagram..........................................................................756

6.13.3. Transport Stream Controller Register List............................................................756

6.13.4. Transport Stream Register Description.................................................................758

6.13.5. Transport Stream Clock Requirement ..................................................................777

6.14. Smart Card Reader .............................................................................................................778

6.14.1. Overview...............................................................................................................778

6.14.2. Smart Card Reader Block Diagram......................................................................779

CONFIDENTIAL

6.14.3. Smart Card Reader Timing Diagram....................................................................779

6.14.4. Smart Card Reader Register List .........................................................................779

6.14.5. Smart Card Reader Register Description.............................................................780

6.14.7. SCIO Pad Configuration.......................................................................................792

6.15. SATA Host...........................................................................................................................793

6.15.1. Overview...............................................................................................................793

6.15.2. SATA_AHCI Timing Diagram................................................................................793

6.16. CAN.....................................................................................................................................794

6.16.1. Overview...............................................................................................................794

6.16.2. CAN System Block Diagram.................................................................................795

6.16.3. CAN Bit Time Configuration..................................................................................795

6.17. Keypad.................................................................................................................................796

6.17.1. Overview...............................................................................................................796

6.17.2. Keypad Interface Register List..............................................................................797

6.17.3. Keypad Interface Register Description.................................................................797

6.17.4. Keypad Interface Special Requirement................................................................800

Appendix A................................................................................................................................................801

CONFIDENTIAL

Chapter 1 System

This part details the A20 system construction from following aspects:

OVERVIEW

A20 BLOCK DIAGRAM

MEMORY MAPPING

CPU CONFIGURATION

CCU

BOOT SYSTEM

SYSTEM CONTROL

PWM

TIMER

HIGH SPEED TIMER

GIC

DMA

AUDIO CODEC

LRADC

TP

SECURITY SYSTEM

SECURITY JTAG

SECURITY ID

PORT CONTROLLER

CONFIDENTIAL

1.1. Overview

Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and

smart TV applications.

A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy

efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also

integrates the powerful ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good

game compatibility. Besides, A20 supports 2160p video decoding and H.264 HP 1080p video encoding.

Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in,

4-CH CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More

importantly, A20 processor is pin-compatible with its predecessor A10, which greatly simplifies the product

design process and makes the upgrade of a design much easier.

The A20 features are listed below:

Dual-Core CPU

●Dual Cortex-A7

–ARMv7 ISA standard ARM instruction set

–Thumb-2

–Jazeller RCT

–NEON Advanced SIMD

–VFPv4 floating point

–Hardware virtualization support

–Large Physical Address Extensions(LPAE)

–JTAG debug

–One general timer for individual CPU

–32KB Instruction and 32KB Data L1 cache for individual CPU

Graphic Engine

●3D

–Mali400 MP2 GPU

–Support OpenGL ES 2.0 / OpenVG 1.1 standard

●2D

–Support BLT and ROP2/3/4

–Support 90°/180°/270° rotation

–Support mirror/ alpha (plane and pixel alpha) /color key

CONFIDENTIAL

–Format conversion: ARGB 8888/4444/1555, RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp (input

only), YUV 444/422/420

Memory

●Internal BROM

–Support system boot from NAND Flash, SPI Nor Flash (SPI0), SD Card/TF card (SDC0/2)

–Support system code download through USB OTG (USB0)

●SDRAM

–Support DDR3/DDR3L/DDR2

–Support 32-bit bus width

–Support 2GB address space

●NAND Flash

–Comply to ONFI 2.3 and Toggle 1.0

–Support 64-bit ECC per 512 bytes or 1024 bytes

–Support 8bits data bus width

–Support 1.8V/3.3V signal voltage

–Support 1K/2K/4K/8K/16K page size

–Support up to 8 CE and 2 RB

–Support system boot from NAND flash

–Support SLC/MLC NAND and EF-NAND

–Support SDR/DDR NAND interface

●SD/MMC Interface

–Comply with eMMC standard specification V4.3

–Comply with SD physical layer specification V3.0

–Comply with SDIO card specification V2.0

–Support 1/4/8 bits bus width

–Support HS/DS/SDR12/SDR25 bus mode

–Support eMMC mandatory and alternative boot operations

–Support four independent SD/MMC/SDIO controllers

–Support SDSC/SDHC/SDXC/MMC/ RS-MMC card

–Support eMMC/iNand Flash

–Support 1GB/2GB/4GB/8GB/16GB/32GB/64GB /128GB SD/MMC card

–Support SDIO interrupt detection

–Support descriptor-based internal DMA controller for efficient scatter and gather operations

CONFIDENTIAL

System Resources

●Timer

–6 timers: clock source can be switched over 24M/32K for all timers, and external signals can be used

as clock source for Timer4/5

–Two 33-bit AVS counters

–Watchdog to generate reset signal or interrupt

–Real time counter for second, minute, hour, day, month, and year

●High Speed Timer

–4 channels

–Clock source is fixed to AHB, and the pre-scale ranges from 1 to 16

–56-bit counter that can be separated to 24-bit high register and 32-bit low register

●DMA

–16 channels

–Support data width of 8/32 bits

–Support linear and IO address modes

●CCU

–8PLLs, a main 24MHz oscillator, an on-chip RC oscillator and a 32768Hz oscillator (optional)

●GIC

–Support 16 SGIs, 16 PPIs, and 128 SPIs

–Support ARM architecture security extensions

–Support ARM architecture virtualization extensions

–Support uniprocessor and multiprocessor environments

Video Engine (Phoenix 3.0)

●Video Decoding

–Support picture size up to 3840x2160

–Support decoding speed up to 1080p@60fps

–Supported formats: Mpeg1/2, Mpeg4 SP/ASP GMC, H.263 including Sorenson Spark, H.264

BP/MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc.

●Video Encoding

–H.264 HP up to 1080p@30fps

–Jpeg baseline: picture size up to 4080x4080

–Alpha blending

–Thumb generation

–4x2 scaling ratio from 1/16 to 64 arbitrary non-integer ratio

CONFIDENTIAL

Display Engine

●Four moveable and size-adjustable layers, each layer size up to 8192x8192 pixels

●Ultra-Scaling engine

–8-tap scale filter in horizontal and 4 tap in vertical

–Source image size from 8x4 to 8192x8192 resolution and destination image size from 8x4 to

8192x8192 resolution

●Support multiple image input formats

–mono 1/2/4/8 bpp

–palette 1/2/4/8 bpp

–6/24/32 bpp color

–YUV444/420/422/411

●Support alpha blending/color key/gamma/harware cursor/sprite

●Output color correction: luminance/hue/saturation, etc

●Support de-interlace

●Video enhancement: lum peaking/DCTi/black and white level extension

●3D input/output format conversion and display

Video Output

●HDMI 1.4 transmitter with HDCP

●LVDS/Sync RGB/CPU LCD interface up to 1920x1200 resolution

●Support 4-channel CVBS, or 2-channel S-video, or 1-channel YPbPr/VGA (YPbPr/VGA up to 1080p)

●Support two-channel independent display

Video Input

●Support TV decoder: 4-ch analog CVBS or 1-ch YPbPr(480i/576i/480p/576p) signal input

●Dual CMOS sensor parallel interfaces that support YUV format only

–CSI0 up to 1080p@30fps

–CSI1 up to 720p@30fps

●Support BT656 interface

●Support 24-bit YUV444/RGB interface

Analog Audio Output

●Stereo audio DAC

●Stereo capless headphone drivers

–Up to 100dB SNR during DAC playback

–Support 8KHz~192KHz DAC sample rate

●One low-noise analog microphone bias

●Dedicated headphone outputs

CONFIDENTIAL

●Two mixers to meet different requirements

–Output mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output

–ADC record mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output

Analog Audio Input

●Support four analog audio inputs

–Two microphone inputs

–Differential or stereo line-in input

–Stereo FM-in input

●Stereo audio ADC

–96dBA SNR

–Support 8KHz ~ 48KHz ADC sample rate

RTP

●12-bit SAR ADC

●Dual touch detection

●Sampling frequency up to 2MHz

Connectivity

USB2.0 OTG

●Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in

Host mode

●Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in Device mode

●Support up to 5 user-configurable endpoints for Bulk , Isochronous, Control and Interrupt

USB EHCI/OHCI

●Two EHCI/OHCI-compliant hosts

EMAC

●Support 10/100Mbps MII data transfer rate

GMAC

●Comply with the IEEE 802.3-2002 standard

●Programmable frame length to support Standard or Jumbo Ethernet frames with size up to 16KB

●Support 10/100/1000Mbps data transfer rates RGMII interface to communicate with an external Gigabit

PHY

●Support 10/100Mbps MII PHY interface

Digital Audio In/Out

●One I2S compliant audio interface, supporting 8-channel and 2-channel input

CONFIDENTIAL

●One PCM, supporting linear sample(8-bit or 16-bit), 8-bit u-law and A-law companded sample

●One AC97 audio codec, supporting 2-channel and 6-channel audio data output

Transport Stream Controller

●Support both SPI and SSI

●Speed up to 150Mbps for both SPI and SSI

●Support 32-channel PID filter

●Support hardware PCR packet detect

Open-Drain TWI

●Up to 5 TWIs compliant with TWI protocol

Smart Card Reader

●One smart card reader controller supporting ISO/IEC 7816-3 and EMV2000 specifications

●Support synchronous and any other non-ISO 7816 and non-EMV cards

SPI

●Master/Slave configurable

●Up to 4 independent SPI controllers: SPI0 with one CS signal for system boot, SPI1/2/3 each with two

CS signals

UART

●Up to 8 UART controllers:UART0 with two wires for debug tools, UART1 with 8 wires, UART2/3 each

with 4 wires, and others each with 2 wires

PS2

●Two PS2 compliant to IBM PS2 and AT-compatible keyboard and mouse interface

●Dual-role controller: a PS2 host or a PS2 device

●Two IR controllers supporting CIR, MIR and FIR modes

SATA

●One SATA Host controller

●Support SATA 1.5Gb/s and SATA 3.0Gb/s

●Comply with SATA spec 2.6

●Support external SATA(eSATA)

CAN

●One CAN bus controller

●Support the CAN2.0 A/B protocol specification

●Programmable data rate up to 1Mbps

CONFIDENTIAL

Keypad

●One keypad matrix interface up to 8 rows and 8 colums

●Interrupt for key press or key release

●Internal debouncing filter to prevent switching noises

LRADC

●6-bit resolution

●Voltage input range between 0V to 2V

PWM

●2 PWM outputs

●Support cycle mode and pulse mode

●The pre-scale is from 1 to 64

Security System

●Security System

–Support AES, DES, 3DES, SHA-1, MD5

–Support ECB/CBC/CNT modes for AES/DES/3DES

–128-bit, 192-bit and 256-bit key size for AES

–160-bit hardware PRNG with 192-bit seed

●Security JTAG

Power Management

●Flexible PLL clock generator and OSC for 32KHz

●Flexible clock gate

●Support DVFS for CPU frequency and voltage adjustment

●Support standby mode (only DDR+RTC-Domain power exist)

Package

●FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm

CONFIDENTIAL

1.2. A20 Block Diagram

CONFIDENTIAL

1.3. Memory Mapping

Module

Address

Size(Bytes)

SRAM A1

0x0000 0000---0x0000 3FFF

16K

SRAM A2

0x0000 4000---0x0000 7FFF

16K

SRAM A3

0x0000 8000---0x0000 B3FF

13K

SRAM A4

0x0000 B400---0x0000 BFFF

SRAM NAND

SRAM D

0x0001 0000---0x0001 0FFF

SRAM B(Secure)

0x0002 0000---0x0002 FFFF

64K

SRAM Controller

0x01C0 0000---0x01C0 0FFF

DRAM Controller

0x01C0 1000---0x01C0 1FFF

DMA

0x01C0 2000---0x01C0 2FFF

NAND Flash

0x01C0 3000---0x01C0 3FFF

Transport Stream

0x01C0 4000---0x01C0 4FFF

SPI 0

0x01C0 5000---0x01C0 5FFF

SPI 1

0x01C0 6000---0x01C0 6FFF

Memory Stick

0x01C0 7000---0x01C0 7FFF

TVD

0x01C0 8000---0x01C0 8FFF

CSI 0

0x01C0 9000---0x01C0 9FFF

TVE 0

0x01C0 A000---0x01C0 AFFF

EMAC

0x01C0 B000---0x01C0 BFFF

LCD 0

0x01C0 C000---0x01C0 CFFF

LCD 1

0x01C0 D000---0x01C0 DFFF

Video Engine

0x01C0 E000---0x01C0 EFFF

SD/MMC 0

0x01C0 F000---0x01C0 FFFF

SD/MMC 1

0x01C1 0000---0x01C1 0FFF

SD/MMC 2

0x01C1 1000---0x01C1 1FFF

SD/MMC 3

0x01C1 2000---0x01C1 2FFF

CONFIDENTIAL

Module

Address

Size(Bytes)

USB 0

0x01C1 3000---0x01C1 3FFF

USB 1

0x01C1 4000---0x01C1 4FFF

Security System

0x01C1 5000---0x01C1 5FFF

HDMI

0x01C1 6000---0x01C1 6FFF

SPI 2

0x01C1 7000---0x01C1 7FFF

SATA

0x01C1 8000---0x01C1 8FFF

PATA

0x01C1 9000---0x01C1 9FFF

ACE

0x01C1 A000---0x01C1 AFFF

TVE 1

0x01C1 B000---0x01C1 BFFF

USB 2

0x01C1 C000---0x01C1 CFFF

CSI 1

0x01C1 D000---0x01C1 DFFF

0x01C1 E000---0x01C1 EFFF

SPI3

0x01C1 F000---0x01C1 FFFF

CCU

0x01C2 0000---0x01C2 03FF

Interrupt

0x01C2 0400---0x01C2 07FF

PIO

0x01C2 0800---0x01C2 0BFF

Timer

0x01C2 0C00---0x01C2 0FFF

SPDIF

0x01C2 1000---0x01C2 13FF

AC97

0x01C2 1400---0x01C2 17FF

IR0

0x01C2 1800---0x01C2 1BFF

IR 1

0x01C2 1C00---0x01C2 1FFF

IIS-1

0x01C2 2000---0x01C2 23FF

IIS-0

0x01C2 2400---0x01C2 27FF

LRADC 0/1

0x01C2 2800---0x01C2 2BFF

AD/DA

0x01C2 2C00---0x01C2 2FFF

Keypad

0x01C2 3000---0x01C2 33FF

0x01C2 3400---0x01C2 37FF

SID

0x01C2 3800---0x01C2 3BFF

SJTAG

0x01C2 3C00---0x01C2 3FFF

0x01C2 4000---0x01C2 43FF

IIS-2

0x01C2 4400---0x01C2 47FF

0x01C2 4800---0x01C2 4BFF

CONFIDENTIAL

Module

Address

Size(Bytes)

0x01C2 4C00---0x01C2 4FFF

0x01C2 5000---0x01C2 53FF

PMU

0x01C2 5400---0x01C2 57FF

0x01C2 5800---0x01C2 5BFF

CPU Configuration

0x01C2 5C00---0x01C2 5FFF

0x01C2 6000---0x01C2 63FF

0x01C2 6400---0x01C2 67FF

0x01C2 6800---0x01C2 6BFF

0x01C2 6C00---0x01C2 6FFF

0x01C2 7000---0x01C2 73FF

0x01C2 7400---0x01C2 77FF

0x01C2 7800---0x01C2 7BFF

0x01C2 7C00---0x01C2 7FFF

UART 0

0x01C2 8000---0x01C2 83FF

UART 1

0x01C2 8400---0x01C2 87FF

UART 2

0x01C2 8800---0x01C2 8BFF

UART 3

0x01C2 8C00---0x01C2 8FFF

UART 4

0x01C2 9000---0x01C2 93FF

UART 5

0x01C2 9400---0x01C2 97FF

UART 6

0x01C2 9800---0x01C2 9BFF

UART 7

0x01C2 9C00---0x01C2 9FFF

PS2-0

0x01C2 A000---0x01C2 A3FF

PS2-1

0x01C2 A400---0x01C2 A7FF

0x01C2 A800---0x01C2 ABFF

TWI 0

0x01C2 AC00---0x01C2 AFFF

TWI 1

0x01C2 B000---0x01C2 B3FF

TWI 2

0x01C2 B400---0x01C2 B7FF

TWI 3

0x01C2 B800---0x01C2 BBFF

CAN

0x01C2 BC00---0x01C2 BFFF

TWI 4

0x01C2 C000---0x01C2 C3FF

Smart Card Reader

0x01C2 C400---0x01C2 C7FF

GPS

0x01C3 0000---0x01C3 FFFF

64K

CONFIDENTIAL

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