Texas Instruments LMH0318 Manual

Programmer's Guide
SNLU183–September 2015
LMH0318 Programming Guide
This document provides a reference for the LMH0318 Reclocker from a programming model perspective.
It contains detailed information relating to programming and different configuration options. The intended
audience includes software as well as hardware engineers working on the system diagnostics and control
software.
The reader should be familiar with the LMH0318 datasheet (SNLS508). In addition to the LMH0318
datasheet, all other collateral data related to the LMH0318 Reclocker (application notes, models, etc.), are
available on the TI website. Alternatively, contact your local Texas Instruments field sales representative.
Contents
1 Access Methods ............................................................................................................. 2
1.1 Register Programming via SMBus and SPI Interface.......................................................... 2
1.2 Register Programming via SPI.................................................................................... 3
1.3 Register Types ..................................................................................................... 3
2 Initialization Set Up.......................................................................................................... 4
3 Register Command Syntax ................................................................................................ 5
4 Device Configuration ....................................................................................................... 6
4.1 Common Device Configuration ................................................................................... 6
4.2 Common Register Commands ................................................................................... 7
5 Register Tables............................................................................................................. 19
5.1 Global Registers................................................................................................... 19
5.2 Receiver Registers................................................................................................ 23
5.3 CDR Registers..................................................................................................... 29
5.4 Transmitter Registers............................................................................................. 34
List of Tables
1 LMH0318 Register Initialization............................................................................................ 4
2 LMH0318 SMPTE Configuration .......................................................................................... 6
3 SMPTE Data Rate Selection............................................................................................... 9
4 CTLE Boost Setting vs Media Trace Length............................................................................ 10
5 Global Registers............................................................................................................ 19
6 Receiver Registers......................................................................................................... 23
7 CDR Registers.............................................................................................................. 29
8 Transmitter Registers...................................................................................................... 34
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Access Methods www.ti.com
1 Access Methods
Two methods are provided for accessing the LMH0318 Registers:
• Register control via the Serial Management Bus (SMBus)
• Register control via the Serial Parallel Interface (SPI)
In a typical system, either SMBus or SPI access is used to configure and monitor the device status.
Unless specified, the register configurations for SPI and SMBus are the same.
1.1 Register Programming via SMBus and SPI Interface
The LMH0318 internal registers can be accessed through standard SMBus or SPI protocol. The SMBUS
Mode is enabled by setting MODE_SEL pin = LOW (1 kΩto GND). Pins associated with SMBus interface
are:
* ADDR0 (pin #2): Strap pin used to set the SMBus address
* ADDR1 (pin #15): Strap pin used to set the SMBus address
* SDA (pin #14): SMBus data pin
* SCL (pin #3): SMBus clock pin
The SMBus slave address is strapped at power up based on the configuration of the ADDR0 and ADDR1
pins. The state of these two pins are read on power up - after the internal power-on reset signal is de-
asserted. The maximum operating speed supported on the SMBus is 400 kHz.
There are 16 unique SMBus addresses that can be assigned to each device by placing external Resistor
straps on the ADDR0 and ADDR1 pins (pin #2 and #15).
1.1.1 SMBus Slave Address
ADDR0 ADDR1
ADDR0 ADDR1 7-bit SMBus Address (1) 8-bit SMBus Write Address
Binary Binary
1 kΩto GND 1 kΩto GND 00 00 0D 1A
1 kΩto GND 20 kΩto GND 00 01 0E 1C
1 kΩto GND Float 00 10 0F 1E
1 kΩto GND 1 kΩto VDD 00 11 10 20
20 kΩto GND 1 kΩto GND 01 00 11 22
20 kΩto GND 20 kΩto GND 01 01 12 24
20 kΩto GND Float 01 10 13 26
20 kΩto GND 1 kΩto VDD 01 11 14 28
Float 1 kΩto GND 10 00 15 2A
Float 20 kΩto GND 10 01 16 2C
Float Float 10 10 17 2E (2)
Float 1 kΩto VDD 10 11 18 30
1 kΩto VDD 1 kΩto GND 11 00 19 32
1 kΩto VDD 20 kΩto GND 11 01 1A 34
1 kΩto VDD Float 11 10 1B 36
1 kΩto VDD 1 kΩto VDD 11 11 1C 38
(1) Seven (7) bit SMBus addresses need to include LSB equal to zero for write and 1 for read operation. For example, for 7 bit hex
address 0x0D, the controlling program should use I2C hex address 0x1A to write and 0X1B to read. This is true for other
addresses as well.
(2) Default SMBus Address
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1.2 Register Programming via SPI
Alternatively, when MODE_Sel is pulled high with 1 kΩ-resistor, the SPI interface is used for device
configuration. Pins associated with the SPI interface are:
* MOSI: Master Output, Slave input (pin#4)
* MISO: Master Input, Slave Output (pin#15)
* SS_N: Slave Select active low (pin#2)
* SPI_SCK: Serial clock output from master (pin#3)
The maximum operating speed supported on the SPI bus is 20 MHz.
1.3 Register Types
The LMH0318 register set is divided into four groups:
• Global Registers- These registers are divided into share and channel registers. Share register define
LMH0318 ID, revision, enabling shared registers. Channels registers are feature specific such as
interrupt status or interrupt mask
• Receiver Registers- These registers are associated with input stage of the device - equalizer boost
setting, signal detect levels and input mux selection.
• Clock Data Recovery (CDR) Registers- These registers control CDR state machine, Eye Opening
Monitor (EOM), and configuration.
• Transmitter Registers- These registers configure output multiplexers and output parameters for OUT0
and OUT1.
3
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2 Initialization Set Up
After power up or register reset write the initialization sequences:
Table 1. LMH0318 Register Initialization
DESCRIPTION ADDRESS [Hex] VALUE [Hex]
Enable Channel Registers 0xFF 0x04
Enable Full Temperature Range 0x16 0x25
0x3E 0x00
Initialize CDR State Machine Control 0x55 0x02
0x6A 0x00
Restore media CTLE Setting 0x03 xx
Reset CDR 0x0A 0x5C
Release Reset 0x0A 0x50
See LMH0318 Register Initialization for detailed register programming
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3 Register Command Syntax
Unless otherwise specified, the settings below apply to both SMBus and SPI register programming.
Operations are read-modify-write. This requires the register to be read first and modified by applying the
specific bit mask.
Command Syntax:
RAW Register Register Register Mask //Comments
Address Content
RAW: This defines a Read/Write command
Register Address: Specifies the register address in hex
Register Content Specifies the value in hex that is going to be written
Register Mask: Defines bits within the register content that will be modified
//: Text comment
Example: RAW In this example, we are setting reg 0x80[0] = 1'b to power down OUT0.
80 01 01 0x80[7:1] are not modified since mask = 0x01
RAR Register Register Register Mask //Comments
Address Content
RAR: Read Only Command
Register Address: Specifies the register address in hex format
Register Content Specifies the register content that is being read
Register Mask: Defines the mask for register content. For example, 1 in a mask defines bits
being read
//: Characters following // are text comments
Example: RAR Read 0xE2[4] and check if bit 4 is set
E2 10 10
●When using SMBus or SPI interface, the host controller may need to set over-ride bit prior to setting
the control bits of a register
●It is recommended to issue CDR Reset and Release after changing register settings that alters CDR
state machine
●See Register Tables for further details on register bit definitions
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Device Configuration www.ti.com
4 Device Configuration
The following sections provide guidance for programming the LMH0318 for certain common applications.
Throughout the rest of the document, macro examples are given to setup the device for different
configurations and settings.
4.1 Common Device Configuration
The LMH0318 supports SMPTE data rates. Once configured for SMPTE application, the LMH0318 can be
optioned to lock to a selection of data rates and report lock status. The following is an example of common
register settings for the LMH0318 initialization followed by possible settings to support SMPTE data rates.
Table 2. LMH0318 SMPTE Configuration
COMMAND REGISTER VALUE MASK //Comments
//Initialization sequence
RAW FF 04 07 //Select Channel Registers
RAW 16 25 FF //Enable Full Temperature Range
RAW 3E 00 80 //Initialize CDR State Machine Control
RAW 55 02 02
RAW 6A 00 FF
RAW 03 XX FF //Use the desired CTLE settings. See CTLE Test Mode to determine the
CTLE setting
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR reset
//In default mode, the LMH0318 automatically locks to different SMPTE
and ST-2082/1 data rates
RAR 1 1 1 //Read LOS of IN0
//Assuming signal is present on IN0, enable IN0 to 75 ΩOUT0 and power
RAW 31 1 3 down 50 ΩOUT1
RAW 2F 00 C0 //Default SMPTE is enabled
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR Reset
RAR 02 18 18 //If reg 0x02[4:3] = 11'b, CDR locked
RAW 0C 30 F0 //Setup register 0x0C to enable reg 0x02 to read the VCO divider settings
RAR 02 38 38 //0x02[5:3] Indicates lock rates
RAW 0C 00 F0 //Setup register 0x0C to enable reg 0x02 to read lock indication
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4.2 Common Register Commands
The followings macros specify register settings for common operations.
4.2.1 Enable Channel Control
In default mode, the shared registers are enabled. To change any channel specific parameter, input
selection, Eye Opening Monitor, Horizontal Eye Opening (HEO), or Vertical Eye Opening (VEO), channel
control must first be enabled as follows:
RAW FF 04 07 //Select Channel Registers
Note: Share register 0xFF can be written/read all the time and does not require selection of share register
bank.
4.2.2 LMH0318 Reset Registers
The LMH0318 has two reset functions: CDR State Machine Reset and Register Reset.
4.2.2.1 LMH0318 CDR State Machine Reset
This operation should be done after changing any of the channel registers.
RAW FF 04 07 //Select Channel Registers
RAW 0A 0C 0C //Reset for the new settings to take place
RAW 0A 00 0C //Release CDR Reset
4.2.2.2 LMH0318 Register Reset
Restore registers default settings:
RAW FF 04 07 //Select Channel Registers
RAW 00 04 04 //Reset Channel Registers
RAW FF 00 07 //Select shared registers
RAW E2 01 0F //Enable Clock Data Recovery (CDR) State Machine
RAR E2 10 10 //Wait until bit 4 set
RAW FF 04 07 //Select Channel Register
Note: LMH0318 Register Initialization must be done after issuing Register Reset
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4.2.2.3 LMH0318 Register Initialization
After power up, ENABLE pin transition from low to high, or LMH0318 Register Reset write the following
register initialization.
RAW FF 04 07 //Select Channel Registers
RAW 16 25 FF //Enable Full Temperature Range
RAW 3E 00 80 //Initialize CDR State Machine Control
RAW 55 02 02
RAW 6A 00 FF
RAW 03 XX FF //Use the desired CTLE settings. See CTLE Test Mode to determine the CTLE
setting
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR reset
4.2.3 Force Power Down
The ENABLE pin (#6) can be used to force the LMH0318 in power down. Additionally, the LMH0318
powers down when there is loss of signal (selected channel Signal Detect is not asserted). There could be
a need to power down the device even when there is active signal. This could be achieved either by
disabling ENABLE pin or forcing the signal detect de-asserted and thus powering down the selected
channel.
To force IN0 signal detect off:
RAW FF 04 07 //Select Channel Registers
RAW 14 40 C0 //Force Signal Detect Off for IN0
To force IN1 signal detect off:
RAW FF 04 07 //Select Channel Registers
RAW 15 40 C0 //Force Signal Detect Off for IN1
After forcing signal detect off, the controlling program may need to enable the signal detect on IN0 or IN1
(normal operation):
RAW FF 04 07 //Select Channel Registers
RAW 14 00 C0 //IN0 Signal Detect Normal Operation
RAW FF 04 07 //Initialize CDR State Machine Control
RAW 15 00 C0 //IN1 Signal Detect Normal Operation
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4.2.4 Selective Data Rate Lock
In default mode, the LMH0318 is configured to automatically lock to all SMPTE data rates. The LMH0318
can be configured to lock to certain data rate or restricts the dividers so the CDR can only lock to the
desired data rate. This enables faster lock time.
Table 3. SMPTE Data Rate Selection
REGISTER FUNCTION
1: Enable CDR Lock to 270Mbps
Reg 0xA0[4] 0: Disable CDR Lock to 270Mbps
1: Enable CDR Lock to 1.485/1.4835 Gbps
Reg 0xA0[3] 0: Disable CDR Lock to 1.485/1.4835 Gbps
1: Enable CDR Lock to 2.97/2.967 Gbps
Reg 0xA0[2] 0: Disable CDR Lock to 2.97/2.967 Gbps
For example, to enable lock to 3G, HD, and 270 Mbps, the following script can be used:
RAW FF 04 07 //Select Channel Registers
RAW A0 1C 1F //Enable Lock to ST 424, ST 292, and ST 259 only
RAW 0A 0C 0C //Initialize CDR State Machine Control
RAW 0A 00 0C //Release CDR Reset
Alternatively, the following sequence can be used to disable lock to certain data rates (for example 3G):
RAW FF 04 07 //Select Channel Registers
RAW A0 00 04 //Disable Lock to 3G
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR Reset
4.2.5 Check Status of LOS (Loss Of Signal) on Input 1 or Input 0
The LMH0318 has two inputs and each input has its own signal detector. Based on signal detect status
and input channel selected, the device automatically goes into power down. For example, if IN0 is
selected and there is no signal on IN0 then the device, CDR and output drivers go into power down. The
following macro checks the status of the signal detects on IN0 or IN1:
RAW FF 04 07 //Select Channel Registers
RAW 1 01 01 //Read LOS of IN0
RAW 1 02 02 //Read LOS of IN1
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4.2.6 Input/Output Selection
The LMH0318 has 2:1 Mux on the Input and 1:2 Fan out on the output. Different input and output
configuration can be selected. The following settings allow these different configurations:
RAW FF 04 07 //Select Channel Registers
RAW 31 00 03 //Set to 00: Enable IN0 to OUT0 and OUT1
//
RAW FF 04 07 //Select Channel Registers
RAW 31 01 03 //Set to 01: Enable IN0 to OUT0 (OUT1 is powered down)
//
RAW FF 04 07 //Select Channel Registers
RAW 31 02 03 //Set to 10: Enable IN1 to OUT1 (OUT0 is powered down)
//
RAW FF 04 07 //Select Channel Registers
RAW 31 03 03 //Set to 11: Enable IN1 to OUT0 and OUT1
4.2.7 CTLE Test Mode
The LMH0318 Continuous Time Linear Equalizer compensates for the high frequency loss caused by the
transmission media. Deterministic jitter due to the ISI (Inter Symbol Interference) caused by the media can
be equalized by the LMH0318 CTLE.
In the default mode, the CTLE boost is determined by register 0x03. The default value of 0x80'h equalizes
10-15 inches PCB FR4 trace loss. The user may change register 0x03 to enable different boost settings
for different media loss characteristics . Table 4 shows recommended CTLE boost settings vs different
media trace length.
Table 4. CTLE Boost Setting vs Media Trace Length
FR4 TRACE SDD21 (dB) WRITE BOOST SETTING BOOST SETTING
LENGTH REGISTER
@ 6 GHz VALUE @ 3 GHz (dB) @ 6 GHz (dB)
(Inches)
1 -1.5 0x03 0x00 4.9 5.8
5 -7.5 0x03 0x00 4.9 5.8
10 -10.5 0x03 0x10 7.7 10.2
15 -15.5 0x03 0x50 10.9 15.3
20 -19.5 0x03 0x50 10.9 15.3
25 -24.5 0x03 0x60 13.2 17
30 -27.5 0x03 0x94 16.2 21.8
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For test purpose only, the register sequence below determines the correct CTLE setting. Note, the
selected CTLE setting produced by the test mode works for all of the data rates; therefore, this test should
be done at the highest data rate. The CTLE compensates for the media not the data rate. Additionally, for
3 Gbps or lower, register 0x55 specifies the fixed CTLE setting when operating in CTLE test mode.
RAW FF 04 07 //Select Channel Registers
RAW 2D 00 08 //Disable EQ over-ride
RAW 2C 40 40 //Enable VEO scaling
RAW 3E 80 80 //Enable HEO/VEO
RAW 6A 44 FF
RAW 31 20 60 //Enable CTLE Test Mode to optimize eye opening
RAW 0A 0C 0C //Reset CDR for the new settings to take place
RAW 0A 00 0C //Release CDR Reset
RAW 0C 00 F0 //Setup register 0x0C to read lock indication
RAW 02 18 18 //Wait until bits [4:3] = 11'b to indicate CDR locked
RAR 52 xx FF //Read EQ Boost setting and store in xx for normal mode of operation
RAW 03 xx FF //Save EQ Boost setting in reg 0x03
RAW 2D 08 08 //Enable the device to force EQ Setting from Reg 0x03
RAW 31 00 60 //Allow register 0x03 to control CTLE setting
RAW 3E 00 80 //Restore initialization settings
RAW 6A 00 FF //Restore initialization settings
RAW 2C 00 40 //Disable VEO scale
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4.2.8 Eye Opening Monitoring Operation
The LMH0318 has an on-chip eye opening monitor (EOM) which can be used to analyze, monitor, and
diagnose the performance of the link. The EOM operates on the post-equalized waveform, just prior to the
data sampler. Therefore, it captures the effects of all the equalization circuits within the receiver.
The EOM monitors the post-equalized waveform in a time window that spans one unit intervals and a
configurable voltage range that spans up to ±400 mV differential. The time window and voltage range are
divided into 64 steps, so the result of the eye capture is a 64 × 64 matrix of “hits,” where each point
represents a specific voltage and phase offset relative to the main data sampler. The number of “hits”
registered at each point needs to be put into context with the total number of bits observed at that voltage
and phase offset in order to determine the corresponding probability for that point. The number of bits
observed at each point is configurable.
A common measurement performed by the EOM is the horizontal and vertical eye opening. The Horizontal
Eye Opening (HEO) represents the width of the post-equalized eye at 0-V differential amplitude, typically
measured in unit intervals or pico-seconds. The Vertical Eye Opening (VEO) represents the height of the
post-equalized eye, measured midway between the mean zero crossing of the eye. This position in time
approximates that of the CDR sampling phase. The followings are the steps required to read eye hits for
64 × 64 cells or total 4096 cells.
RAW FF 04 07 //Select Channel Registers
RAW 11 00 20 //Enable EOM
RAW 24 80 80 // Start Fast EOM
RAR 24 00 01 //Wait until EOM samples ready (0x24[0]= 0'b)
RAW 26 xx 00 //Read Reg 0x26 and discard the content
RAR 24 00 01 //Wait until EOM Samples Ready
RAW 26 xx 00 //Read Reg 0x26
RAR 24 00 01 //Wait until EOM Samples Ready
RAW 25 xx FF //Read Reg 0x25 and save number of eye hits
RAW 26 xx FF //Read Reg 0x26 and save number of eye hits
//Execute the above three commands for 4095 times (total 4096 times for
64X64 cells)
RAW 24 00 80 //Disable fast EOM
RAW 11 20 20 //Power down EOM
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4.2.9 Lock Data Rate Indication
There could be a need to realize the data rate the device has locked to. In this case, register 0x02[4] is
read to make sure the device is locked. Then VCO divisor setting indicates the data rate.
RAW FF 04 07 //Select Channel Registers
RAW 0C 00 F0 //Setup register 0x0c to read lock indication bit 4
RAW 02 18 18 //Wait until bit 4 is set indicating device is locked
RAW 0C 30 F0 //Setup register 0x0C to read the VCO divider setting
RAR 02 38 38 //Read divider settings
// 02[5-3] = 010'b 2.97 Gbps
// 02[5-3] = 011'b 1.485 Gbps
// 02[5-3] = 100'b 270Mbps
RAW 0C 00 F0 //Setup the default value for Reg 0x0C
4.2.10 Read Horizontal and Vertical Eye Opening
The LMH0318 produces two readings to indicate line signal quality: The Horizontal Eye Opening (HEO)
and the Vertical Eye Opening (VEO) are indications of signal quality. These parameters can be read by
the host processor or the LMH0318 can be optioned to cause interrupt if HEO/VEO reach a threshold.
To convert the HEO reading to Unit Interval (UI) eye opening, we need to divide the HEO reading, in
decimal, to 64.
HEO = (Decimal Reg0x27)/64
For example, if the HEO reading is 0x31 (49 decimal) then the HEO UI eye opening would be
49/64=0.77UI. This means the HEO is about 77% open.
Similarly, VEO has 64 steps as well. The chip automatically covers differential peak to peak value from +/-
100mV to +/-400mV and reports the value adjusted to +/-100 mV. Thus, each step is 200/64 or 3.125 mV.
Therefore VEO in mV = (Decimal VEO value)×3.125. For example, if we read 0xC8 (200 decimal) for the
VEO reading, this corresponds to 200 × 3.125 mV = 625 mV vertical eye opening.
RAW FF 04 07 //Select Channel Registers
RAW 11 00 20 //Enable EOM
RAW 3E 80 80 //Enable HEO/VEO
RAR 27 xx FF //Read HEO, convert hex to dec, then divide by 64 for value in UI
RAR 28 xx FF //Read VEO, convert hex to decimal and Multiply by 3.125mV
RAW 3E 00 80 //Restore initialization setting
RAW 11 20 20 //Power down EOM
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4.2.11 OUT0 and OUT1 Mode Selection
The LMH0318 75-ΩOUT0 and 50-ΩOUT1 can be configured to drive out the reclocked data, raw data
(i.e non reclocked), clock, or these outputs to be muted (common mode voltage on both positive and
negative output signal).
4.2.11.1 OUT0 and OUT1 Default Mode of Operation
In default mode, register 0x1C[3:2] determine the output configuration for both outputs per following table.
0x1C[3:2} OUT0 OUT1
00 Mute Mute
01 Locked: Reclocked Data Full data rate clock
Unlocked: Raw Data Unlocked: Mute
10 Locked: Reclocked Data Locked: Reclocked Data
Unlocked: Raw Data Unlocked: Raw Data
11 Forced Raw Data Forced Raw Data
The following can be used to set OUT0 and OUT1 configuration:
RAW FF 04 07 //Select Channel Registers
RAW 09 00 20 //Allow register 0x1C to control OUT0 and OUT1 configuration
RAW 1C 00 0C //Mute OUT0 and OUT1
RAW 1C 04 0C //Locked: OUT0 Reclocked Data OUT1 Recovered Clock Un-Locked: OUT0
Raw Data OUT1 Mute
RAW 1C 80 0C //Locked: OUT0: Reclocked Data OUT1: Reclocked Data Un-Locked: OUT0
Raw Data OUT1 Raw data
RAW 1C 0C 0C //OUT0 Raw Data OUT1 Raw Data
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4.2.11.2 OUT0 and OUT1 Independent Control:
The LMH0318 allows independent control of OUT0 and OUT1. Note: 0x09[5] over-ride effects both OUT0
and OUT1.
4.2.11.2.1 OUT0 10 MHz Clock
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable Over-ride
RAW 1C 20 F0 //10MHz on OUT0
4.2.11.2.2 OUT0 RAW Data
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable over-ride
RAW 1C 40 E0 //OUT0 Raw Data
4.2.11.2.3 OUT0 Mute
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable Over-ride
RAW 1C 00 E0 //Set to 0: Mute OUT0
4.2.11.2.4 OUT0 Reclocked Data
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable Over-ride
RAW 1C 80 E0 //OUT0 Reclocked Data (valid only in locked condition)
4.2.11.2.5 OUT1 RAW Data
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable Over-ride to control this setting with registers
RAW 1E 00 E0 //OUT1 RAW Data
4.2.11.2.6 OUT1 Mute
When OUT1 is muted, the differential peak-to-peak output voltage is approximately 0 V.
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable over-ride to control with registers
RAW 1E E0 E0 //Set to 0: Mute OUT1
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4.2.11.2.7 OUT1 Reclocked Data
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable over-ride
RAW 1E 20 E0 //Locked: OUT1 Reclocked Data (valid only in locked condition)
4.2.11.2.8 OUT1 Full Rate Clock
The following sequence enables full rate or line recovered clock.
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable over-ride
RAW 1E 40 E0 //OUT1 full rate clock
4.2.11.2.9 OUT1 10 MHz Clock
RAW FF 04 07 //Select Channel Registers
RAW 09 20 20 //Enable over-ride
RAW 1E A0 E0 //Enable 10 MHz on OUT1
4.2.12 Invert OUT1 Data Polarity
For ease of layout, there may be a need to invert the polarity of the OUT1 differential pair.
RAW FF 04 07 //Select Channel Registers
RAW 1E 80 80 //Invert OUT1 Polarity
4.2.13 OUT0 and OUT1 Settings
The LMH0318 has programmable VOD (Voltage Output Differential), Pre-Emphasis (OUT0), PW (Pulse
Width OUT0 settings), De-Emphasis Settings, and individual power-down settings
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4.2.13.1 OUT0 VOD Settings
75-ΩOUT0has programmable peak to peak setting from 720 mV to 880 mV. In default mode, output
voltage setting is expected to be 800mV ±15 mV. To increase or decrease the output voltage swing, the
content of Reg 0x80[7:4] has to be read first and then increased or decreased respectively. Note: In raw
mode, the VOD setting would use register setting -3 (irrespective of the data rate).
RAW FF 04 07 //Select Channel Registers
RAR 80 XX F0 //Read Register 0x80[7:4]
RAW 80 XX F0 //Adjust by 1, 2, or 3 to get the desired output voltage swing
4.2.13.2 OUT0 Power Down or Power Up
The LMH0318 OUT0 75 Ωcurrent mode output draws high current and can be powered down to save
power.
RAW FF 04 07 //Select Channel Registers
RAW 80 03 03 //Power Down OUT0
RAW FF 04 07 //Select Channel
RAW 80 02 03 //Power up OUT0
4.2.13.3 OUT1 VOD Settings
OUT1 VOD settings can have a range of 600 mv to 1300 mv:
RAW FF 04 07 //Select Channel Registers
RAW 84 00 70 //Set drv_1_sel_vod to 0 (570 mVp-p)
RAW 84 20 70 //Set drv_1_sel_vod to 2 (730 mVp-p)
RAW 84 40 70 //Set drv_1_sel_vod to 4 (900 mVp-p)
RAW 84 60 70 //Set drv_1_sel_vod to 6 (1035 mVp-p)
4.2.13.4 OUT1 De-Emphasis Settings
There are 15 output de-emphasis settings for the LMH0318 OUT1, ranging from 0 dB to -11 dB. The de-
emphasis values come from register 0x85, bits 2:0 and 0x85 bit 3, which is the de-emphasis range bit.
RAW FF 04 07 //Select Channel Registers
RAW 85 00 0F //OUT1 DE Setting set to 0 dB
RAW 85 02 0F //OUT1 DE Setting set to -2 dB
RAW 85 07 0F //OUT1 DE Setting set to -11 dB
4.2.13.5 OUT1 Power Down
If needed the OUT1 output can be powered down:
RAW FF 04 07 //Select Channel Registers
RAW 84 03 03 //Power Down out1
RAW 84 02 03 //Power Up OUT1 (normal operating State)
17
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4.2.14 Signal Quality Alert HEO Interrupt Threshold
The LMH0318 can be optioned to cause interrupt if HEO goes below certain threshold and reg 0x56[3] =
1'b. The LMH0318 compares HEO value, reg 0x27[7:0], vs threshold setting of reg 0x32[7:4]*4. Note:
Register 0x54[7:0] indicates source of interrupt. Also, reg 0x FF[5] needs to be set to enable interrupt on
to LOS pin.
RAW FF 04 07 //Select Channel Registers
RAW 11 00 20 //Enable EOM
RAW 32 60 F0 //Set HEO interrupt threshold level: 6*4 = 24/64 = .37 If HEO drops below
0.37UI enable interrupt
RAW 56 08 08 //Enable HEO/VEO Signal Quality Alert interrupt
RAW FF 20 20 //Enable interrupt onto LOS pin
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR Reset so changes will go into effect
4.2.15 Signal Quality Alert VEO Threshold Settings
Similar to HEO setting, the VEO can also be programmed to cause if VEO drops below a threshold.
RAW FF 04 07 //Select Channel Registers
RAW 11 00 20 //Enable EOM
RAW 32 06 0F //Set VEO interrupt threshold level: 6*4*3.125 = 75mV If VEO drops below 75
mV enable interrupt
RAW 56 04 08 //Enable HEO/VEO Signal Quality Alert interrupt
RAW FF 80 20 //Enable interrupt onto LOS pin
RAW 0A 0C 0C //Reset CDR
RAW 0A 00 0C //Release CDR Reset so changes will go into effect
18 LMH0318 Programming Guide SNLU183–September 2015
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www.ti.com Register Tables
5 Register Tables
Register Maps
The LMH0318 register set definition is organized into four groups:
1. Global Registers: Chip ID, Interrupt status, LOS registers
2. Receiver Registers: Equalizer boost settings and signal detect setting
3. CDR Registers: PLL control
4. Transmitter Registers: OUT0 and OUT1 parameter setting
The typical device initialization sequence for the LMH0318 includes the followings. For detailed register
settings See LMH0318 Programming Guide (SNLU183).
1. Shared Register Configuration
(a) Reading device ID
(b) Selecting interrupt on to LOS pin
(c) Settings up the register to access the channel registers
2. Channel Register Configuration
(a) CDR Reset
(b) Interrupt register configuration
(c) Optional Input/Output selection
(d) Optional VOD selection
(e) CDR Reset and Release
5.1 Global Registers
Table 5. Global Registers
FIELD REGISTER
REGISTER NAME BITS DEFAULT R/RW DESCRIPTION
ADDRESS
SMBus Observation Reg_0x00 Share 0x00 SMBus Address Observation
7 SMBUS_addr3 0 R SMBus strap observation
6 SMBUS_addr2 0 R
5 SMBUS_addr1 0 R
4 SMBUS_addr0 0 R
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
Reset Shared Regs Reg 0x04 Share 0x01 Shared Register Reset
7 Reserved 0 RW
rst_i2c_regs 1: Reset Shared Registers
6 0 RW 0: Normal operation
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 1 RW
Enable SMBus Strap Reg 0x06 Share 0x00 Allow SMBus strap observation
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
19
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Table 5. Global Registers (continued)
FIELD REGISTER
REGISTER NAME BITS DEFAULT R/RW DESCRIPTION
ADDRESS
4 Reserved 0 RW
3 Test control[3] 0 RW Set to >9 to allow strap observation
on share reg 0x00
2 Test control[2] 0 RW
1 Test control[1] 0 RW
0 Test control[0] 0 RW
Device Version Reg 0xF0 Share 0x01 Device Version
7 VERSION[7] 0 RW Device revision
6 VERSION[6] 0 RW
5 VERSION[5] 0 RW
4 VERSION[4] 0 RW
3 VERSION[3] 0 RW
2 VERSION[2] 0 RW
1 VERSION[1] 0 RW
0 VERSION[0] 1 RW
Channel Control Reg 0xFF Control 0x00 Enable Channel Control
7 Reserved 0 RW
6 Reserved 0 RW
los_int_bus_sel 1: Selects interrupt onto LOS pin
5 0 RW 0: Selects signal detect onto LOS pin
4 Reserved 0 RW
3 Reserved 0 RW
en_ch_Access 1: Enables access to channel
2 0 RW registers
0: Enables access to share registers
1 Reserved 0 RW
0 Reserved 0 RW
Reset_Channel_Regs Reg_0x00 Channel Reset all Channel Registers to
0x00 Default Values
7 Reserved 0
6 Reserved 0
5 Reserved 0
4 Reserved 0
3 Reserved 0
Rst_regs 1: Reset Channel Registers ( self
2 0 clearing )
0: Normal operation
1 Reserved 0
0 Reserved 0
LOS_status Reg_0x01 Channel 0x00 Signal Detect Status
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
LOS1 1: Loss of signal on IN1
1 0 R 0: Signal present on IN1
LOS0 1: Loss of signal on IN0
0 0 R 0: Signal present on IN0
20 LMH0318 Programming Guide SNLU183–September 2015
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