Alpha Micro AM-100 User manual

JAN l' 1979
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TECHNICAL MANUAL
FOR
AM·" OC
2-BOARD 1 B-BIT CPU
DWM-001 00-00

~alpha
~~rnICrD
TECHNICAL MANUAL
FOR
AM-~DD
2-BOARD 1 6-BIT CPU
Manufactured By
ALPHA MICROSYSTEMS
17881 SKY PARK NORTH
IRVINE, CALIFORNIA 8271 4

PROPIUETARY NOTICE
This document and the information herein disclosed is the proprietary property
of ALPHA MICRO, 17881 Sky Park North, Irvine, California 92714. Any persllo
or entity to whom this document is furnished ot havingpossession thereof, by ac-
ceptance, auumes custody thereof and agrees that the document is given in con-
fidence and will not be copied or reproduced in whole or·in part, nor used or
revealed to any person in any manner except to meet the purposes for which it
was delivered. Additional rights and obligations regarding this document and its
contents may be de(med;by aseparate written agreement with ALPHA MICRO-
SYSTEMS, and if so, suc1t!separate written agreement shall be controlling.
"AMOS:' "Alpha BASIC;" and "AM-IOO" are trademarks of products and soft·
ware of ALPHA MICROSYSTEMS, Irvine, California -92714 ©1978, 1979,
ALPHA MICROSYSTEMS.

USER COMMENTS <'
TECHNICAL PUBLICATIONS FILE REFERENCE
FROM: NAME
NOTE,
Use this form to communicate any errors,
ADDRESS
suggested changes, or general comments
about this document.
If necessary, call us at:
CITY
17141957-6076
STATE ZIP
DOCUMENT:
COMMENTS:
TITLE/NUMBER/REVISION _
FOLD,STAPLE & MArl
ZZF-OOOO2-01

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[r\Ilne, California
92714
ATTN: EDUCATIONAL SERVICES DIVISION
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TABLE OF CONTENTS
Paragraph Page
1.0
1.1
1.2
2.0
2.1
2. 2
2.3
2.4
2 • 5
3.0
3.1
3.2
3.2. 1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2. 7
3.2. 8
SECTION 1 GENERAL DESCRIPTION
Introduction • . . . • . •
Circuit Board Description
Application . . . . . . .
SECTION 2 OPERATING DATA
Introduction . . . . . . . . • .
Capabilities and Specifications
Interface Description and Wiring
User Options • • . . . . •
Interrupt and DMA Options
System Connections . •
SECTION 3 PROGRA~~ING
Introduction . . . .
System Configuration
Software Overview
Operating System .
Assembly Language Program
Text Editor .
Utility and Sort Programs
A1phabasic Program
Accounting Package
A1phaLisp
A1phaPasca1
i
1-1
1-1
1- 2
2-1
2-1
2-2
2-6
2- 8
2- 8
3-1
3-1
3· 5
3- 5
3- 5
3-6
3-6
3-6
3- 7
3- 7
3-7

Paragraph
Page
SECTION
4 FUNCTIONAL
THEORY
OF OP,ERATION
4.0
Introduction
····
4-1
4.1
CPU
Configuration
4-1
4.1. 1AM-100
Two-Board Set
4-1
4.1. 2
S-100
Bus Operation
4-2
4.1.3 CPU
Chip
Set
4-16
4.1.3.1 Data
Chip
4-16
4.1.3.2
Control Chip
4-18
4.1.3.3 Microm
Chips
4-18
4.1.3.4
Microinstruction
Bus 4-18
4.2
CPU Operations
·
4-21
4. 2. 1 Clock
Generator
4- 34
4.2.2
State
Code Decoder Logic
4- 35
4.2. 3
Sequencer
Operation 4- 35
4.2.4 Initialization and Status 4-47
(
4.2.5
Data Access
·· · ··
4-48
4.2.5.1
Addressing
Operations
4-50
4.2.5.2
Write
Operations
···
4- 50
4.2.5.3
Read
Operations
···
4-51
4.2.6
DMA and
Interrupt Operations
4-51
4.2.6.1 CPU
Chip
Set Interrupts 4-52
4.2.6.2
Vectored
Interrupts
4-53
4.2.6.3
DMA Operations
· ·
4-53
4.3
CPU Microprocessor
Chip' Set Description
4-54
4.3. 1
System Components
· · ·...
4-58
4.3.1.1
Registers
··· · ··...
4-59
4.3.1.2
Instruction
Address Generation
4-64
4.3.1.3
Microinstruction Bus ·· 4-65
4.3.1.4 Data
Access
Bus ····
4-66
4.3.1.5 Microinstruction Storage
4-66
4. 3.2 CPU Operations,
4-66
4.3.2.1 CPU Sequencing
4-67
4.3.2.2
Control Lines
4-75
ii

Microinstruction Bus Operation
Bus Operation ....
'Microinstruction Bus Element Description
Data Chip
Control Chip ..
Microinstruction ROM
Data Access
Input/Output Instructions
Data/Address Lines ....
Control Lines .. . . . .
Interrupt, Reset, and Compute
Input/Output Operations
Circuit Module Description ..
Four-Phase Clock Generator (Board 2, U12).
Tri-State 4-Bit DType Register (Board 1,
U1, U9, U10) .
High-Speed Hex Inverter (Board 1, U7)
Tri-State Buffers (Board 1, U5, U8, U22,
U24, U26; Board 2, U45, U46, U48) '"
Hex Tri-State Buffers (Board 2, U1l, U47).
Eight-Line to Three-Line Encoder (Board 2,
U29, U30) ..........•.....
Data Selector/Multiplexer (Board 1, U16,
U17, U18, U21) .
NAND TTL-to-MOS Driver Board (Board 1, U2,
U 3). • • • • • • • • • • • . • • • . • • •
D Positive-Edge-]riggered Flip-Flops with
Preset and Clear (Board 2, U6, U18, U19,
U
23, U 31, U3 2, U 34, U36) . . . . . . . . .
Paragraph
4. 3. 3
4.3.3.1
4.3.3.2
4. 3.4
4. 3. 5
,4.3.5.1
4.3.5.2
4.3.5.3
4.3.5.4
4.3.5.5
4.3.6
4.3.6.1
4.3.6.2
4.3.6.3
4.3.6.4
4.3.6.5
4.4
4.41
4.4.2
4.4. 3
4.4.4
4.4.5
4.4.6
4.4. 7
4.4. 8
4.4.9
Programmable Translation
Programmable Translation
Programmable Translation
Microinstructions
Array
Array
Array
(PTA) . . .
Conponents.
Operations.
Page
4- 78
4- 79
4-90
4-96
4-108
4-109
4-109
4-114
4-114
4~ 116
4-117
4-118
4-134
4-134
4-136
4-137
4-142
4-143
4-145
4-146
4-147
4-148
4-149
4-150
4-151
4-152
iii

Paragraph Page
4.4.10 Dual J-K Negative-Edge-Triggered Flip-Flops
With Preset (Board 2, UiO, U28, U40, USC,
r"
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
U 51) .. .. • .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
Dual Retriggerable One-Shots With Clear
(Board 2, U22) .....•...•...
Dual Voltage Controlled Oscillators (Board
2, US) .. .. .. .. .. .. .. .. .. .. .... .... ..
Decoder (Board 2, U7, U8, U42) '"
D Flip-Flops With Clear (Board 1, U13, U14,
U25; Board 2, UlO) .....•....
Tri-State Octal Buffers (Board 1, U6, U11,
4-153
4-154
4-155
4-156
4-157
U19, U27) .. .. .. .. .. .. ..
.. .. .. .. .. .. ..
4-158
5.0
5. 1
5.2
SECTION 5 MAINTENANCE AND TROUBLESHOOTING
Introduction ...•.
Circuit Board Checkout
Warranty Procedures
SECTION 6 SCHEMATIC AND PARTS LIST
5-1
5-1
5-2
Schematic and Parts List
iv
.... . .
.. .. .. ..
6-1

Figure
1-1
1-2
2-1
2-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
LIST OF ILLUSTRATIONS
AM-laO Circuit Board Set Simplified Block
Diagram . • . . . . . . . •
AM-lOa System Block Diagram
Header Jumper Wiring . . .
Real Time Clock Connection
S-IOO Bus Read Timing
S-IOO Bus Write Timing ..
S-IOO Bus Read-Modify-Write Timing
S-100 Bus DMA Timing ....
CPU Chip Set . . . . . . . • . .
Microinstruction Bus Timing
AM-lOO Functional Block Diagram
AM-lOO System Clocks ...
Sequencer Flow Diagram . .
Sequencer Logic Equations
CPU Read Byte Timing •
CPU Read Word Timing .
CPU Write Byte Timing
CPU Write Word Timing
CPU Read-Modify-Write Byte Timing
CPU Read-Modify-Write Word Timing
AM-lOO Power-Up Sequence ....•
MCP 1600 Microprocessor Block Diagram
Register File
01 Data Paths
02 Data Paths
03 Data Paths
v
1- 3
1- 5
2-7
2-10
4-5
4-6
4- 7
4-8
4-17
4-20
4- 2 3
4-34
4- 39
4-40
4- 41
4-42
4-43
4-44
4-45
4-46
4-49
4-55
4-61
4- 70
4- 71
4- 72

Figure
4- 2 3
4-24
4-25
4-26
4-27
4-28
4-29
4- 30
4-31
4- 32
4-33
4-34
4- 35
4- 36
4-37
4-38
4- 39
4-40
4-41
4-42
4- 4 3
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
4-53
4-54
¢4 Data Paths .•... .
¢4 Data Paths Second Cycle
Major Control Lines '"
PTA Component Interconnections
Array No. 1 Organization ...
Typical Gate - Array No.1 ..
Array No. 2 Data Specification
Array No. 2 Organization •..
Array No. 2 Gate and Interconnect Structure.
Data Specification . . • . . • . • . . • • .
Array No.3 Interrupt Organization .....
Array No. 3 Translation Register Organization.
Typical Gate of Array No. 3
Array No. 4 Organization
01 Data Flow
¢2 Data Flow
¢3 Data Flow
¢4 Data Flow
System Interconnections Microprocessor Set
TTL Output Timing CP1631B ......
Microinstruction Bus Interface Timing
Control Chip Microinstruction Bus Timing
Microinstruction Bus Timing CP1631B
I/O Instruction Condition Testing
Execution of Read Instruction
Execution of Write Instruction.
Execution of Input Instruction .
Execution of Output Instruction
Write/Output Sequence ..
Read/Input Sequence
Read-Modify-Write Sequence
Interrupt Acknowledge Sequence
vi
Page
4- 73
4- 74
4-76
4- 80
4-81
4-81
4-82
4- 83
4- 83
4- 85
4- 86
4- 86
4-87
4- 89
4-92
4-93
4-94
4-95
4-108
4-113
4-115
4-116
4-117
4-120
4-121
4-124
4-128
4-131
4-139
4-139
4-140
4-141

"
Figure
4-55
4-56
4-57
4-58
4-59
4-60
4-61
4-62
4-63
4-64
4-65
4-66
4-67
4-68
4-69
Four Phase Clock Logic and Timing .....
Tri-State 4-Bit D Type Register Connections.
High Speed Hex Inverter Connections
Tri-State Buffer Connections ..
Hex Tri-State Buffer Connections
Eight-Line to Three-Line Encoder Connections
Data Selector/Multiplexer Connections
NAND TTL-To-MOS Driver Connections
D Flip-Flop Connections
J-K Flip-Flop Connections
One-Shot Connections . . . •
Dual Voltage Controlled Oscillator Connections
Decoder Connections
D Flip-Flop Connections
Tri-State Octal Buffer Connections
vii
Page
4-144
4-145
4-146
4-147
4-148
4-149
4-150
4-151
4-152
.4-153
4-154
4-155
4-156
4-157
4-158

Table
2-1
2-2
3-1
3- 2
3- 3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
LIST OF TABLES
AM-I00 Specifications
AM-I00 Interface Signals .
Alpha Micro I/O Addresses
Boot Addresses .
DMA Levels . . . . • . • .
Interrupt Levels . . . . .
S-100 Bus Command/Control Lines.
S-100 Bus Status Lines ....•
S-100 Bus Utility Lines ...•
S-100 Bus Interface Signals List
AM-I00 Signals List ....
Microm State Code Functions
Status Byte Buffer Bits
CPU Chip Set Interrupts
Data Chip (CP1611B) Pin Assignments
Control Chip (CP1621B) Pin Assignments
Microm Chip (CP1631B) Pin Assignments
Translation State Code Outputs 4 of 7
Translation State Code Outputs -- 5 of 7
Microinstruction Set ..•.••...
Microinstructions .
Summary
of Microinstruction and Status Flags
Microbus Timing ...•. . . . • . . • . .
viii
Page
2-1
2- 3
3- 2
3- 3
3- 4
3-4
4- 3
4-3
4- 3
4-10
4-27
4- 36
4-47
40 52
4-56
4-57
4-57
4- 84
4- 84
4-99
4-100
4-105
4-110
•

SECTION I
GENERAL DESCRIPTION
1.0 INTRODUCTION.
This manual provides operating and maintenance instructions
for the AH-IOO Central Processor Unit (CPU) circuit board
set manufactured by Alpha Microsystems located in Irvine,
California. Circuit board description, operating and usage
instructions, programming, theory of operation, and maintenance
instructions are included to provide the user with the infor-
mation necessary to utilize this circuit board to its full
capability.
1.1 CIRCUIT BOARD DESCRIPTION.
The AM-IOO CPU circuit board set is a 16-bit microprocessor
board set that is compatible with the 5-100 Bus structure.
The AM-IOO utilizes the Western Digital. WD16 chip set
microprogrammed to enhance the software of the operating
system. The microprocessor provides 16-bit flexibility and
speed with floating point arithmetic to provide large throughput.
The two board AM-Ioo supports most of the standard 5-100 Bus
peripherals including static memory, 1/0 facilities and video.
A simplified block diagram of the AM-IOO CPU board set is
shown in Figure 1-1. For a complete detailed description
of CPU operation, see Section 4 of this manual.
1-1

1.2 APPLICATION.
The AM-IOO is a l6-bit CPU that is fully compatible with a
standard 8-bit 5-100 bus system. It is fully compatible with
many available peripherals from other manufacturers. A block
diagram of the system capability is contained in Figure 1-2.
This shows the basic 5-100 Bus structure, the currently avail-
able Alpha Micro circuit cards, and the commercially available
peripherals that can be used for a fully integrated system.
1-2
•
t

1-5/1-6 Blank
Figure 1-2. AM-IOO System Block Diagram
16 BIT ADOl'lESS BUS
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CONTROLS
Figure 1-1. AM-IOO Simplified
Block Diagram
1-3/1-4 Blank

SECTION 2
OPERATING
DATA
2.0 INTRODUCTION.
This Section contains information on the use of the AM-lOO
CPU two board set. Capabilities, specifications, interface
wiring and user option descriptions are provided for the
successful integration of the board into the user's system.
2.1 CAPABILITIES AND SPECIFICATIONS.
This two board set operates from the standard 5-100 Bus
structure and can be integrated into a complete system.
Specifications for the AM-lOO are contained in Table 2-1,
Table 2-1. AM-lOO Specifications
PARAMETER
SPECIFICATION
Interface
type Standard S-lOO
Bus,
l6-Bit words,
byte multiplexed
for
compatibility
to
8-bit peripherals and
memories.
Instruction
Set Over
150 standard instructions
coded
in unique microcode
executed on the
WD-16 CPU chip
set.
Arithmetic
Hardware floating point arithmetic
Operations
to 11 s igni fican t digits.
CPU Architecture Microprogrammed
instruction
set;
eight l6-bit
general purpose
regis-
ters; floating
point
hardware
uni t;
special
high-speed byte
multiplexing
logic.
2-1

Table 2-1 (Cont.). AM-lOO Specifications
PARAMETER
SPECIFICATION
Interrupt Capability
Eight vectored and one non-vectored
interrupt lines.
DMA Capability
Seven
DMA
channels.
(Included
in vec-
tored interrupt
line count.)
.. C-
Real Time Clock Standard Feature.
Circuit Boards Two board
set
-
standard
5" x
10"
with lOO-pin
connectors .
.
2.2 INTERFACE DESCRIPTION AND WIRING.
The AM-lOa CPU interfaces with the standard S-IOO Bus
structure. All data inputs, outputs, and control signals
are transferred through these lines. The S-IOO bus con-
nections are made by the bottom edge connectors and are
listed in Table 2-2.
2-2
(

Table 2-2. AM-lOO Interface Signals
SIGNAL
NAME
31
PIN NO.
AD Address
0
79
Al Address 180
A2
Address 281
A3
Address
331
A4 Address 4
30
AS
Address
S
29
A6
Address 6
82
A7 Address 783
A8
Address 8
84
A9 Address 9
34
AID
Address 10 37
All
Address 11
87
A12 Address 12 33
A13
Address 13
85
A14
Address 14 86
A15
Address 15
32
CLOC
2 MHz Clock
49
DID
Data Input Bus 95
DII Bits 0-7
94
DI2 41
DI3
42
DI4 91
DIS 92
DI6 93
DI7 43
2-3