Altera Arria 10 Avalon-ST Interface User manual

Arria 10 Avalon-ST Interface for PCIe Solutions
User Guide
Last updated for Quartus Prime Design Suite: 15.1
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2015.11.02
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Arria 10 Avalon-ST Interface for PCIe Datasheet
Altera®Arria®10 FPGAs include a configurable, hardened protocol stack for PCI Express®that is
compliant with PCI Express Base Specification 3.0. The Hard IP for PCI Express using the Avalon®
Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough
understanding of the PCIe®Protocol.
Figure 1-1: Arria 10 PCIe Variant with Avalon-ST Interface
Application
Layer
(User Logic)
Avalon-ST
Interface PCIe Hard IP
Block
PIPE
Interface PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4,
and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers
double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per
second for Gen2, and 8.0 giga-transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which
introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to
encoding to about 1.5%.
Link Width
×1 ×2 ×4 ×8
PCI Express Gen1
(2.5 Gbps) 2 4 8 16
PCI Express Gen2
(5.0 Gbps) 4 8 16 32
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Link Width
×1 ×2 ×4 ×8
PCI Express Gen3
(8.0 Gbps) 7.87 15.75 31.51 63
Refer to the AN 456: PCI Express High Performance Reference Design for more information about
calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including
the Arria 10 Hard IP for PCI Express IP core.
Devices
Related Information
•Introduction to Altera IP Cores
Provides general information about all Altera IP cores, including parameterizing, generating,
upgrading, and simulating IP.
•Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP version upgrades.
•Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
•PCI Express Base Specification 3.0
•AN 456: PCI Express High Performance Reference Design
This example design includes an Avalon-ST interface to the Application Layer. It illustrates chaining
DMA performance. You can download this design to an Altera Development Kit and that passes PCI-
SIG interoperability tests.
•Creating a System with Qsys
Arria 10 Features
New features in the Quartus®Prime 15.1 software release:
• New Generate Design Example option that automatically generates both simulation and hardware
example designs with the parameters you specify. You can download the hardware example design
directly to the Arria 10 FPGA Development Kit ES2 Edition.
• Revised component GUI that combines all supported data rates, interface widths and Application
Layer frequencies as a single parameter, HIP mode.
The Arria 10 Hard IP for PCI Express supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and
Native Endpoints.
• Dedicated 16 KByte receive buffer.
• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core
bitstreams to be stored separately.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
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• Support for multiple packets per cycle with the 256-bit Avalon-ST interface.
• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error
reporting (AER) for high reliability applications.
• Easy to use:
• Flexible configuration.
• Substantial on-chip resource savings and guaranteed timing closure.
• No license requirement.
• Example designs to get started.
Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores
The table compares the features for three variants of the Hard IP for PCI Express IP Core. An SR-IOV variant is
also available, but not included because it is very specialized product. Consult the Arria 10 Avalon-ST Interface
with SR-IOV PCIe Solutions User Guide for features of this IP core.
Feature Avalon-ST Interface Avalon-MM Interface Avalon-MM DMA
IP Core License Free Free Free
Native Endpoint Supported Supported Supported
Root port Supported Supported Not Supported
Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 Not Supported
Gen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8
Gen3 ×1, ×2, ×4, ×8 ×1, ×2, ×4 ×2, ×4, ×8
64-bit Application
Layer interface Supported Supported Not supported
128-bit Application
Layer interface Supported Supported Supported
256-bit Application
Layer interface Supported Not Supported Supported
Maximum payload size 128, 256, 512, 1024, 2048
bytes 128, 256 bytes 128, 256 bytes
Number of tags
supported for non-
posted requests
256 8 16
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Feature Avalon-ST Interface Avalon-MM Interface Avalon-MM DMA
Automatically handle
out-of-order
completions
(transparent to the
Application Layer)
Not supported Supported Supported
Automatically handle
requests that cross 4
KByte address
boundary (transparent
to the Application
Layer)
Not supported Supported Supported
Polarity Inversion of
PIPE interface signals Supported Supported Supported
Number of MSI
requests 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32
MSI-X Supported Supported Supported
Legacy interrupts Supported Supported Supported
Expansion ROM Supported Not supported Not supported
Table 1-3: TLP Support Comparison for all Hard IP for PCI Express IP Cores
The table compares the TLP types that the variants of the Hard IP for PCI Express IP Cores can transmit. Each
entry indicates whether this TLP type is supported (for transmit) by endpoints (EP), Root Ports (RP), or both (EP/
RP).
Transaction Layer Packet
type (TLP) (transmit
support)
Avalon-ST Interface Avalon-MM Interface Avalon-MM DMA
Memory Read Request
(Mrd)EP/RP EP/RP EP
Memory Read Lock
Request (MRdLk)EP/RP EP
Memory Write Request
(MWr)EP/RP EP/RP EP
I/O Read Request
(IORd)EP/RP EP/RP
I/O Write Request
(IOWr)EP/RP EP/RP
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Transaction Layer Packet
type (TLP) (transmit
support)
Avalon-ST Interface Avalon-MM Interface Avalon-MM DMA
Config Type 0 Read
Request (CfgRd0)RP RP
Config Type 0 Write
Request (CfgWr0)RP RP
Config Type 1 Read
Request (CfgRd1)RP RP
Config Type 1 Write
Request (CfgWr1)RP RP
Message Request (Msg) EP/RP EP/RP
Message Request with
Data (MsgD)EP/RP EP/RP
Completion (Cpl) EP/RP EP/RP EP
Completion with Data
(CplD)EP/RP EP
Completion-Locked
(CplLk)EP/RP
Completion Lock with
Data (CplDLk)EP/RP
Fetch and Add
AtomicOp Request
(FetchAdd)
EP
The Arria 10 Avalon-ST Interface for PCIe Solutions User Guide explains how to use this IP core and not
the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this
document only in conjunction with an understanding of the PCI Express Base Specification.
Note: This release provides separate user guides for the different variants. The Related Information
provides links to all versions.
Related Information
•Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
•Arria 10 Avalon-ST with SR-IOV PCIe Solutions User Guide
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Release Information
Table 1-4: Hard IP for PCI Express Release Information
Item Description
Version 15.1
Release Date November 2015
Ordering Codes No ordering code is required
Product IDs There are no encrypted files for the Arria 10 Hard
IP for PCI Express. The Product ID and Vendor ID
are not required because this IP core does not
require a license.
Vendor ID
Altera verifies that the current version of the Quartus Prime software compiles the previous version of
each IP core, if this IP core was included in the previous release. Altera reports any exceptions to this
verification in the Altera IP Release Notes or clarifies them in the Quartus Prime IP Update tool. Altera
does not verify compilation with IP core versions older than the previous release.
Related Information
Altera IP Release Notes
Device Family Support
Table 1-5: Device Family Support
Device Family Support
Arria 10 Preliminary. The IP core is verified with prelimi‐
nary timing models for this device family. The IP
core meets all functional requirements, but might
still be undergoing timing analysis for the device
family. It can be used in production designs with
caution.
Other device families Refer to the Altera's PCI Express IP Solutions web
page for support information on other device
families.
Related Information
•Altera's PCI Express Web Page
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Configurations
The Arria 10 Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack
including the following layers:
• Physical (PHY), including:
• Physical Media Attachment (PMA)
• Physical Coding Sublayer (PCS)
• Media Access Control (MAC)
• Data Link Layer (DL)
• Transaction Layer (TL)
The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Altera
devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You
can customize the Hard IP to meet your design requirements.
Figure 1-2: PCI Express Application with a Single Root Port and Endpoint
The following figure shows a PCI Express link between two Arria 10 FPGAs.
Altera FPGA
User Application
Logic
PCIe
Hard IP
RP
PCIe
Hard IP
EP
User Application
Logic
PCI Express Link
Altera FPGA
Figure 1-3: PCI Express Application Using Configuration via Protocol
The Arria 10 design below includes the following components:
• A Root Port that connects directly to a second FPGA that includes an Endpoint.
• Two Endpoints that connect to a PCIe switch.
• A host CPU that implements CvP using the PCI Express link connects through the switch. For more
information about configuration over a PCI Express link, refer to Configuration via Protocol (CvP)
on page 15-1.
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PCIe Link
PCIe Hard IP
RP Switch
PCIe
Hard IP
EP
User Application
Logic
PCIe Hard IP
EP
PCIe Link
PCIe Link
User Application
Logic
Altera FPGA Hard IP for PCI Express
Altera FPGA with Hard IP for PCI Express
Active Serial or
Active Quad
Device Configuration
Configuration via Protocol (CvP)
using the PCI Express Link
Serial or
Quad Flash
USB
Download
cable
PCIe
Hard IP
EP
User
Application
Logic
Altera FPGA with Hard IP for PCI Express
Config
Control
CVP
USB
Host CPU
PCIe
Related Information
Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
Debugging on page 18-1
IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
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models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli test the Application Layer interface, Configuration Space, and all
types and sizes of TLPs
• Error injection tests inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check
for the proper responses
• PCI-SIG®Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
Altera provides example designs that you can leverage to test your PCBs and complete compliance base
board testing (CBB testing) at PCI-SIG, upon request.
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no
ALMs and no embedded memory).
Related Information
Fitter Resources Reports
Recommended Speed Grades
Recommended speed grades are pending characterization of production Arria 10 devices.
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