Altera JESD204B IP CORE User manual

JESD204B IP Core User Guide
Last updated for Quartus Prime Design Suite: 16.1
Subscribe
Send Feedback
UG-01142
2016.10.31
101 Innovation Drive
San Jose, CA 95134
www.altera.com

Contents
JESD204B IP Core Quick Reference................................................................... 1-1
About the JESD204B IP Core..............................................................................2-1
Datapath Modes........................................................................................................................................... 2-3
IP Core Variation......................................................................................................................................... 2-3
JESD204B IP Core Conguration..............................................................................................................2-4
Run-Time Conguration................................................................................................................ 2-4
Channel Bonding......................................................................................................................................... 2-5
Performance and Resource Utilization..................................................................................................... 2-6
Getting Started.................................................................................................... 3-1
Introduction to Altera FPGA IP Cores..................................................................................................... 3-1
Installing and Licensing IP Cores.............................................................................................................. 3-2
OpenCore Plus IP Evaluation.....................................................................................................................3-3
Upgrading IP Cores..................................................................................................................................... 3-3
IP Catalog and Parameter Editor............................................................................................................... 3-6
Design Walkthrough....................................................................................................................................3-7
Creating a New Quartus Prime Project.........................................................................................3-8
Parameterizing and Generating the IP Core................................................................................ 3-8
Compiling the JESD204B IP Core Design.................................................................................... 3-9
Programming an FPGA Device................................................................................................... 3-10
JESD204B IP Core Design Considerations.............................................................................................3-10
Integrating the JESD204B IP core in Qsys..................................................................................3-10
Pin Assignments.............................................................................................................................3-11
Adding External Transceiver PLL................................................................................................3-12
Timing Constraints For Input Clocks......................................................................................... 3-12
JESD204B IP Core Parameters.................................................................................................................3-15
JESD204B IP Core Component Files...................................................................................................... 3-20
JESD204B IP Core Testbench...................................................................................................................3-21
Generating and Simulating the IP Core Testbench...................................................................3-22
Testbench Simulation Flow...........................................................................................................3-24
JESD204B IP Core Functional Description........................................................4-1
Transmitter....................................................................................................................................................4-4
TX Data Link Layer......................................................................................................................... 4-5
TX PHY Layer.................................................................................................................................. 4-8
Receiver......................................................................................................................................................... 4-8
RX Data Link Layer......................................................................................................................... 4-9
RX PHY Layer................................................................................................................................ 4-12
Operation.................................................................................................................................................... 4-13
TOC-2 JESD204B IP Core User Guide
Altera Corporation

Operating Modes........................................................................................................................... 4-13
Scrambler/Descrambler................................................................................................................ 4-14
SYNC_N Signal.............................................................................................................................. 4-14
Link Reinitialization...................................................................................................................... 4-16
Link Startup Sequence...................................................................................................................4-17
Error Reporting rough SYNC_N Signal.................................................................................4-18
Clocking Scheme........................................................................................................................................4-18
Device Clock...................................................................................................................................4-21
Link Clock.......................................................................................................................................4-23
Local Multi-Frame Clock..............................................................................................................4-24
Clock Correlation...........................................................................................................................4-25
Reset Scheme.............................................................................................................................................. 4-26
Reset Sequence............................................................................................................................... 4-27
ADC–FPGA Subsystem Reset Sequence.................................................................................... 4-28
FPGA–DAC Subsystem Reset Sequence.....................................................................................4-30
Signals..........................................................................................................................................................4-31
Transmitter......................................................................................................................................4-31
Receiver........................................................................................................................................... 4-40
Registers...................................................................................................................................................... 4-48
Register Access Type Convention................................................................................................4-48
JESD204B IP Core Deterministic Latency Implementation Guidelines........... 5-1
Constraining Incoming SYSREF Signal.................................................................................................... 5-1
Programmable RBD Oset......................................................................................................................... 5-2
Programmable LMFC Oset...................................................................................................................... 5-5
Maintaining Deterministic Latency during Link Reinitialization.......................................................5-10
JESD204B IP Core Debug Guidelines.................................................................6-1
Clocking Scheme..........................................................................................................................................6-1
JESD204B Parameters..................................................................................................................................6-1
SPI Programming.........................................................................................................................................6-1
Converter and FPGA Operating Conditions........................................................................................... 6-2
Signal Polarity and FPGA Pin Assignment.............................................................................................. 6-2
Creating a SignalTap II Debug File to Match Your Design Hierarchy .................................................6-3
Debugging JESD204B Link Using System Console.................................................................................6-4
JESD204B IP Core Document Archives.............................................................A-1
JESD204B IP Core Document Revision History................................................B-1
JESD204B IP Core User Guide TOC-3
Altera Corporation

JESD204B IP Core Quick Reference 1
2016.10.31
UG-01142 Subscribe Send Feedback
e Altera JESD204B MegaCore®function is a high-speed point-to-point serial interface intellectual
property (IP).
e JESD204B MegaCore function is part of the MegaCore IP Library, which is distributed with the
Quartus®Prime soware and downloadable from the Altera website at www.altera.com.
Note: For system requirements and installation instructions, refer to Altera Soware Installation &
Licensing.
Table 1-1: Brief Information About the JESD204B IP Core
Item Description
Release
Informa‐
tion
Version 16.0
Release Date May 2016
Ordering Code IP-JESD204B
Product ID 0116
Vendor ID 6AF7
IP Core
Informa‐
tion
Protocol Features
• Joint Electron Device Engineering Council (JEDEC) JESD204B.
01, 2012 standard release specication
• Device subclass:
• Subclass 0—Backwards compatible to JESD204A.
• Subclass 1—Uses SYSREF signal to support deterministic
latency.
• Subclass 2—Uses SYNC_N detection to support determin‐
istic latency.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134

Item Description
IP Core
Informa‐
tion
Core Features • Run-time conguration of parameters L,M, and F
• Data rates up to 12.5 gigabits per second (Gbps)—per JESD204B
specication
• Data rates of up to 15 Gbps—not certied per JESD204B speci‐
cation (uncharacterized support)
• Single or multiple lanes (up to 8 lanes per link)
• Serial lane alignment and monitoring
• Lane synchronization
• Modular design that supports multidevice synchronization
• MAC and PHY partitioning
• Deterministic latency support
• 8B/10B encoding
• Scrambling/Descrambling
• Avalon®Streaming (Avalon-ST) interface for transmit and
receive datapaths
• Avalon Memory-Mapped (Avalon-MM) interface for Congu‐
ration and Status registers (CSR)
• Dynamic generation of simulation testbench
Typical Application • Wireless communication equipment
• Broadcast equipment
• Military equipment
• Medical equipment
• Test and measurement equipment
Device Family Support • Cyclone®V FPGA device families
• Arria®V FPGA device families
• Arria V GZ FPGA device families
• Arria 10 FPGA device families
• Stratix®V FPGA device families
Refer to the device support table and What’s New in Altera IP page
of the Altera website for detailed information.
Design Tools • Qsys parameter editor in the Quartus Prime soware for design
creation and compilation
• TimeQuest timing analyzer in the Quartus Prime soware for
timing analysis
• ModelSim®-Altera, Aldec Riviera-Pro, VCS/VCS MX, and
NCSim soware for design simulation or synthesis
Related Information
•Altera Soware Installation and Licensing
•What's New in Altera IP
•JESD204B IP Core Release Notes
•Errata for JESD204B IP Core in the Knowledge Base
1-2 JESD204B IP Core Quick Reference UG-01142
2016.10.31
Altera Corporation JESD204B IP Core Quick Reference
Send Feedback

•Design Examples for JESD204B IP Core User Guide
•JESD204B IP Core Document Archives on page 7-1
Provides a list of user guides for previous versions of the JESD204B IP core.
UG-01142
2016.10.31 JESD204B IP Core Quick Reference 1-3
JESD204B IP Core Quick Reference Altera Corporation
Send Feedback

About the JESD204B IP Core 2
2016.10.31
UG-01142 Subscribe Send Feedback
e Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or
analog-to-digital (ADC) converters to transfer data to FPGA devices. is unidirectional serial interface
runs at a maximum data rate of 15.0 Gbps. is protocol oers higher bandwidth, low I/O count and
supports scalability in both number of lanes and data rates. e JESD204B IP core addresses multi-device
synchronization by introducing Subclass 1 and Subclass 2 to achieve deterministic latency.
e JESD204B IP core incorporates:
• Media access control (MAC)—data link layer (DLL) block that controls the link states and character
replacement.
• Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.
e JESD204B IP core does not incorporate the Transport Layer (TL) that controls the frame assembly
and disassembly. e TL and test components are provided as part of a design example component where
you can customize the design for dierent converter devices.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134

Figure 2-1: Typical System Application for JESD204B IP Core
e JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional ow of data,
to transmit and receive data on the FPGA fabric interface.
JESD204B TX
IP Core
FPGA
M Converters
1 Link, L Lanes
SYNC_N
M Converters
M Converters
SYNC_N
SYNC_N
M Converters
SYNC_N
JESD204B RX
IP Core
1 Link, L Lanes
1 Link, L Lanes
1 Link, L Lanes
DAC Device
Clock 1
ADC Device
Clock 1
Multi-Device
Synchronization
through Subclass 1
or Subclass 2
Multi-Device
Synchronization
through Subclass 1
or Subclass 2
Logic Device (TX)
Device Clock 2
Logic Device (RX)
Device Clock 2
JESD204B TX
IP Core
JESD204B RX
IP Core
Key features of the JESD204B IP core:
• Data rate of up to 15.0 Gbps (uncharacterized support)
• Run-time JESD204B parameter conguration (L, M, F, S, N, K, CS, CF)
• MAC and PHY partitioning for portability
• Subclass 0 mode for backward compatibility to JESD204A
• Subclass 1 mode for deterministic latency support (using SYSREF) between the ADC/DAC and logic
device
• Subclass 2 mode for deterministic latency support (using SYNC_N) between the ADC/DAC and logic
device
• Multi-device synchronization
2-2 About the JESD204B IP Core UG-01142
2016.10.31
Altera Corporation About the JESD204B IP Core
Send Feedback

Datapath Modes
e JESD204B IP core supports TX-only, RX-only, and Duplex (TX and RX) mode. e IP core is a
unidirectional protocol where interfacing to ADC utilizes the transceiver RX path and interfacing to DAC
utilizes the transceiver TX path.
e JESD204B IP core generates a single link with a single lane and up to a maximum of 8 lanes. If there
are two ADC links that need to be synchronized, you have to generate two JESD204B IP cores and then
manage the deterministic latency and synchronization signals, like SYSREF and SYNC_N, at your custom
wrapper level.
e JESD204B IP core supports duplex mode only if the LMF conguration for ADC (RX) is the same as
DAC (TX) and with the same data rate. is use case is mainly for prototyping with internal serial
loopback mode. is is because typically as a unidirectional protocol, the LMF conguration of converter
devices for both DAC and ADC are not identical.
IP Core Variation
e JESD204B IP core has three core variations:
• JESD204B MAC only
• JESD204B PHY only
• JESD204B MAC and PHY
In a subsystem where there are multiple ADC and DAC converters, you need to use the Quartus Prime
soware to merge the transceivers and group them into the transceiver architecture. For example, to create
two instances of the JESD204B TX IP core with four lanes each and four instances of the JESD204 RX IP
core with two lanes each, you can apply one of the following options:
• MAC and PHY option
1. Generate JESD204B TX IP core with four lanes and JESD204B RX IP core with two lanes.
2. Instantiate the desired components.
3. Use the Quartus Prime soware to merge the PHY lanes.
• MAC only and PHY only option—based on the conguration above, there are a total of eight lanes in
duplex mode.
1. Generate the JESD204B Duplex PHY with a total of eight lanes. (TX skew is reduced in this congu‐
ration as the channels are bonded).
2. Generate the JESD204B TX MAC with four lanes and instantiate it two times.
3. Generate the JESD204B RX MAC with two lanes and instantiate it four times.
4. Create a wrapper to connect the JESD204B TX MAC and RX MAC with the JESD204B Duplex
PHY.
Note: If the data rate for TX and RX is dierent, the transceiver does not allow duplex mode to generate a
duplex PHY. In this case, you have to generate a RX-only PHY on the RX data rate and a TX-only
PHY on the TX data rate.
UG-01142
2016.10.31 Datapath Modes 2-3
About the JESD204B IP Core Altera Corporation
Send Feedback

JESD204B IP Core Conguration
Table 2-1: JESD204B IP Core Conguration
Symbol Description Value
L Number of lanes per converter device 1-8
M Number of converters per device 1-256
F Number of octets per frame 1, 2, 4-256
S Number of transmitted samples per converter per frame 1-32
N Number of conversion bits per converter 1-32
N' Number of transmitted bits per sample (JESD204 word size,
which is in nibble group)
1-32
K Number of frames per multiframe 17/F ≤ K ≤ 32 ; 1-32
CS Number of control bits per conversion sample 0-3
CF Number of control words per frame clock period per link 0-32
HD High Density user data format 0 or 1
LMFC Local multiframe clock (F × K /4) link clock counts (1)
Run-Time Conguration
e JESD204B IP core allows run-time conguration of LMF parameters.
e most critical parameters that must be set correctly during IP generation are the L and F parameters.
Parameter L denotes the maximum lanes supported while parameter F denotes the size of the deskew
buer needed for deterministic latency. e hardware generates during parameterization, which means
that run-time programmability can only fall back from the parameterized and generated hardware, but not
beyond the parameterized IP core.
You can use run-time conguration for prototyping or evaluating the performance of converter devices
with various LMF congurations. However, in actual production,Altera recommends that you generate the
JESD204B IP core with the intended LMF to get an optimized gate count.
For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for both
congurations, you need to generate the JESD204B IP core with maximum F and L, which is L = 4 and F =
2. During operation, you can use the fall back conguration to disable the lanes that are not used in LMF
= 222 mode. You must ensure that other JESD204B congurations like M, N, S, CS, CF, and HD do not
violate the parameter F setting. You can access the Conguration and Status Register (CSR) space to
modify other congurations such as:
• K (multi-frame)
• device and lane IDs
• enable or disable scrambler
• enable or disable character replacement
(1) e value of F x K must be divisible by 4.
2-4 JESD204B IP Core Conguration UG-01142
2016.10.31
Altera Corporation About the JESD204B IP Core
Send Feedback

F Parameter
is parameter indicates how many octets per frame per lane that the JESD204B link is operating in. You
must set the F parameter according to the JESD204B IP Specication for a correct data mapping.
To support the High Density (HD) data format, the JESD204B IP core tracks the start of frame and end of
frame because F can be either an odd or even number. e start of frame and start of multi-frame wrap
around the 32-bits data width architecture. e RX IP core outputs the start of frame (sof[3:0]) and start
of multiframe (somf[3:0]), which act as markers, using the Avalon-ST data stream. Based on these
markers, the transport layer build the frames.
In a simpler system where the HD data format is set to 0, the F will always be 1, 2, 4, 6, 8, and so forth.
is simplies the transport layer design, so you do not need to use the sof[3:0] and somf[3:0]
markers.
Channel Bonding
e JESD204B IP core supports channel bonding—bonded and non-bonded modes.
e channel bonding mode that you select may contribute to the transmitter channel-to-channel skew. A
bonded transmitter datapath clocking provides low channel-to-channel skew as compared to non-bonded
channel congurations.
For Arria 10 devices, refer to the Arria 10 Transceiver User Guide, PMA Bonding chapter, on how to
connect the ATX PLL in bonded conguration and non-bonded conguration. For the non-bonded
conguration, refer to Multi-Channel x1/xN Non-Bonded Example. For bonded conguration, refer to
Implementing x6/xN Bonding Mode.
• In PHY-only mode, you can generate up to 32 channels, provided that the channels are on the same
side. In MAC and PHY integrated mode, you can generate up to 8 channels.
• In bonded channel conguration, the lower transceiver clock skew for all channels result in a lower
channel-to-channel skew. You must use contiguous channels when you select bonded mode. For Stratix
V, Arria V, and Cyclone V devices, the JESD204B IP core automatically selects between ×6, ×N or
feedback compensation (_compensation) bonding depending on the number of transceiver channels
you set. For Arria 10 devices, refer to Table 2-4 for the clock network selection. Refer to Channel
Bonding section of the Arria 10 Transceiver PHY User Guide for more information about PMA
Bonding.
• In non-bonded channel conguration, the transceiver clock skew is higher and latency is unequal in
the transmitter phase compensation FIFO for each channel. is may result in a higher channel-to-
channel skew.
Table 2-2: Maximum Number of Lanes (L) Supported in Bonded and Non-Bonded Mode
Device Family Core Variation Bonding Mode Conguration Maximum Number of
Lanes (L)
Arria V
PHY only Bonded 32 (2)
Non-bonded 32 (2)
MAC and PHY Bonded 6
Non-bonded 8
(2) e maximum lanes listed here is for conguration simplicity. Refer to the Altera Transceiver PHY User Guide
for the actual number of channels supported.
UG-01142
2016.10.31 Channel Bonding 2-5
About the JESD204B IP Core Altera Corporation
Send Feedback

Device Family Core Variation Bonding Mode Conguration Maximum Number of
Lanes (L)
Arria V GZ
Arria 10
Stratix V
PHY only Bonded 32 (2)
Non-bonded 32 (2)
MAC and PHY Bonded 8
Non-bonded 8
Table 2-3: Clock Network Selection for Bonded Mode
Device Family L ≤ 6 L > 6
Arria 10 ×6 ×N (3)
Stratix V ×6 feedback compensation
Arria V ×N ×N
Arria V GZ ×6 feedback compensation
Cyclone V ×N ×N
Related Information
•Arria 10 Device Datasheet
•Arria 10 Transceiver PHY User Guide
Performance and Resource Utilization
Table 2-4: JESD204B IP Core FPGA Performance
Device Family PMA Speed
Grade
FPGA Fabric
Speed Grade
Data Rate
Link Clock FMAX
(MHz)
Enable Hard PCS
(Gbps)
Enable Soft PCS
(Gbps) (4)
Cyclone V
5<Any supported
speed grade>
1.0 to 5.0 — 125.00
6 6 or 7 1.0 to 3.125 — 78.125
Arria V GX/SX <Any supported
speed grade>
<Any supported
speed grade>
1.0 to 6.55 — (5) 163.84
(3) Bonded mode is not supported for data rate > 15 Gbps. Refer to the Arria 10 datasheet for the maximum
data rate and channel span supported by the ×N clock network and the transceiver power supply
operating condition for your device.
(4) Select Enable So PCS to achieve maximum data rate. For the TX IP core, enabling so PCS incurs an
additional 3–8% increase in resource utilization. For the RX IP core, enabling so PCS incurs an additional
10–20% increase in resource utilization.
2-6 Performance and Resource Utilization UG-01142
2016.10.31
Altera Corporation About the JESD204B IP Core
Send Feedback

Device Family PMA Speed
Grade
FPGA Fabric
Speed Grade
Data Rate
Link Clock FMAX
(MHz)
Enable Hard PCS
(Gbps)
Enable Soft PCS
(Gbps) (4)
Arria V GT/ST <Any supported
speed grade>
<Any supported
speed grade>
1.0 to 6.55 4.0 to 7.5
(PMA direct) (5)
187.50
Arria V GZ 2 3 2.0 to 9.9 — (5) 247.50
3 4 2.0 to 8.8 — (5) 220.00
Arria 10
1 1 2.0 to 12.0 2.0 to 15.0 (6) (data rate /
40)
2 1 2.0 to 12.0 2.0 to 15.0 (6) (data rate /
40)
2 2 2.0 to 9.83 2.0 to 15.0 (6) (data rate /
40)
3 1 2.0 to 12.0 2.0 to 14.2 (6) 355.00
3 2 2.0 to 9.83 2.0 to 14.2 (6) 355.00
4 3 2.0 to 8.83 2.0 to 12.5 312.50
Stratix V
1 1 or 2 2.0 to 12.2 2.0 to 12.5 312.50
2 1 or 2 2.0 to 12.2 2.0 to 12.5 312.50
2 3 2.0 to 9.8 2.0 to 12.5 (7) 312.50
3 1, 2, 3, or 4 2.0 to 8.5 2.0 to 8.5 212.50
e following table lists the resources and expected performance of the JESD204B IP core. ese results
are obtained using the Quartus Prime soware targeting the following Altera FPGA devices:
• Cyclone V : 5CGTFD9E5F31I7
• Arria V : 5AGXFB3H4F35C5
• Arria V GZ : 5AGZME5K2F40C3
• Arria 10 : 10AX115H2F34I2SGES
• Stratix V : 5SGXEA7H3F35C3
(4) Select Enable So PCS to achieve maximum data rate. For the TX IP core, enabling so PCS incurs an
additional 3–8% increase in resource utilization. For the RX IP core, enabling so PCS incurs an additional
10–20% increase in resource utilization.
(5) Enabling So PCS does not increase the data rate for the device family and speed grade. You are
recommended to select the Enable Hard PCS option.
(6) Refer to the Arria 10 Device Datasheet for the maximum data rate supported across transceiver speed grades
and transceiver power supply operating conditions.
(7) When using So PCS mode at 12.5 Gbps, the timing margin is very limited. You are advised to enable high
tter eort, register duplication, and register retiming to improve timing performance.
UG-01142
2016.10.31 Performance and Resource Utilization 2-7
About the JESD204B IP Core Altera Corporation
Send Feedback

All the variations for resource utilization are congured with the following parameter settings:
Table 2-5: Parameter Settings To Obtain the Resource Utilization Data
Parameter Setting
JESD204B Wrapper Base and PHY
JESD204B Subclass 1
Data Rate 5 Gbps
PCS Option Enabled Hard PCS
PLL Type • ATX (for 10 series devices)
• CMU (for V series devices)
Bonding Mode Non-bonded
Reference Clock Frequency 125.0 MHz
Octets per frame (F) 1
Enable Scrambler (SCR) O
Enable Error Code Correction (ECC_EN) O
Table 2-6: JESD204B IP Core Resource Utilization
e numbers of ALMs and logic registers in this table are rounded up to the nearest 10.
Note: e resource utilization data are extracted from a full design which includes the Altera Transceiver
PHY Reset Controller IP Core. us, the actual resource utilization for the JESD204B IP core
should be smaller by about 15 ALMs and 20 registers.
Device Family Data Path Number of
Lanes (L)
ALMs ALUTs Logic
Registers
Memory Block
(M10K/M20K) (8) (9)
Cyclone V
RX
1 1018 1512 1209 1
2 1558 2298 1840 2
4 2766 3951 3101 4
8 5202 7398 5621 8
TX
1 713 1147 949 0
2 863 1417 1065 0
4 1188 1930 1300 0
8 1706 2837 1767 0
(8) M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.
(9) e Quartus Prime soware may auto-t to use MLAB when the memory size is too small. Conversion from
MLAB to M20K or M10K was performed for the numbers listed above.
2-8 Performance and Resource Utilization UG-01142
2016.10.31
Altera Corporation About the JESD204B IP Core
Send Feedback

Device Family Data Path Number of
Lanes (L)
ALMs ALUTs Logic
Registers
Memory Block
(M10K/M20K) (8) (9)
Arria V
RX
1 1021 1512 1208 1
2 1554 2298 1839 2
4 2779 3951 3098 4
8 5190 7398 5612 8
TX
1 713 1147 949 0
2 868 1417 1066 0
4 1192 1930 1299 0
8 1716 2853 1766 0
Arria V GZ
RX
1 1046 1519 1225 0
2 1610 2323 1871 0
4 2883 4017 3161 0
8 5418 7519 5752 0
TX
1 710 1150 948 0
2 927 1489 1085 0
4 1348 2134 1359 0
8 2111 3355 1907 0
Arria 10
RX
1 1050 1499 1216 0
2 1590 2247 1843 0
4 2826 3845 3098 0
8 5314 7147 5589 0
TX
1 740 1121 949 0
2 921 1404 1071 0
4 1298 1937 1310 0
8 1946 2938 1790 0
(8) M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.
(9) e Quartus Prime soware may auto-t to use MLAB when the memory size is too small. Conversion from
MLAB to M20K or M10K was performed for the numbers listed above.
UG-01142
2016.10.31 Performance and Resource Utilization 2-9
About the JESD204B IP Core Altera Corporation
Send Feedback

Device Family Data Path Number of
Lanes (L)
ALMs ALUTs Logic
Registers
Memory Block
(M10K/M20K) (8) (9)
Stratix V
RX
1 1045 1519 1225 0
2 1609 2323 1874 0
4 2871 4017 3160 0
8 5419 7519 5747 0
TX
1 714 1150 948 0
2 928 1489 1086 0
4 1345 2134 1359 0
8 2105 3355 1908 0
Related Information
•JESD204B IP Core Parameters on page 3-15
•Fitter Resources Reports in the Quartus Prime Help
Information about the Quartus Prime resource utilization reporting, including ALMs needed.
(8) M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.
(9) e Quartus Prime soware may auto-t to use MLAB when the memory size is too small. Conversion from
MLAB to M20K or M10K was performed for the numbers listed above.
2-10 Performance and Resource Utilization UG-01142
2016.10.31
Altera Corporation About the JESD204B IP Core
Send Feedback

Getting Started 3
2016.10.31
UG-01142 Subscribe Send Feedback
e JESD204B IP core is part of the MegaCore IP Library distributed with the Quartus Prime soware and
downloadable from the Altera website at www.altera.com.
Related Information
•Altera Soware Installation & Licensing
•Introduction to Altera IP Cores
Provides general information about all Altera FPGA IP cores, including parameterizing, generating,
upgrading, and simulating IP cores.
•Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for soware or IP version upgrades.
•Project Management Best Practices
Guidelines for ecient management and portability of your project and IP les.
Introduction to Altera FPGA IP Cores
Altera and strategic IP partners oer a broad portfolio of congurable IP cores optimized for Altera FPGA
devices.
e Quartus Prime soware installation includes the Altera FPGA IP library. Integrate optimized and
veried Altera FPGA IP cores into your design to shorten design cycles and maximize performance. e
Quartus Prime soware also supports integration of IP cores from other sources. Use the IP Catalog
(Tools > IP Catalog) to eciently parameterize and generate synthesis and simulation les for your
custom IP variation. e Altera FPGA IP library includes the following types of IP cores:
• Basic functions
• DSP functions
• Interface protocols
• Low power functions
• Memory interfaces and controllers
• Processors and peripherals
is document provides basic information about parameterizing, generating, upgrading, and simulating
stand-alone IP cores in the Quartus Prime soware.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134

Figure 3-1: IP Catalog
Select to Parameterize
Right-Click for Details
Search for Installed IP
Filter IP by
Device
Installing and Licensing IP Cores
e Quartus Prime soware installation includes the Altera FPGA IP library. is library provides useful
IP core functions for your production use without the need for an additional license. Some MegaCore IP
functions in the library require that you purchase a separate license for production use. e OpenCore®
feature allows evaluation of any Altera FPGA IP core in simulation and compilation in the Quartus Prime
soware. Upon satisfaction with functionality and performance, visit the Self Service Licensing Center to
obtain a license number for any Altera FPGA product.
e Quartus Prime soware installs IP cores in the following locations by default:
Figure 3-2: IP Core Installation Path
intelFPGA(_pro*)
quartus - Contains the Quartus Prime software
ip - Contains the IP library and third-party IP cores
altera - Contains the IP library source code
<IP core name> - Contains the IP core source files
Table 3-1: IP Core Installation Locations
Location Software Platform
<drive>:\intelFPGA_pro\quartus\ip\
altera
Quartus Prime Pro Edition Windows
3-2 Installing and Licensing IP Cores UG-01142
2016.10.31
Altera Corporation Getting Started
Send Feedback

Location Software Platform
<drive>:\intelFPGA\quartus\ip\altera Quartus Prime Standard
Edition
Windows
<home directory>:/intelFPGA_pro/
quartus/ip/altera
Quartus Prime Pro Edition Linux
<home directory>:/intelFPGA/quartus/
ip/altera
Quartus Prime Standard
Edition
Linux
OpenCore Plus IP Evaluation
e free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. Purchase a license for MegaCore IP cores if you decide to take your design to
production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming les for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indenitely. is operation
requires a connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
Related Information
•Quartus Prime Licensing Site
•Quartus Prime Installation and Licensing
Upgrading IP Cores
Any IP variations that you generate from a previous version or dierent edition of the Quartus Prime
soware, may require upgrade before compilation in the current soware edition or version.
e Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool
or Project > Upgrade IP Components to upgrade outdated IP cores.
UG-01142
2016.10.31 OpenCore Plus IP Evaluation 3-3
Getting Started Altera Corporation
Send Feedback

Figure 3-3: IP Upgrade Alert in Project Navigator
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or
unsupported for an IP variation in the project. Upgrade IP variations that require upgrade before compila‐
tion in the current version of the Quartus Prime soware.
Note: Upgrading IP cores may append a unique identier to the original IP core entity name(s), without
similarly modifying the IP instance name. ere is no requirement to update these entity references
in any supporting Quartus Prime le, such as the Quartus Prime Settings File (.qsf), Synopsys
Design Constraints File (.sdc), or SignalTap File (.stp), if these les contain instance names. e
Quartus Prime soware reads only the instance name and ignores the entity name in paths that
specify both names. Use only instance names in assignments.
Table 3-2: IP Core Upgrade Status
IP Core Status Description
IP Upgraded Indicates that your IP variation uses the latest version of the IP core.
IP Upgrade Optional Indicates that upgrade is optional for this IP variation in the current version of
the Quartus Prime soware. Optionally, upgrade this IP variation to take
advantage of the latest development of this IP core. Retain previous IP core
characteristics by declining to upgrade. Refer to the Description for details
about IP core version dierences. If you do not upgrade the IP, the IP variation
synthesis and simulation les remain unchanged, and you cannot modify
parameters until upgrading.
3-4 Upgrading IP Cores UG-01142
2016.10.31
Altera Corporation Getting Started
Send Feedback