Altera MAX 10 series User manual

MAX 10 User Flash Memory User Guide
Last updated for Quartus Prime Design Suite: 16.0
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2016.05.02 101 Innovation Drive
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Contents
MAX 10 User Flash Memory Overview...............................................................1-1
MAX 10 UFM Architecture and Features...........................................................2-1
UFM and CFM Array Size..........................................................................................................................2-1
UFM Memory Organization Map.............................................................................................................2-2
UFM Block Diagrams..................................................................................................................................2-2
UFM Operating Modes...............................................................................................................................2-5
MAX 10 UFM Design Considerations................................................................3-1
Guideline: UFM Power Supply Requirement..........................................................................................3-1
Guideline: Program and Read UFM with JTAG..................................................................................... 3-1
Guideline: UFM Content Initialization.................................................................................................... 3-2
Guideline: Erase Before Program.............................................................................................................. 3-2
MAX 10 UFM Implementation Guides.............................................................. 4-1
Altera On-Chip Flash IP Core....................................................................................................................4-1
UFM Avalon-MM Operating Modes........................................................................................................4-1
UFM Read Status and Control Register........................................................................................4-1
UFM Write Control Register..........................................................................................................4-2
UFM Program (Write) Operation.................................................................................................4-2
UFM Sector Erase Operation......................................................................................................... 4-4
UFM Page Erase Operation............................................................................................................4-4
UFM Read Operation......................................................................................................................4-5
UFM Burst Read Operation............................................................................................................4-7
Flash Initialization Files............................................................................................................................4-12
Altera On-Chip Flash IP Core References..........................................................5-1
Altera On-Chip Flash Parameters............................................................................................................. 5-1
Altera On-Chip Flash Signals.....................................................................................................................5-2
Altera On-Chip Flash Registers................................................................................................................. 5-4
MAX 10 User Flash Memory User Guide Archive.............................................A-1
Document Revision History for MAX 10 User Flash Memory User Guide...... B-1
TOC-2
Altera Corporation

MAX 10 User Flash Memory Overview 1
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Altera®MAX®10 FPGAs offer a user flash memory (UFM) block that stores non-volatile information.
The UFM provides an ideal storage solution that you can access using the Avalon Memory Mapped
(Avalon-MM) slave interface to UFM.
The UFM block also offers the following features.
Features Capacity
Endurance Counts to at least 10,000 program/erase cycles
Data retention (after 10,000
program/erase cycles) • 20 years at 85 ºC
• 10 years at 100 ºC
Maximum operating frequency • Serial interface
• 10M02,10M04, 10M08, 10M16, 10M25: 7.25 MHz
• 10M40, 10M50: 4.81 MHz
• Parallel interface
• 10M02: 7.25 MHz
• 10M04, 10M08, 10M16, 10M25, 10M40, 10M50: 116 MHz
Data length Stores data of up to 32 bits length in parallel
Related Information
•Utilizing the User Flash Memory (UFM) on Max 10 Devices with a Nios II Processor
•Putting Altera MAX Series in Hibernation Mode Using User Flash Memory
•MAX 10 User Flash Memory User Guide Archive on page 6-1
Provides a list of user guides for previous versions of the Altera On-Chip Memory IP core.
©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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MAX 10 UFM Architecture and Features 2
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The UFM architecture of MAX 10 devices is a combination of soft and hard IPs. You can only access the
UFM using the Altera On-Chip Flash IP core in the Quartus®Prime software.
UFM and CFM Array Size
Each array is organized as various sectors.
A page is the smallest amount of flash memory that you can erase at one time. A sector contains a number
of pages. You can erase each page or sector independently.
The Altera On-Chip Flash IP core also gives you access to configuration flash memory (CFM) based on
your specification in the parameter editor.
Table 2-1: UFM and CFM Array Size
This table lists the dimensions of the UFM and CFM arrays.
Device
Pages per Sector
Page Size
(Kb)
Total User
Flash
Memory Size
(Kb) (1)
Total Configuration
Memory Size (Kb) (1)
UFM1 UFM0 CFM2
(Image 2)
CFM1
(Image 2)
CFM0
(Image 1)
10M02 3 3 0 0 34 16 96 544
10M04 0 8 41 29 70 16 1,248 2,240
10M08 8 8 41 29 70 16 1,376 2,240
10M16 4 4 38 28 66 32 2,368 4,224
10M25 4 4 52 40 92 32 3,200 5,888
10M40 4 4 48 36 84 64 5,888 10,752
10M50 4 4 48 36 84 64 5,888 10,752
(1) The maximum possible value, which is dependent on the mode you select.
©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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9001:2008
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101 Innovation Drive, San Jose, CA 95134

UFM Memory Organization Map
The address scheme changes based on the configuration mode you specify in the Altera On-Chip Flash
parameter editor.
The following tables show the dynamic UFM support based on different configuration mode and MAX 10
variant.
Table 2-2: Dynamic Flash Size Support: Flash and Analog Variants
Configuration UFM1 UFM0 CFM2
(Image 2)
CFM1
(Image 2)
CFM0
(Image 1)
Dual compressed images UFM space UFM space — — —
Single uncompressed image UFM space UFM space UFM space — —
Single compressed image UFM space UFM space UFM space UFM space —
Single uncompressed image with
memory initialization UFM space UFM space — — —
Single compressed image with
memory initialization UFM space UFM space — — —
Table 2-3: Dynamic Flash Size Support: Compact Variant
Configuration UFM1 UFM0 CFM2
(Image 2)
CFM1
(Image 2)
CFM0
(Image 1)
Dual compressed images Not available
Single uncompressed image UFM space UFM space — — —
Single compressed image UFM space UFM space — — —
Single uncompressed image with
memory initialization Not available
Single compressed image with
memory initialization Not available
UFM Block Diagrams
This figure shows the top level view of the Altera On-Chip Flash IP core block diagram. The Altera On-
Chip Flash IP core supports both parallel and serial interfaces for MAX 10 FPGAs.
2-2 UFM Memory Organization Map UG-M10UFM
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Figure 2-1: Altera On-Chip Flash IP Core Block Diagram
UFM Block Interface
Avalon-MM Slave Controller
(Control)
Control Register
Status Register
altera_onchip_flash
Avalon-MM Slave
Serial Controller
(Data)
Avalon-MM
Avalon-MM Slave
Parallel Controller
(Data)
Avalon-MM Avalon-MM
This IP block has two Avalon-MM slave controllers:
• Data—a wrapper of the UFM block that provides read and program accesses to the flash.
• Control—the CSR and status register for the flash, which is required only for program and erase
operations.
These figures show the detailed overview of the Avalon-MM interface during read and program (write)
operation.
Figure 2-2: Altera On-Chip Flash IP Core Avalon-MM Slave Read and Program (Write) Operation in
Parallel Mode
This figure shows the standard interface for MAX 10 devices in parallel mode.
Avalon-MM Slave
Parallel Controller
(Data)
Avalon-MM Slave
Controller
(Control)
Control Register
Status Register
altera_onchip_flash
UFM
Block
Interface
UFM
Block I/F
clock
reset_n
addr[x:0]
read
readdata[31:0]
write
writedata[31:0]
waitrequest
readdatavalid
burstcount[x:0]
clock
reset_n
addr
read
readdata[31:0]
write
writedata[31:0]
read
write
read/
write
read
internal
internal
external
external
Note: The maximum frequency for all devices in parallel mode, except for 10M02, is 116 MHz. The
maximum frequency for 10M02 devices is 7.25 MHz.
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Figure 2-3: Altera On-Chip Flash IP Core Avalon-MM Slave Read and Program (Write) Operation in
Serial Mode
This figure shows the standard interface for MAX 10 devices in serial mode.
Avalon-MM Slave
Serial Controller
(Data)
Avalon-MM Slave
Controller
(Control)
Control Register
Status Register
altera_onchip_flash
UFM
Block
Interface
UFM
Block I/F
clock
reset_n
addr[x:0]
read
readdata
write
writedata
waitrequest
readdatavalid
burstcount[x:0]
clock
reset_n
addr
read
readdata[31:0]
write
writedata[31:0]
read
write
read/
write
read
internal
internal
external
external
These figures show the detailed overview of the Avalon-MM interface during read only operation.
Figure 2-4: Altera On-Chip Flash IP Core Avalon-MM Slave Read Only Operation in Parallel Mode
Avalon-MM Slave
Parallel Controller
(Data)
altera_onchip_flash
UFM
Block
Interface
UFM
Block I/F
clock
reset_n
addr[x:0]
read
readdata[31:0]
waitrequest
readdatavalid
burstcount[x:0]
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Figure 2-5: Altera On-Chip Flash IP Core Avalon-MM Slave Read Only Operation in Serial Mode
Avalon-MM Slave
Serial Controller
(Data)
altera_onchip_flash
UFM
Block
Interface
UFM
Block I/F
clock
reset_n
addr[x:0]
read
readdata
waitrequest
readdatavalid
burstcount[x:0]
UFM Operating Modes
The UFM block offers the following operating modes:
• Read
• Burst read
• Program (Write)
• Sector erase
• Page erase
• Sector write protection
You can choose one of the following access modes in the Altera On-Chip Flash parameter editor to read
and control the operations.
• Read and program mode—this mode allows both data and control slave interface. This mode is
applicable for both UFM and CFM sectors.
• Read only mode—this mode allows only data slave interface, and restricted to only read operations.
This mode is applicable for both UFM and CFM sectors.
• Hidden—this mode does not allow any read or program (write) operations. This mode is applicable
only for CFM sectors.
The following table shows the comparison between parallel and serial modes.
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Table 2-4: Comparison between Parallel Mode and Serial Mode
Feature Parallel Mode Serial Mode
Avalon-MM Data Interface Parallel mode with 32-bit
data bus Serial mode with 32 bits based burst count
Access Mode • Read and program
• Read only
• Hidden
• Read and program
• Read only
• Hidden
Read Mode • Incrementing burst
read
• Wrapping burst read
Incrementing burst read only
Program (Write) Operation Single 32-bit parallel
program operation Single 32-bit serial program operation
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MAX 10 UFM Design Considerations 3
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There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Guideline: UFM Power Supply Requirement
During UFM and CFM operations, make sure to follow the maximum slew rate requirement for power
supply ramp down. This setting prevents device damage in case of power loss.
Table 3-1: Maximum Slew Rate Requirement
Device Maximum Slew Rate
Single-supply device 0.073V/µs
Multi-supply device 0.023V/µs
<0.023V/µs
Multi-Supply Device
2.5V
0V
<0.073V/µs
Single-Supply Device
0V
3.3V
Guideline: Program and Read UFM with JTAG
You can program UFM using JTAG interface version IEEE Standard 1149.1.
©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134