AMIMON AMN12310 WHDI User manual

Version 0.5
AMIMON Confidential 1
AMN12310
WHDI
TM
Receiver
Module Datasheet
Version 0.5

Important Notice
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AMIMON Confidential 2
I portant Notice
AMIMON Ltd. reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant
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AMIMON's standard warranty. Testing and other quality control techniques are used to the extent AMIMON deems necessary to
support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not
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Contact Us
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Tel: [phone]
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TEL [phone]
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Revision History
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AMIMON Confidential 3
Revision History
Version Date Description
0.1 - Initial Release
0.2 15.6.08 Revision
Board Mechanical size
Reset and Wake-up Timer modified
RF frame modified
Power switch on RF removed
Operating Conditions and Electrical Characteristics modified
AMN11310 Block Diagram modified
Unhide Certification & Compliance
Power requirements
Mini-MAC changed to MAC.
WHDI Module Configuration
Connector Schematics
Stack up
Test Points and Jumpers
0.3 20.7.08 Fixed link to STMF datasheet p-18.
Fixed Table 1: Rx WHDI Connector Pin List
Fixed recommended stack up table p- 29
0.4 03.08.08 Add section MCLK Specifications
0.5 2.9.08 Change in FCC chapter

Table of Contents
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Table of Contents
Important Notice......................................................................................................2
Revision History ......................................................................................................3
Table of Contents ....................................................................................................4
List of Figures .........................................................................................................6
List of Tables ..........................................................................................................6
Chapter 1 ..........................................................................................................8
Introduction ..........................................................................................................8
1.1 Features ...................................................................................................................................................8
Chapter 2 ........................................................................................................11
Overview ........................................................................................................11
2.1 AMN2210 WHDI Baseband Receiver ....................................................................................................12
2.2 STM32F MAC µController......................................................................................................................12
2.3 AMN3210 WHDI
TM
5GHz Transceiver ...................................................................................................13
2.4 Power Amplifier (PA).............................................................................................................................13
2.5 Board Connector (WHDI
TM
Connector).................................................................................................13
2.6 Clocks ....................................................................................................................................................13
2.6.1 40MHz Crystal Oscillator ................................................................................................................. 13
2.6.2 40Mhz Digital Clock......................................................................................................................... 13
2.6.3 10Mhz Micro Controller Clock ......................................................................................................... 13
2.7 CY22150 External Video PLL ................................................................................................................14
Chapter 3 ........................................................................................................15
Interfaces ........................................................................................................15
3.1 Video Data Input and Conversions.......................................................................................................15
3.2 Video Interface Output Timing Diagram ...............................................................................................16
3.2.1 Timing Requirements ...................................................................................................................... 16
3.3 Audio Data Capture ...............................................................................................................................17
S
S

Table of Contents
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3.3.1 I
2
S Bus Specification ....................................................................................................................... 18
3.4 Management Buses and Connectors ...................................................................................................21
3.4.1 Two-Wire Serial Bus Interface......................................................................................................... 21
3.4.2 Interrupts.......................................................................................................................................... 22
3.4.3 WHDI Module Configuration............................................................................................................ 23
3.5 Reset and Wake-up Timer .....................................................................................................................23
Chapter 4 ........................................................................................................26
WHDI Connector Pins ............................................................................................26
4.1 Signals ...................................................................................................................................................26
4.2 Connector Schematics..........................................................................................................................27
4.3 Pin List...................................................................................................................................................28
Chapter 5 ........................................................................................................30
Electrical Specifications ..........................................................................................30
5.1 Operating Conditions and Electrical Characteristics ..........................................................................30
Chapter 6 ........................................................................................................32
Design Guidelines .................................................................................................32
6.1 Digital Layout Recommendation ..........................................................................................................32
6.1.1 Stack Up .......................................................................................................................................... 32
6.1.2 General Guidelines.......................................................................................................................... 33
6.1.3 WHDI Lines...................................................................................................................................... 33
6.1.4 Power and Ground .......................................................................................................................... 33
6.2 RF Design Recommendation ................................................................................................................33
6.2.1 RF Components .............................................................................................................................. 33
6.2.2 Power Management ........................................................................................................................ 33
6.3 Test Points and Jumpers ......................................................................................................................34
Chapter 7 ........................................................................................................36
Mechanical Dimensions ..........................................................................................36
7.1 RF Shield frame and cover....................................................................................................................38

List of Figures
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List of Figures
Figure 1: AMN12310 Block Diagram....................................................................................................................... 11
Figure 2: WHDI Baseband Receiver Chipset.......................................................................................................... 12
Figure 3: Video Data Receiver Path........................................................................................................................ 15
Figure 4: Timing Diagram ........................................................................................................................................ 17
Figure 5: I
2
S Simple System Configurations and Basic Interface Timing ............................................................... 18
Figure 6: I
2
S Output Timings ................................................................................................................................... 19
Figure 7: Two-Wire/Application-MAC Connection................................................................................................... 21
Figure 8: Two-Wire MAC Write Commands ............................................................................................................ 22
Figure 9: Two-Wire Read Command....................................................................................................................... 22
Figure 10: Reset Time Diagram .............................................................................................................................. 23
Figure 11: Reset Mechanism .................................................................................................................................. 24
Figure 12: WHDI Connector .................................................................................................................................... 27
Figure 13: Mechanical Dimensions Top View ......................................................................................................... 36
Figure 14: Mechanical Dimensions Bottom View.................................................................................................... 37
Figure 15: RF-Shield Frame .................................................................................................................................... 38
Figure 16: RF-Shield Cover..................................................................................................................................... 38
List of Tables
 Fixed Table 1: Rx WHDI Connector Pin List ........................................................................................ 3
Table 2: Common Supported Video Input Resolutions ........................................................................................... 16
Table 3: Video Channel Mapping ............................................................................................................................ 16
Table 4: Video Interface .......................................................................................................................................... 16
Table 5: Audio Interface Output Timing................................................................................................................... 19
Table 6: MCLK timing. ............................................................................................................................................. 20
Table 7: Device Addresses ..................................................................................................................................... 21
Table 8: Reset Timing Requirements...................................................................................................................... 24
Table 9: WHDI Connector Signals .......................................................................................................................... 26
Table 10: Rx WHDI Connector Pin List ................................................................................................................... 28
Table 11: Absolute Maximum Ratings over Operating Case Temperature Range................................................. 30
Table 12: Recommended Operating Conditions ..................................................................................................... 30

List of Tables
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Table 13: Electrical Characteristics over Recommended Range of Supply Voltage and Operating
Conditions........................................................................................................................................... 30
Table 14: Digital Layout Recommendation ............................................................................................................. 32

Introduction
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Chapter 1
Introduction
The AMN12310 is the second generation of WHDI
TM
receiver board. It is based on AMIMON's WHDI receiver
chipset: the AMN2210 baseband receiver and the AMN3210 RFIC receiver.
The AMN12310 WHDI
TM
wireless receiver module, together with the AMN11310 wireless transmitter module,
presents the ultimate solution for converting any High Definition (HD) system into a wireless one. These add-on
modules enable wireless A/V applications that easily fit into the living room and eliminate traditional A/V wiring.
The perfect HD video and audio quality and the high robustness are unmatched by any other wireless technology,
and present a true alternative to cable. The WHDI system transmits uncompressed video and audio streams
wirelessly and thus simplifies and eliminates system issues, such as: lip-sync, large buffers and other burdens
like retransmissions or error propagation.
1.1 Features
•Uncompressed and uncompromised HD video quality, using AMIMON's baseband chipsets:
AMN2210: WHDITM Baseband Receiver
AMN3210: WHDITM RFIC Receiver
•WHDI – Wireless High Definition Interface:
Digital video: 30-bit RGB or YCrCb
Digital audio: I2S and SPDIF
Two-wire serial bus slave interface
One interrupt line
•Supports any uncompressed video resolutions, including:
HD: 720p, 1080i, 1080p, 576i, 576p, 480p, 480i
PC: VGA (640x480), SVGA (800x600), XGA (1024x768)
Panel: 854x800, 1280x768, 1366x768
•Audio:
Up to 3Mbps audio stream:
I2S: Two PCM channels (sampled up to 48 KHz x 24 bit)
SPDIF: Including AC-3, DTS
•Strong 256-bit AES encryption
•User-defined two-way channel with minimum 10 Kbps for data and control
•Less than 1mSec latency between source and sink

Introduction
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•Small mechanical footprint:
With PCB integrated antennas
•RF characteristics:
MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth.
Coexists with 802.11a/n and 5.8GHz cordless devices.
Support for Automatic Transmission Power Control (ATPC).
No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for
almost any room.
14mW typical transmission power of the uplink channel.
Maximum 45mW transmission power of the uplink channel.
Minimum -65 dBm received signal power for successful operation
•Current consumption
Option to to disable 40MHz digital clock to AMN2210 from AMN3210.
•Power requirements:
3.3V (±5%), ~4.2W
•Certification & Compliance:
FCC
This product is for indoor use only in the band of 5.15-5.25GHz.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must accept any
interference received, including interference that may cause undesired operation.
Any changes or modifications not expressly approved by Amimon for compliance could void the
user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation. This equipment generates, uses and can
radiate radio frequency energy and, if not installed and used in accordance with the instructions, may
cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following
measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
Consult the dealer or an experienced radio/TV technician for help.
MIC
This device has complied with Japan Radio law:
Item 19-11 of Article 1 paragraph 1 of certification ordinance.
Item 19-3 of Article 1 paragraph 1 of certification ordinance.

Introduction
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•Caution: The module should be positioned so that personnel in the area for prolonged periods may safely
remain at least 20 cm (8 in) in an uncontrolled environment from the module.

Overview
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Chapter 2
Overview
The AMN12310 WHDI Video Display Unit (VDU) is designed to be at the receiver end of the WHDI downstream.
The AMN12310 receives wireless downstream transmission, demodulates it and regenerates the video, audio
and control content transmitted by the AMN11310 WHDI transmitter. The receiver works at the 5GHz unlicensed
band. Figure 1 displays a block diagram of the AMN12310. It has an MIMO design of five wireless input channels,
and one slow rate output wireless channel, which generates an upstream channel for data content transmissions.
The outputs from the VDU are digital uncompressed video, digital audio and control, all via the WHDI connector.
The MAC uC is responsible for the control and the management.
80 Pin WHDI
TH
Connector
SPI
VIDEO
Control
TwoWire
RESET
Interrupt
Audio
Int
AMN2210
WHDI
TM
Baseband Receiver
CLK
Out
CLK
In
Control
Two-Wire
40M XTAL
AMN3210
uC
MAC
CY22150
Video
PLL
PA
rssi
clken
3.3V
RX_ANT0_P/N
Clk40M_OE
CLK40M DIG_CLK (40M)
3.3V_RAIL
3.3V
S_RESET_B
UC_MAC_CLK (Clo ck 10MHz)
PIN#15
PIN 5# PIN#6 1
PIN #37 -40
PIN #62
fb
Figure 1: AMN12310 Block Diagram

Overview
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The main building blocks of the AMN12310 are as follows:
•AMN2210 WHDI Baseband Receiver, as briefly described on page 12
•STM32F MAC µController, as briefly described on page 12
•AMN3210 WHDI
TM
5GHz Transceiver, as briefly described on page 13
•Power Amplifier (PA), as briefly described on page 13
•Board Connector (WHDI
TM
Connector), as described on page 13
•Clock enable switch for input 40M clock to AMN2110, as described on page 13
•40MHz Crystal Oscillator, as described on page 13
•CY22150 External Video PLL, as described on page 14
2.1 AMN2210 WHDI Baseband Receiver
The AMN2210 WHDI
TM
baseband receiver chip is the heart of the AMN12310 WHDI Receiver module. The
AMN2210 interfaces the A/V source through the WHDI connector, and is controlled on board by the MAC uC.
WHDI
TM
Baseband Receiver
AMN2210
Downlink
De-modulation
Uplink
modulation
Video
Interface
Audio
Interface
Control
ADC
DAC
ADC
ADC
ADC
ADC
Video
Sink
Audio
Sink
MiniMAC
MicroController
Figure 2: WHDI Baseband Receiver Chipset
The AMN2210 is based on MIMO technology receiving up to five input channels. Five analog-to-digital converters
and one digital-to-analog converter are embedded within the chip.
The AMN2210 internal PLL accepts an input clock frequency of 40MHz. The input frequency is multiplied and
then used as an internal system clock.
2.2 STM32F MAC µController
The STM32F Microcontroller is based on an ARM 32-bit Cortex™-M3 CPU, with 128 Kbytes of embedded Flash
memory. It is used as an external microcontroller for implementing the MAC layer of the WHDI link.
The STM32F Internal PLL accepts an input clock frequency of 10MHz and generates an internal 60MHz system
clock. The STM32F also has the option to work with an internal 4-to-16 MHz crystal oscillator.

Overview
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2.3 AMN3210 WHDI
TM
5GHz Transceiver
The VDU uses AMN3210 WHDI receiver chip. The AMN3210 is a fully integrated Zero-IF MIMO receiver
specifically designed for WHDI applications using OFDM modulation for single-band 4.9GHz to 5.9GHz. The
device includes:
•Five Complete Downlink Zero-IF Receivers
•One Uplink Direct Conversion Transmitter
•Integrated Synthesizer/VCO
•Internal DC Servo Loops
•RSSI, RF and Baseband Control Interface
•Power Management Unit
•3-Wire SPI Interface
To complete RF front-end solution, the AMN3210 uses external PA, RF Band Pass Filters (BPF), RF BALUNs
and a few passive components.
2.4 Power Amplifier (PA)
In order to extend the operating range for the AMN12310 upstream, the RF transmitter uses a power amplifier.
The power amplifier has an output power detector for TPC purposes.
AMN12310 uses Sharp IRM053U7 PA.
2.5 Board Connector (WHDI
TM
Connector)
For information regarding the connector specification and pin-outs see section 4.1,Signals, page 26.
2.6 Clocks
2.6.1 40MHz Crystal Oscillator
An on-board 40MHz crystal oscillator is connected to the AMN3210 chip.
2.6.2 40Mhz Digital Clock
AMN3210 drives the 40MHz clock to the baseband AMN2210 through a buffer (with output enable).
This clock is named DIG_CLK. The control to the output buffer is named Clk40M_OE.
2.6.3 10Mhz Micro Controller Clock
The DIG_CLK (40MHz) clock is divided by four by the AMN2210 and generates 10MHz that drives the STM32F
UC.

Overview
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2.7 CY22150 External Video PLL
An external PLL is used for re-generating the video clock. The PLL receives a lower speed clock (generally
limited to 10 MHz), which is generated inside the AMN2210 according to the video parameters. The PLL
multiplies the clock to the desired speed dictated by the incoming video format (for example: 74.25Mhz for 720p
or 1080i).

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Chapter 3
Interfaces
3.1 Video Data Input and Conversions
Figure 3: Video Data Receiver Path
Figure 3 shows the basic control over the video data output. Essentially the receiver mirrors the video format of
the transmitter end and so most of the configurations are done on the transmitter end.
The video output data is uncompressed digital video up to 3*10 bits in width. The video interface provides a direct
connection to the inputs of a display device, an HDMI transmitter, or any other video interface device.
Color Space Converter
The receiver can output either RGB or YCbCr color space. For more details, you may refer to the MAC registers
in the programmer's reference guide.
Color Range Limiter
The YCbCr data range can be limited to 16-235.

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Common Video Output Format
Table 2 lists the common supported video output resolutions.
Table 2: Common Supported Video Input Resolutions
Input Pixel Clock (MHz)
Color Space Video Format Bus
Width 480i 480p XGA 720p 1080i
RGB/YCbCr 4:4:4 24 27 27 65 74.25 74.25
Video Channel Mapping
The 30 bit video output signals are mapped to the RGB and YCbCr color space according to the options
described in the following table:
Table 3: Video Channel Mapping
Option D[29:20] D[19:10] D[9:0]
#1 RED (Cr) GREEN (Y) BLUE (Cb)
#2 RED (Cr) BLUE (Cb) GREEN (Y)
#3 GREEN (Y) RED (Cr) BLUE (Cb)
#4 GREEN (Y) BLUE (Cb) RED (Cr)
#5 BLUE (Cb) RED (Cr) GREEN (Y)
#6 BLUE (Cb) GREEN (Y) RED (Cr)
The AMN123100 allows any of the output video channels options. The first option is the default from power-up. In
order to change the video channel mapping, refer to the appropriate programmer's reference guide.
3.2 Video Interface Output Timing Diagram
3.2.1 Timing Requirements
Important: The following parameters relate to the AMN2210 baseband chipset and not to the entire AMN12310
board.
Table 4: Video Interface
Symbol Parameter MIN TYP MAX Units
TDCKCYC DCLK period 12.5 40 Ns
TDCKFREQ DCLK frequency 25* 80 MHz
TDCKDUTY DCLK duty cycle 40% 60% Ns
TDCKPDR Propagation delay after DCLK rising edge 1.0 4.0 Ns
TDCKPDF Propagation delay after DCLK falling edge 1.0 4.0 Ns
* It is possible to support lower clock frequency using an external PLL for video clock generation.

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3.2.1.1 Timing Diagram
EDGE = 0 EDGE = 1
Figure 4: Timing Diagram
3.3 Audio Data Capture
AMN12310 audio processing logic block receives the audio stream from the WHDI wireless link and regenerates
the appropriate clock and data. If the transmitter end was configured to SPDIF audio interface, then the audio is
output on the receiver side through the SPDIF. The same is true for the I
2
S interface.
No constraints exist for a coherent video and audio clock, where coherent means that the audio and the video
clock must have been created from the same clock source. The AMN12310 supports two-channel audio-sampling
frequencies of up to 48 KHz, 32 bits per sample.

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3.3.1 I2S Bus Specification
The AMN12310 supports a standardized communication structure inter-IC sound (I
2
S) bus. As shown in Figure 5,
the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). In addition, it has a
MCLK signal which is synchronized to and a multiple of the WS. The external device generating SCK and WS is
the AMN12310.
Figure 5: I2S Simple System Configurations and Basic Interface Timing
The AMN12310 outputs exactly 32 bits for each channel (left and right). By default, the serial data is valid on the
leading (LOW to HIGH) edge of the clock signal, but it can also be configured to be valid on the edge (HIGH to
LOW) of the clock signal. The WS is also valid by default on the leading edge of the clock signal. The WS line
changes one clock period before the first bit of the transmitted channel.
The AMN12310 mirrors the transmitter's end audio inputs and so the MSB and the LSB position are defined at
the audio source at the transmitter side. In case the audio samples in the transmitter are less than 32 bits long,
they are padded with zeroes to generate receiver output samples of 32 bits.
3.3.1.1 MUTE
The AMN12310 has an error detection mechanism. It outputs a high MUTE signal in case of bad audio reception
(bad frames).

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3.3.1.2 Timing Requirements
Table 5: Audio Interface Output Timing
Symbol Parameter MIN TYP MAX Units
TSCKCYC SCK period 325 976 ns
TSCKFREQ SCK frequency 1.024 3.072 MHz
TSCKDUTY SCK duty cycle 40 60 %
TDCKPDR Propagation delay after SCK rising edge 25 ns
TDCKPDF Propagation delay after SCK falling edge 25 ns
3.3.1.3 Timing Diagram
TSCKCYC
TDCKPDR
TSCKDUTY
SCK
SD,WS
50%
TSCKCYC
TDCKPDF
TSCKDUTY
SCK
SD,WS
50%
EDGE = 1EDGE = 0
Figure 6: I2S Output Timings
3.3.1.4 MCLK Specifications
In addition, AMN2210 outputs a MCLK signal which is synchronized to and a multiple of the WS. The default
configuration of the MCLK frequency is 256 times the sampling frequency of the audio signal. For example, if the
audio sampling frequency is 48 KHz, the MCLK frequency will be 12.288 MHz. The following table provides the
specification of the MCLK –

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Table 6: MCLK timing.
Symbol Parameter MIN TYP MAX Units
T
MCKCYC
MCK period 244.14 81.38 ns
T
MCKFREQ
MCK frequency 4.096* 12.288** MHz
T
MCKDUTY
MCK duty cycle 40 60 %
T
DCKPDR
Propagation delay after MCK
rising edge
25 ns
T
DCKPDF
Propagation delay after MCK
falling edge
25 ns
T
JITTER-CYC-
CYC
Cycle-to-cycle jitter*** 5 ns
* The minimum frequency is obtained by using the minimum audio sampling frequency of 32 KHz and the
minimum clock rate multiplication of 128.
** The maximum frequency is obtained by using the minimum audio sampling frequency 48 KHz and the
minimum clock rate multiplication of 256.
*** The cycle-to-cycle jitter is based on the system clock of the AMN2210, which is 200 MHz.