Analog Devices AD8221AR User manual

Precision Instrumentation Amplifier
AD8221
Rev. C
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FEATURES
Easy to use
Available in space-saving MSOP
Gain set with 1 external resistor (gain range 1 to 1000)
Wide power supply range: ±2.3 V to ±18 V
Temperature range for specified performance:
−40°C to +85°C
Operational up to 125°C1
Excellent AC specifications
80 dB minimum CMRR to 10 kHz (G = 1)
825 kHz, –3 dB bandwidth (G = 1)
2 V/µs slew rate
Low noise
8 nV/√Hz, @ 1 kHz, maximum input voltage noise
0.25 µV p-p input noise (0.1 Hz to 10 Hz)
High accuracy dc performance (AD8221BR)
90 dB minimum CMRR (G = 1)
25 µV maximum input offset voltage
0.3 µV/°C maximum input offset drift
0.4 nA maximum input bias current
APPLICATIONS
Weigh scales
Industrial process controls
Bridge amplifiers
Precision data acquisition systems
Medical instrumentation
Strain gages
Transducer interfaces
GENERAL DESCRIPTION
The AD8221 is a gain programmable, high performance
instrumentation amplifier that delivers the industry’s highest
CMRR over frequency in its class. The CMRR of instrumentation
amplifiers on the market today falls off at 200 Hz. In contrast,
the AD8221 maintains a minimum CMRR of 80 dB to 10 kHz
for all grades at G = 1. High CMRR over frequency allows the
AD8221 to reject wideband interference and line harmonics,
greatly simplifying filter requirements. Possible applications
include precision data acquisition, biomedical analysis, and
aerospace instrumentation.
CONNECTION DIAGRAM
8
7
6
5
1
2
3
4
–IN
RG
RG
+VS
VOUT
REF
–VS
+IN
TOP VIEW
AD8221
03149-001
Figure 1.
40
50
60
70
80
90
CMRR (dB)
100
110
120
FREQUENCY (Hz)
10010 1k 10k 100k
03149-002
AD8221
COMPETI
TOR 1
COMPETITOR 2
Figure 2. Typical CMRR vs. Frequency for G = 1
Low voltage offset, low offset drift, low gain drift, high gain
accuracy, and high CMRR make this part an excellent choice
in applications that demand the best dc performance possible,
such as bridge signal conditioning.
Programmable gain affords the user design flexibility. A single
resistor sets the gain from 1 to 1000. The AD8221 operates on
both single and dual supplies and is well suited for applications
where ±10 V input voltages are encountered.
The AD8221 is available in a low cost 8-lead SOIC and 8-lead
MSOP, both of which offer the industry’s best performance. The
MSOP requires half the board space of the SOIC, making it ideal
for multichannel or space-constrained applications.
Performance is specified over the entire industrial temperature
range of −40°C to +85°C for all grades. Furthermore, the AD8221
is operational from −40°C to +125°C1.
1See Typical Performance Characteristics for expected operation from
85°C to 125°C.

AD8221
Rev. C | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 17
Gain Selection ............................................................................. 18
Layout .......................................................................................... 18
Reference Terminal .................................................................... 19
Power Supply Regulation and Bypassing ................................ 19
Input Bias Current Return Path ............................................... 19
Input Protection ......................................................................... 19
RF Interference ........................................................................... 20
Precision Strain Gage................................................................. 20
Conditioning ±10 V Signals for a +5 V Differential Input
ADC ............................................................................................. 20
AC-Coupled Instrumentation Amplifier................................ 21
Die Information.............................................................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
3/11—Rev. B to Rev. C
Added Pin Configuration and Function Descriptions Section.. 9
Added Die Information Section ................................................... 22
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide .......................................................... 24
9/07—Rev. A to Rev. B
Changes to Features.......................................................................... 1
Changes to Table 1 Layout............................................................... 3
Changes to Table 2 Layout............................................................... 5
Changes to Figure 15...................................................................... 11
Changes to Figures 32 .................................................................... 13
Changes to Figure 33, Figure 34, and Figure 35......................... 14
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
11/03—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Specifications Section.................................................. 4
Changes to Theory of Operation Section.................................... 13
Changes to Gain Selection Section............................................... 14
10/03—Revision 0: Initial Version

AD8221
Rev. C | Page 3 of 24
SPECIFICATIONS
VS= ±15 V, VREF = 0 V, TA= 25°C, G = 1, RL= 2 kΩ, unless otherwise noted.
Table 1.
AR Grade BR Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
VCM = −10 V to +10 V
G = 1 80 90 dB
G = 10 100 110 dB
G = 100 120 130 dB
G = 1000 130 140 dB
CMRR at 10 kHz VCM = −10 V to +10 V
G = 1 80 80 dB
G = 10 90 100 dB
G = 100 100 110 dB
G = 1000 100 110 dB
NOISE RTI noise =
√eNI2+ (eNO/G)2
Voltage Noise, 1 kHz
Input Voltage Noise, eNI VIN+, VIN−, VREF = 0 8 8 nV/√Hz
Output Voltage Noise, eNO 75 75 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2 2 µV p-p
G = 10 0.5 0.5 µV p-p
G = 100 to 1000 0.25 0.25 µV p-p
Current Noise f = 1 kHz 40 40 fA/√Hz
f = 0.1 Hz to 10 Hz 6 6 pA p-p
VOLTAGE OFFSET1
Input Offset, VOSI VS= ±5 V to ±15 V 60 25 µV
Over Temperature T = −40°C to +85°C 86 45 µV
Average TC 0.4 0.3 µV/°C
Output Offset, VOSO VS= ±5 V to ±15 V 300 200 µV
Over Temperature T = −40°C to +85°C 0.66 0.45 mV
Average TC 6 5 µV/°C
Offset RTI vs. Supply (PSR) VS= ±2.3 V to ±18 V
G = 1 90 110 94 110 dB
G = 10 110 120 114 130 dB
G = 100 124 130 130 140 dB
G = 1000 130 140 140 150 dB
INPUT CURRENT
Input Bias Current 0.5 1.5 0.2 0.4 nA
Over Temperature T = −40°C to +85°C 2.0 1 nA
Average TC 1 1 pA/°C
Input Offset Current 0.2 0.6 0.1 0.4 nA
Over Temperature T = −40°C to +85°C 0.8 0.6 nA
Average TC 1 1 pA/°C
REFERENCE INPUT
RIN 20 20 kΩ
IIN VIN+, VIN−, VREF = 0 50 60 50 60 µA
Voltage Range –VS+VS–VS+VSV
Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V

AD8221
Rev. C | Page 4 of 24
AR Grade BR Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
POWER SUPPLY
Operating Range V
S
= ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 V
Quiescent Current 0.9 1 0.9 1 mA
Over Temperature T = −40°C to +85°C 1 1.2 1 1.2 mA
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 825 825 kHz
G = 10 562 562 kHz
G = 100 100 100 kHz
G = 1000 14.7 14.7 kHz
Settling Time 0.01% 10 V step
G = 1 to 100 10 10 µs
G = 1000 80 80 µs
Settling Time 0.001% 10 V step
G = 1 to 100 13 13 µs
G = 1000 110 110 µs
Slew Rate G = 1 1.5 2 1.5 2 V/µs
G = 5 to 100 2 2.5 2 2.5 V/µs
GAIN G = 1 + (49.4 kΩ/R
G
)
Gain Range 1 1000 1 1000 V/V
Gain Error VOUT ± 10 V
G = 1 0.03 0.02 %
G = 10 0.3 0.15 %
G = 100 0.3 0.15 %
G = 1000 0.3 0.15 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 10 RL= 10 kΩ 3 10 3 10 ppm
G = 100 RL= 10 kΩ 5 15 5 15 ppm
G = 1000 RL= 10 kΩ 10 40 10 40 ppm
G = 1 to 100 R
L
= 2 kΩ 10 95 10 95 ppm
Gain vs. Temperature
G = 1 3 10 2 5 ppm/°C
G > 12–50 –50 ppm/°C
INPUT
Input Impedance
Differential 100||2 100||2 GΩ||pF
Common Mode 100||2 100||2 GΩ||pF
Input OperatingVoltage Range3VS= ±2.3 V to ±5 V –VS+ 1.9 +VS− 1.1 –VS+ 1.9 +VS− 1.1 V
OverTemperature T = −40°C to +85°C –VS+ 2.0 +VS− 1.2 –VS+ 2.0 +VS− 1.2 V
Input OperatingVoltage Range VS= ±5 V to ±18 V –VS+ 1.9 +VS− 1.2 –VS+ 1.9 +VS− 1.2 V
Over Temperature T =−40°C to +85°C –VS+ 2.0 +VS− 1.2 –VS+ 2.0 +VS− 1.2 V
OUTPUT RL= 10 kΩ
Output Swing VS= ±2.3 V to ±5 V –VS+ 1.1 +VS− 1.2 –VS+ 1.1 +VS− 1.2 V
Over Temperature T = −40°C to +85°C –VS+ 1.4 +Vs − 1.3 –VS+ 1.4 +VS− 1.3 V
Output Swing VS= ±5 V to ±18 V –VS+ 1.2 +VS− 1.4 –VS+ 1.2 +VS− 1.4 V
Over Temperature T = –40°C to +85°C –VS+ 1.6 +VS− 1.5 –VS+ 1.6 +VS− 1.5 V
Short-Circuit Current 18 18 mA

AD8221
Rev. C | Page 5 of 24
AR Grade BR Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
TEMPERATURE RANGE
Specified Performance –40 +85 –40 +85 °C
Operating Range4–40 +125 –40 +125 °C
1Total RTI VOS = (VOSI) + (VOSO/G).
2Does not include the effects of external resistor RG.
3One input grounded. G = 1.
4See Typical Performance Characteristics for expected operation between 85°C to 125°C.
Table 2.
Parameter Conditions
ARM Grade
UnitMin Typ Max
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = −10 V to +10 V
G = 1 80 dB
G = 10 100 dB
G = 100 120 dB
G = 1000 130 dB
CMRR at 10 kHz VCM = –10 V to +10 V
G = 1 80 dB
G = 10 90 dB
G = 100 100 dB
G = 1000 100 dB
NOISE RTI noise = √eNI2+ (eNO/G)2
Voltage Noise, 1 kHz
Input Voltage Noise, e
NI
V
IN+
, V
IN−
, V
REF
= 0 8 nV/√Hz
Output Voltage Noise, eNO 75 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2 µV p-p
G = 10 0.5 µV p-p
G = 100 to 1000 0.25 µV p-p
Current Noise f = 1 kHz 40 fA/√Hz
f = 0.1 Hz to 10 Hz 6 pA p-p
VOLTAGE OFFSET1
Input Offset, V
OSI
V
S
= ±5 V to ±15 V 70 µV
Over Temperature T = −40°C to +85°C 135 µV
Average TC 0.9 µV/°C
Output Offset, VOSO VS= ±5 V to ±15 V 600 µV
Over Temperature T = −40°C to +85°C 1.00 mV
Average TC 9 µV/°C
Offset RTI vs. Supply (PSR) VS= ±2.3 V to ±18 V
G = 1 90 100 dB
G = 10 100 120 dB
G = 100 120 140 dB
G = 1000 120 140 dB
INPUT CURRENT
Input Bias Current 0.5 2 nA
Over Temperature T = −40°C to +85°C 3 nA
Average TC 3 pA/°C
Input Offset Current 0.3 1 nA
Over Temperature T = −40°C to +85°C 1.5 nA
Average TC 3 pA/°C

AD8221
Rev. C | Page 6 of 24
Parameter Conditions
ARM Grade
UnitMin Typ Max
REFERENCE INPUT
R
IN
20 kΩ
IIN VIN+, VIN−, VREF = 0 50 60 µA
Voltage Range −VS+VSV
Gain to Output 1 ± 0.0001 V/V
POWER SUPPLY
Operating Range VS= ±2.3 V to ±18 V ±2.3 ±18 V
Quiescent Current 0.9 1 mA
Over Temperature T = −40°C to +85°C 1 1.2 mA
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = 1 825 kHz
G = 10 562 kHz
G = 100 100 kHz
G = 1000 14.7 kHz
Settling Time 0.01% 10 V step
G = 1 to 100 10 µs
G = 1000 80 µs
Settling Time 0.001% 10 V step
G = 1 to 100 13 µs
G = 1000 110 µs
Slew Rate G = 1 1.5 2 V/µs
G = 5 to 100 2 2.5 V/µs
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 V/V
Gain Error VOUT ± 10 V
G = 1 0.1 %
G = 10 0.3 %
G = 100 0.3 %
G = 1000 0.3 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 10 RL= 10 kΩ 5 15 ppm
G = 100 R
L
= 10 kΩ 7 20 ppm
G = 1000 RL= 10 kΩ 10 50 ppm
G = 1 to 100 RL= 2 kΩ 15 100 ppm
Gain vs. Temperature
G = 1 3 10 ppm/°C
G > 12–50 ppm/°C
INPUT
Input Impedance
Differential 100||2 GΩ/pF
Common Mode 100||2 GΩ/pF
Input Operating Voltage Range3VS= ±2.3 V to ±5 V –VS+ 1.9 +VS− 1.1 V
Over Temperature T = −40°C to +85°C –VS+ 2.0 +VS− 1.2 V
Input Operating Voltage Range VS= ±5 V to ±18 V –VS+ 1.9 +VS− 1.2 V
Over Temperature T = −40°C to +85°C –VS+ 2.0 +VS− 1.2 V
OUTPUT RL= 10 kΩ
Output Swing VS= ±2.3 V to ±5 V –VS+ 1.1 +VS− 1.2 V
Over Temperature T = −40°C to +85°C –VS+ 1.4 +VS− 1.3 V
Output Swing VS= ±5 V to ±18 V –VS+ 1.2 +VS− 1.4 V
Over Temperature T = −40°C to +85°C –VS+ 1.6 +VS− 1.5 V
Short-Circuit Current 18 mA

AD8221
Rev. C | Page 7 of 24
Parameter Conditions
ARM Grade
UnitMin Typ Max
TEMPERATURE RANGE
Specified Performance −40 +85 °C
Operating Range4−40 +125 °C
1Total RTI VOS = (VOSI) + (VOSO/G).
2Does not include the effects of external resistor RG.
3One input grounded. G = 1.
4See Typical Performance Characteristics for expected operation between 85°C to 125°C.

AD8221
Rev. C | Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 200 mW
Output Short-Circuit Current Indefinite
Input Voltage (Common-Mode) ±VS
Differential Input Voltage ±VS
Storage Temperature Range −65°C to +150°C
Operating Temperature Range1−40°C to +125°C
1Temperature range for specified performance is –40°C to +85°C. See Typical
Performance Characteristics for expected operation from 85°C to 125°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Specification for a device in free air.
Table 4.
Package θ
JA
Unit
8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W
8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
ESD CAUTION

AD8221
Rev. C | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
–IN 1
RG2
RG3
+IN 4
+VS
8
VOUT
7
REF
6
–VS
5
AD8221
03149-103
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input Terminal.
2 RGGain Setting Terminal. Place resistor across the RGpins to set the gain. G = 1 + (49.4 kΩ/RG).
3RGGain Setting Terminal. Place resistor across the RGpins to set the gain. G = 1 + (49.4 kΩ/RG).
4 +IN Positive Input Terminal.
5 −VSNegative Power Supply Terminal.
6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.
7 VOUT Output Terminal.
8 +VSPositive Power Supply Terminal.

AD8221
Rev. C | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS= ±15 V, RL= 10 kΩ, unless otherwise noted.
0
200
400
600
800
1000
UNITS
1200
1400
1600
0–50–100–150 50 100 150
CMR (µV/V)
03149-003
Figure 4. Typical Distribution for CMR (G = 1)
0
300
600
900
1200
1500
UNITS
1800
2100
2400
0–20–40–60 20 40 60
INPUT OFFSET VOLTAGE (µV)
03149-004
Figure 5. Typical Distribution of Input Offset Voltage
0
500
1000
1500
2000
2500
3000
UNITS
0–0.5–1.0–1.5 0.5 1.0 1.5
INPUT BIAS CURRENT (nA)
03149-005
Figure 6. Typical Distribution of Input Bias Current
0
500
1000
1500
2000
2500
3000
3500
UNITS
0–0.3–0.6–0.9 0.3 0.6 0.9
INPUT OFFSET CURRENT (nA)
03149-006
Figure 7. Typical Distribution of Input Offset Current
–15
–10
–5
0
5
10
15
INPUT COMMON-MODE VOLTAGE (V)
–5 0–15 –10 5 10 15
OUTPUT VOLTAGE (V)
03149-007
V
S
= ±5V
V
S
= ±15V
Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1
–15
–10
–5
0
5
10
15
INPUT COMMON-MODE VOLTAGE (V)
–5 0–15 –10 5 10 15
OUTPUT VOLTAGE (V)
03149-008
V
S
= ±5V
V
S
= ±15V
Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100

AD8221
Rev. C | Page 11 of 24
0.40
0.45
0.50
0.55
0.60
0.65
INPUT BIAS CURRENT (nA)
0.70
0.75
0.80
–5 0–15 –10 5 10 15
COMMON-MODE VOLTAGE (V)
03149-009
VS= ±5V
VS= ±15V
Figure 10. IBIAS vs. CMV
0
0.25
0.50
0.75
1.00
1.25
CHANGE IN INPUT OFFSET VOLTAGE (µV)
1.50
1.75
2.00
0.10.01 1 10
WARM-UP TIME (min)
03149-010
Figure 11. Change in Input Offset Voltage vs. Warm-Up Time
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT CURRENT (nA)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03149-011
INPUT BIAS CURRENT
VS = ±15V
INPUT OFFSET CURRENT
Figure 12. Input Bias Current and Offset Current vs. Temperature
20
40
60
80
100
120
POSITIVE PSRR (dB)
140
160
180
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
03149-012
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
GAIN = 1000
Figure 13. Positive PSRR vs. Frequency, RTI (G = 1 to 1000)
20
40
60
80
100
120
NEGATIVE PSRR (dB)
140
160
180
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
03149-013
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
Figure 14. Negative PSRR vs. Frequency, RTI (G = 1 to 1000)
TOTAL DRIFT 25°C – 85°C RTI (µV)
10
100
1k
10k
100k
1k 10k10 100 100k 1M 10M
SOURCE RESISTANCE (
03149-014
BEST AVAILABLE FET
INPUT IN-AMP GAIN = 1
BEST AVAILABLE FET
INPUT IN-AMP GAIN = 1000
AD8221 GAIN = 1
AD8221 GAIN = 1000
Figure 15. Total Drift vs. Source Resistance

AD8221
Rev. C | Page 12 of 24
–30
–20
–10
0
10
20
30
40
50
60
70
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
GAIN (dB)
03149-015
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 16. Gain vs. Frequency
40
60
80
100
CMRR (dB)
120
140
160
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
03149-016
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 17. CMRR vs. Frequency, RTI
40
60
80
100
CMRR (dB)
120
140
160
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
03149-017
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
Figure 18. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
–100
–80
–60
–40
–20
0
20
40
60
80
100
CMR (µV/V)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03149-018
Figure 19. CMR vs. Temperature
–VS+0
+0.4
+0.8
+1.2
+1.6
+2.0
+2.4
–1.6
–2.0
–2.4
–1.2
–0.8
–0.4
+VS–0
INPUT VOLTAGE LIMIT (V)
REFERRED TO SUPPLY VOLTAGES
SUPPLY VOLTAGE (±V)
50 10 15 20
03149-019
Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1
–V
S
+0
+0.4
+0.8
+1.2
+1.6
+2.0
–1.6
–2.0
–1.2
–0.8
–0.4
+V
S
–0
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
SUPP LY VOLTAGE (±V)
50 10 15 20
03149-020
RL= 10k
RL= 2k
RL= 10k
RL= 2k
Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1

AD8221
Rev. C | Page 13 of 24
OUTPUT VOLTAGE SWING (V p-p)
0
20
10
30
LOAD RESISTANCE (
101 100 1k 10k
03149-021
VS= ±15V
Figure 22. Output Voltage Swing vs. Load Resistance
–V
S
+0
+1
+2
+3
–3
–2
–1
+V
S
–0
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
0 1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (mA)
03149-022
SOURCING
SINKING
Figure 23. Output Voltage Swing vs. Output Current, G = 1
–10 –8 –6 –4 –2 0 2 4 6 8 10
VS= ±15V
03149-023
ERROR (1ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 1, RL= 10 kΩ
VS= ±15V
03149-024
–10 –8 –6 –4 –2 0 2 4 6 8 10
ERROR (10ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity, G = 100, RL= 10 kΩ
VS= ±15V
03149-025
–10 –8 –6 –4 –2 0 2 4 6 8 10
ERROR (100ppm/DIV)
OUTPUT VOLTAGE (V)
Figure 26. Gain Nonlinearity, G = 1000, RL= 10 kΩ
VOLTAGE NOISE RTI (nV/ Hz)
1
100
10
1k
1 10 100 1k 10k 100k
FREQUENCY (Hz)
03149-026
GAIN = 1
GAIN = 1000
BW LIMIT
GAIN = 10
GAIN = 100
GAIN = 1000
Figure 27. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)

AD8221
Rev. C | Page 14 of 24
1s/DIV2µV/DIV
03149-027
Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
1s/DIV0.1µV/DIV
03149-028
Figure 29. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
CURRENT NOISE (fA/ Hz)
10
100
1k
FREQUENCY (Hz)
101 100 1k 10k
03149-029
Figure 30. Current Noise Spectral Density vs. Frequency
1s/DIV5pA/DIV
03149-030
Figure 31. 0.1 Hz to 10 Hz Current Noise
0
5
10
15
20
25
30
OUTPUT VOLTAGE (V p-p)
FREQUENCY (Hz)
1k 100k10k 1M
03149-031
GAIN = 1 GAIN = 10, 100, 1000
V
S
= ±15V
Figure 32. Large Signal Frequency Response
20µs/DIV
0.002%/DIV
7.9µs TO 0.01%
8.5µs TO 0.001%
5V/DIV
03149-032
Figure 33. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/DIV

AD8221
Rev. C | Page 15 of 24
20µs/DIV
4.9µs TO 0.01%
5.6µs TO 0.001%
5V/DIV
03149-033
0.002%/DIV
Figure 34. Large Signal Pulse Response and Settling Time (G = 10),
0.002%/DIV
20µs/DIV
10.3µs TO 0.01%
13.4µs TO 0.001%
5V/DIV
03149-034
0.002%/DIV
Figure 35. Large Signal Pulse Response and Settling Time (G = 100),
0.002%/DIV
200µs/DIV
83µs TO 0.01%
112µs TO 0.001%
5V/DIV
03149-035
0.002%/DIV
Figure 36. Large Signal Pulse Response and Settling Time (G = 1000),
0.002%/DIV
4µs/DIV
20mV/DIV
03149-036
Figure 37. Small Signal Response, G = 1, RL= 2 kΩ, CL= 100 pF
4µs/DIV
20mV/DIV
03149-037
Figure 38. Small Signal Response, G = 10, RL= 2 kΩ, CL= 100 pF
10µs/DIV
20mV/DIV
03149-038
Figure 39. Small Signal Response, G = 100, RL= 2 kΩ, CL= 100 pF

AD8221
Rev. C | Page 16 of 24
2
100µs/DIV
20mV/DIV
03149-039
Figure 40. Small Signal Response, G = 1000, RL= 2 kΩ, CL= 100 pF
SETTLING TIME (µs)
0
10
5
15
OUTPUT VOLTAGE STEP SIZE (V)
50 10 15 20
03149-040
SETTLED TO 0.01%
SETTLED TO 0.001%
Figure 41. Settling Time vs. Step Size (G = 1)
SETTLING TIME (µs)
1
100
10
1000
GAIN
1 100 10 1000
03149-041
SETTLED TO 0.001%
SETTLED TO 0.01%
Figure 42. Settling Time vs. Gain for a 10 V Step

AD8221
Rev. C | Page 17 of 24
THEORY OF OPERATION
C1 C2
+V
S
+V
S
+IN–IN
–V
S
–V
S
10k
10k
10k
400400
10kREF
OUTPUT
I
B
COMPENSATIONI
B
COMPENSATION
+V
S
–V
S
+V
S
–V
S
+VS
VB
I I
R1 24.7k24.7k
RG
Q1
R2
Q2
–VS
+VS
–VS
A2A1
A3
03149-042
Figure 43. Simplified Schematic
The AD8221 is a monolithic instrumentation amplifier based
on the classic 3-op amp topology. Input transistors Q1 and Q2
are biased at a fixed current so that any differential input signal
forces the output voltages of A1 and A2 to change accordingly.
A signal applied to the input creates a current through RG, R1,
and R2, such that the outputs of A1 and A2 deliver the correct
voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be
viewed as precision current feedback amplifiers. The amplified
differential and common-mode signals are applied to a
difference amplifier that rejects the common-mode voltage
but amplifies the differential voltage. The difference amplifier
employs innovations that result in low output offset voltage as
well as low output offset voltage drift. Laser-trimmed resistors
allow for a highly accurate in-amp with gain error typically less
than 20 ppm and CMRR that exceeds 90 dB (G = 1).
Using superbeta input transistors and an IBcompensation
scheme, the AD8221 offers extremely high input impedance,
low IB, low IBdrift, low IOS, low input bias current noise, and
extremely low voltage noise of 8 nV/√Hz.
The transfer function of the AD8221 is
GR
GkΩ4.49 1
Users can easily and accurately set the gain using a single
standard resistor.
Because the input amplifiers employ a current feedback
architecture, the gain-bandwidth product of the AD8221
increases with gain, resulting in a system that does not suffer
from the expected bandwidth loss of voltage feedback
architectures at higher gains.
To maintain precision even at low input levels, special attention
was given to the design and layout of the AD8221, resulting in
an in-amp whose performance satisfies the most demanding
applications.
A unique pinout enables the AD8221 to meet a CMRR
specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz
(G = 1000). The balanced pinout, shown in Figure 44, reduces
the parasitics that had, in the past, adversely affected CMRR
performance. In addition, the new pinout simplifies board
layout because associated traces are grouped together. For
example, the gain setting resistor pins are adjacent to the
inputs, and the reference pin is next to the output.
8
7
6
5
1
2
3
4
–IN
R
G
R
G
+V
S
V
OUT
REF
–V
S
+IN
TOP VIEW
AD8221
03149-043
Figure 44. Pinout Diagram

AD8221
Rev. C | Page 18 of 24
GAIN SELECTION
Placing a resistor across the RGterminals set the gain of
AD8221, which can be calculated by referring to Table 6 or
by using the gain equation.
1
kΩ4.49
 G
R
G
Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of R
G
(Ω) Calculated Gain
49.9 k 1.990
12.4 k 4.984
5.49 k 9.998
2.61 k 19.93
1.00 k 50.40
499 100.0
249 199.4
100 495.0
49.9 991.0
The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
Careful board layout maximizes system performance. Traces
from the gain setting resistor to the RGpins should be kept as
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the local ground of the AD8221, as shown
in Figure 47, or connected to a voltage that is referenced to the
local ground of the AD8221.
Common-Mode Rejection
One benefit of the high CMRR over frequency of the AD8221 is
that it has greater immunity to disturbances, such as line noise
and its associated harmonics, than do typical instrumentation
amplifiers. Typically, these amplifiers have CMRR fall-off at
200 Hz; common-mode filters are often used to compensate for
this shortcoming. The AD8221 is able to reject CMRR over a
greater frequency range, reducing the need for filtering.
A well implemented layout helps to maintain the high CMRR
over frequency of the AD8221. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as permissible.
Grounding
The output voltage of the AD8221 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
example layout is shown in Figure 45 and Figure 46.
03149-044
Figure 45. Top Layer of the AD8221-EVAL
03149-045
Figure 46. Bottom Layer of the AD8221-EVAL

AD8221
Rev. C | Page 19 of 24
REFERENCE TERMINAL
As shown in Figure 43, the reference terminal, REF, is at one
end of a 10 kΩ resistor. The output of the instrumentation
amplifier is referenced to the voltage on the REF terminal; this
is useful when the output signal needs to be offset to a precise
midsupply level. For example, a voltage source can be tied to the
REF pin to level-shift the output so that the AD8221 can interface
with an ADC. The allowable reference voltage range is a function
of the gain, input, and supply voltage. The REF pin should not
exceed either +VSor –VSby more than 0.5 V.
For best performance, source impedance to the REF terminal
should be kept low, because parasitic resistance can adversely
affect CMRR and gain accuracy.
POWER SUPPLY REGULATION AND BYPASSING
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance. Bypass capacitors should be used to decouple
the amplifier.
A 0.1 µF capacitor should be placed close to each supply pin.
As shown in Figure 47, a 10 µF tantalum capacitor can be used
further away from the part. In most cases, it can be shared by
other precision integrated circuits.
AD8221
+VS
+IN
–IN
LOAD
REF
0.1µF 10µF
0.1µF 10µF
–VS
VOUT
03149-046
Figure 47. Supply Decoupling, REF, and Output Referred to Local Ground
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8221 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 48.
+VS
REF
TRANSFORMER
THERMOCOUPLE
–VS
AD8221
+V
S
REF
–V
S
AD8221
CAPACITOR COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8221
1
f
HIGH-PASS
= 2ʌRC
03149-047
Figure 48. Creating an IBIAS Path
INPUT PROTECTION
All terminals of the AD8221 are protected against ESD, 1 kV
Human Body Model. In addition, the input structure allows for
dc overload conditions below the negative supply, −VS. The
internal 400 Ω resistors limit current in the event of a negative
fault condition. However, in the case of a dc overload voltage
above the positive supply, +VS, a large current flows directly
through the ESD diode to the positive rail. Therefore, an external
resistor should be used in series with the input to limit current
for voltages above +Vs. In either scenario, the AD8221 can
safely handle a continuous 6 mA current, I = VIN/REXT for
positive overvoltage and I = VIN/(400 Ω + REXT) for negative
overvoltage.
For applications where the AD8221 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors, and low leakage diode clamps, such as BAV199Ls,
FJH1100s, or SP720s should be used.

AD8221
Rev. C | Page 20 of 24
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 49. The
filter limits the input signal bandwidth according to the following
relationship:
)2(π2
1
CD
Diff
CCR
FilterFreq 
C
CM
RC
FilterFreq π2
1
where CDt10CC.
R
R
AD8221
+15V
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
V
OUT
–15V
R1
499
C
D
C
C
C
C
10nF
1nF
1nF
03149-048
4.02k
4.02k
Figure 49. RFI Suppression
CDaffects the difference signal, and CCaffects the common-
mode signal. Values of R and CCshould be chosen to minimize
RFI. Mismatch between the R × CCat the positive input and the
R × CCat the negative input degrades the CMRR of the AD8221.
By using a value of CDone magnitude larger than CC, the effect
of the mismatch is reduced, and therefore, performance is
improved.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8221
make it an excellent candidate for bridge measurements. As
shown in Figure 50, the bridge can be directly connected to
the inputs of the amplifier.
+5V
+2.5V
03149-049
10µF 0.1µF
AD8221
+IN
–IN
R
350
350350
350
+
–
Figure 50. Precision Strain Gage
CONDITIONING ±10 V SIGNALS FOR A +5 V
DIFFERENTIAL INPUT ADC
There is a need in many applications to condition ±10 V signals.
However, many of today’s ADCs and digital ICs operate on
much lower, single-supply voltages. Furthermore, new ADCs
have differential inputs because they provide better common-
mode rejection, noise immunity, and performance at low supply
voltages. Interfacing a ±10 V, single-ended instrumentation
amplifier to a +5 V, differential ADC can be a challenge.
Interfacing the instrumentation amplifier to the ADC requires
attenuation and a level shift. A solution is shown in Figure 51.
+12V
+IN
–IN
0.1µF
10µF
0.1µF10µF
–12V
R3
1k
+2.5V
R4
1k
REF R5
499
R2
10k
R1
10k
C1
470pF
+12V
0.1µF
0.1µF
–12V
+12V
+5V +5V
0.1µF
10nF
0.1µF
–12V
+12V
0.1µF
0.1µF
–12V
R6
27.4
R7
27.4
C2
220µF
10µF 0.1µF 22µF
+5V 2.5V
220nF 10nF
AD8221
AD8022
OP27
AD8022
AD7723
VIN(+)
AV
DD
AGND DGND REF1 REF2
DV
DD
VIN(–)
AD780
GND
+V
IN
V
OUT
03149-050
(½)
(½)
Figure 51. Interfacing to a Differential Input ADC