Analog Devices EVAL-AD5758 User manual

EVAL-AD5758 User Guide
UG-1268
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the AD5758 Single-Channel, 16-Bit Current and Voltage Output DAC with
Dynamic Power Control and HART Connectivity
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 22
FEATURES
Full featured evaluation board for the AD5758
On-board 2.5 V ADR4525 reference
On-board ADP1031-1 isolated PMU with integrated
SPI signal isolation channels
ACE software for control
EVALUATION KIT CONTENTS
EVAL-AD5758SDZ evaluation board
EQUIPMENT NEEDED
EVAL-SDP-CS1Z board
Bench top power supply and connector cables
ADDITIONAL DOCUMENTS REQUIRED
AD5758 data sheet
ACE User Manual
SOFTWARE REQUIRED
ACE software for control
GENERAL DESCRIPTION
This user guide describes the evaluation board for the AD5758,
a single-channel, voltage and current output, digital-to-analog
converter (DAC) with on-chip dynamic power control (DPC) to
minimize package power dissipation.
For full details, refer to the AD5758 data sheet. Consult the data
sheet when using the EVAL-AD5758SDZ. The configuration of
the various link options is explained in the Evaluation Board
Hardware section. The installation of the companion software is
discussed in the Evaluation Software Quick Start Procedures
section.
The EVAL-AD5758SDZ, as shown in Figure 1, requires the
EVAL-SDP-CS1Z board. The EVAL-AD5758SDZ interfaces to
the USB port of the PC via the EVAL-SDP-CS1Z board. The
Analysis|Control|Evaluation (ACE) software allows simplified
programming of the AD5758, and is available with the EVAL-
AD5758SDZ evaluation board.
EVALUATION BOARD PHOTOGRAPH
16710-001
Figure 1. EVAL-AD5758SDZ Evaluation Board

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Equipment Needed........................................................................... 1
Additional Documents Required ................................................... 1
Software Required ............................................................................ 1
General Description..................................................................... 1
Evaluation Board Photograph......................................................... 1
Revision History ............................................................................... 2
Evaluation Board Hardware............................................................ 3
Power Supplies .............................................................................. 3
Serial Communication................................................................. 3
AD5758 Address Pins.................................................................... 3
Evaluation Software Quick Start Procedures................................ 5
Installing the Analysis|Control| Evaluation (ACE) Software
and AD5758 Plug-Ins ................................................................... 5
Initial Setup ....................................................................................5
AD5758 Block Diagram and Functions..........................................7
Initial Configuration.....................................................................9
DC-to-DC Converter Settings.....................................................9
Setting the DAC Output............................................................ 10
Writing to the ADC Configuration Register .......................... 10
Updating Diagnostic Results .................................................... 10
Example Configuration Sequences.......................................... 11
ACE Tool Views.............................................................................. 13
Macro Tool .................................................................................. 13
Register Debugger Tool ............................................................. 13
Events Tool .................................................................................. 13
Evaluation Board Schematics and Artwork................................ 14
Ordering Information.................................................................... 21
Bill of Materials........................................................................... 21
REVISION HISTORY
3/2019—Rev. 0 to Rev. A
Changes to Feature Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Power Supplies Section, Serial Communication
Section, and Table 1.......................................................................... 3
Changes to Table 2............................................................................ 4
Changes to Figure 2.......................................................................... 5
Changes to Figure 7.......................................................................... 6
Changes to Figure 8 and Table 3..................................................... 7
Changes to Table 4............................................................................ 8
Changes to Figure 10........................................................................ 9
Changes to Setting the DAC Output Section, Figure 11, Writing
to the Configuration Register Section, Figure 12, Figure 13, and
Figure 14 .......................................................................................... 10
Changes to Figure 15...................................................................... 11
Changes to Figure 16...................................................................... 12
Changes to Figu4re 17 ................................................................... 14
Changes to Figure 18...................................................................... 15
Changes to Figure 19...................................................................... 16
Changes to Figure 20...................................................................... 17
Deleted Figure 21 and Figure 22; Renumbered Sequentially ... 18
Added Figure 21; Renumbered Sequentially .............................. 18
Deleted Figure 23 and Figure 24 .................................................. 19
Added Figure 22, Figure 23, and Figure 24................................. 19
Added Figure 25 and Figure 26 .................................................... 20
Changes to Table 5.......................................................................... 21
5/2018—Revision 0: Initial Version

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 3 of 22
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5758SDZ evaluation board contains the ADP1031-1
power management unit (PMU), which generates three of four
power supply inputs required by the AD5758: AVDD1 (+26.7 V),
AVDD2(+5.15 V), and AVSS (−15.4 V), device. VLOGIC is the fourth
power supply required by the AD5758. The JP11 link provides
the 3.3 V supply to the VLOGIC input via the VLDO output of the
AD5758. The AVDD2 input can be connected to the AVDD1 input
via the JP12 link if the VOUT2 supply from the ADP1031-1 is not
in use. See Table 1 for link options and the default link positions.
The EVAL-AD5758SDZ evaluation board operates with a power
supply range from −33 V on AVSS to +33 V on AVDD1, with a
maximum voltage of 60 V between the two rails. AVDD2 requires
a voltage between 5 V and 33 V. The VDPC+ pin of the AD5758
can be driven by AVDD1 via the JP6 link. The JP6 link bypasses
the dc-to-dc circuitry.
SERIAL COMMUNICATION
The SDP-S system demonstration platform handles commu-
nication to the EVAL-AD5758SDZ via the PC. By default, the
SDP-S board handles the serial port interface (SPI) commu-
nication, controls the RESET and LDAC pins, and monitors
the FAULT pin of the AD5758.
The EVAL-AD5758SDZ evaluation board can disconnect from
the SDP-S board and drive the digital signals from an external
source by removing the appropriate links on the P10 link. The
option to tie the RESET and LDAC pins to high or low levels
can be accessed through the S2 and JP4 links.
AD5758 ADDRESS PINS
The AD5758 address pins, AD0 and AD1, are used in conjunction
with the address bits within the SPI frame to determine which
AD5758 device is being addressed by the system controller. The
AD0 and AD1 pins can be configured through the JP7 and JP8
links.
Table 1. EVAL-AD5758SDZ Link Option Functions
Link Default Link
Position Function
JP1 B Position A selects the AVSS pin to GND for the unipolar supply option (current output only).
Position B selects the VOUT3 pin of the ADP1031-1.
JP2 Inserted Connects the VLOGIC pin of the AD5758 to the SVDD1 pin of the ADP1031-1.
JP3 A Position A selects the 3.3 V output from the SDP-S to the MVDD pin of the ADP1031-1.
Position B selects the 3.3 V input via the EXT+3.3V_ header to the MVDD pin of the ADP1031-1.
JP4 A Position A connects the LDAC pin to GND. Position B connects the LDAC pin to the VLOGIC pin.
JP5
A
Position A selects V
OUT2
of the ADP1031-1 as the input voltage to the ADR4525.
Position B selects the VLDO pin as the input voltage to the ADR4525.
JP6 Not inserted Shorts the VDPC+ pin to the AVDD1 pin, bypassing the positive dc-to-dc circuitry.
JP7 A Position A connects the AD0 pin to GND. Position B connects the AD0 pin to the VLOGIC pin.
JP8 A Position A connects the AD1 pin to GND. Position B connects the AD1 pin to the VLOGIC pin.
JP9 Inserted Connects the return signal to GND.
JP10 B Position A selects the REFOUT pin of the AD5758 as the input to the REFIN pin of the AD5758.
Position B selects the ADR4525 output as the input to the REFIN pin.
JP11 Inserted Selects 3.3 V output of the VLDO pin to the VLOGIC pin.
JP12 A Position A selects VOUT2 of the ADP1031-1 as the input voltage to the AVDD2 pin.
Position B selects the AVDD1 pin as the input voltage to the AVDD2 pin.
JP13
Inserted
Connects V
OUT1
of the ADP1031-1 to the AV
DD1
pin.
P10 Inserted Provides options to disconnect from the SDP-S board and to drive digital signals from an external source. See
Table 2 for the specific link options.
S2 Left In the left position, this link connects the RESET pin to the VLOGIC pin.
Middle (default) In the middle position (default), this link controls the RESET pin via the SDP-S board.
Right In the right position, this link connects the RESET pin to GND.

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 4 of 22
Table 2. Link Options for the P2_ Header
Pin No. Position Function
1, 2 Inserted Connects the FAULT signal from the SDP-S to the MGP03 pin on the ADP1031-1.
Not inserted Disconnects the FAULT signal from the SDP-S to the MGP03 pin on the ADP1031-1
3, 4 Inserted Connects the RESET signal from the SDP-S to the MGPI2 pin on the ADP1031-1.
Not inserted Disconnects the RESET signal from the SDP-S to the MGPI2 pin on the ADP1031-1.
5, 6 Inserted Connects the LDAC signal from the SDP-S to the MGPI1 pin on the ADP1031-1.
Not inserted Disconnects the LDAC signal from the SDP-S to the MGPI1 pin on the ADP1031-1.
7, 8 Inserted Connects the SCLK signal from the SDP-S to the MCK pin on the ADP1031-1.
Not inserted Disconnects the SCLK signal from the SDP-S to the MCK pin on the ADP1031-1.
9, 10 Inserted Connects the SDO signal from the SDP-S to the MI pin on the ADP1031-1.
Not inserted
Disconnects the SDO signal from the SDP-S to the MI pin on the ADP1031-1.
11, 12 Inserted Connects the SDI signal from the SDP-S to the MO pin on the ADP1031-1.
Not inserted Disconnects the SDI signal from the SDP-S to the MO pin on the ADP1031-1.
13, 14 Inserted Connects the SYNC signal from the SDP-S to the MSS pin on the ADP1031-1.
Not inserted Disconnects the SYNC signal from the SDP-S to the MSS pin on the ADP1031-1.
15, 16 Inserted Connects the PWRGD signal from the SDP-S to the PWRGD pin on the ADP1031-1.
Not inserted
Disconnects the PWRGD signal from the SDP-S to the PWRGD pin on the ADP1031-1.

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 5 of 22
EVALUATION SOFTWARE QUICK START PROCEDURES
INSTALLING THE ANALYSIS|CONTROL|
EVALUATION (ACE) SOFTWARE AND AD5758
PLUG-INS
The EVAL-AD5758SDZ software uses the Analog Devices, Inc.,
ACE software. For instructions the use of the ACE software, see
the www.analog.com/ACE product page.
When the installation completes, the EVAL-AD5758SDZ eval-
uation board plug-in appears when the ACE software opens
(see Figure 2).
16710-002
Figure 2. EVAL-AD5758SDZ Evaluation Board Plug-In Window after Opening
the ACE Software
INITIAL SETUP
To set up the EVAL-AD5758SDZ, take the following steps:
1. Connect a USB cable to the PC and then to the SDP-S
board.
2. Connect the SDP-S board to the EVAL-AD5758SDZ. The
PC recognizes the EVAL-AD5758SDZ.
3. Power up the EVAL-AD5758SDZ with the relevant power
supplies.
4. If not opened already, open the ACE software. The EVAL-
AD5758SDZ appears in the Attached Hardware pane.
16710-003
Figure 3. EVAL-AD5758SDZ Plug-In Not Installed
5. When setting up the evaluation board for the first time, the
EVAL-AD5758SDZ plug-in may need to be installed. If the
plug-in appears as shown in Figure 6, go to Step 7. If the plug-
in appears as shown in Figure 3, click the button that is circled
in red in Figure 3. After clicking this button, the pop-up
window shown in Figure 4 appears. Click Yes.
16710-004
Figure 4. Installing Plug-In Pop-Up Window
6. A new window appears, as shown in Figure 5. Navigate to
the Board.AD5758 plug-in and click Install Selected. The
EVAL-AD5758SDZ plug-in installs and is displays, as
shown in Figure 6.
16710-205
Figure 5. Plug-In Manager Window
16710-206
Figure 6. Attached Hardware Pane with EVAL-AD5758SDZ Connection

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 6 of 22
7. Double-click EVAL-AD5758SDZ to open the AD5758 block
diagram (see Figure 7). The INITIAL CONFIGURATION
pane appears on the left side of the window. Several register
settings can be configured in this pane and are written to the
device in the appropriate order. The DIG_DIAG_STATUS,
RESET_OCCURED, and CAL_MEM_UNREFRESHED
LED indicators in the window are illuminated red by default.
Writing the initial configuration values clears these error
flags. If the device is power cycled, or if the USB cable is
disconnected and reconnected while the ACE software is
open, contact with the EVAL-AD5758SDZ can be lost. If
contact is lost, click the System tab, click the USB symbol
on the EVAL-AD5758SDZ, and then click Acquire to
communicate with the EVAL-AD5758SDZ.
16710-107
Figure 7. AD5758 Block Diagram in the ACE Software

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 7 of 22
AD5758 BLOCK DIAGRAM AND FUNCTIONS
The AD5758 ACE block diagram, as shown in Figure 8, appears
similar to the block diagram shown in the AD5758 data sheet for
simplified correlation to the functions on the EVAL-AD5758SDZ
evaluation board with the descriptions given in the AD5758 data
sheet.
A full description of each block and register setting is available
in the AD5758 data sheet. The full screen AD5758 block diagram,
with labels, is shown in Figure 8. Table 3 describes the
functionality of each block.
16710-006
L1
L2
L3
L4
L5
O
N
M
L11
L6
L10
L12
L7
L8
L9
F
G
H
I
QRS
U
A B C D E
K
L13
P
L14 L15
T
V
Figure 8. AD5758 Block Diagram with Labels
Table 3. AD5758 Block Diagram Label Functions (See Figure 8)
Label Function Description
A To apply any changes made to the block diagram or to register values in the memory map to the device, click Apply Changes.
B To read back all of the registers of the device, click Read All.
C Click Reset Chip to reset the AD5758. The Reset Chip button has the same functionality as the software reset of the AD5758.
D Click Diff to show the registers that are different from the data stored on the device. This function shows what has changed since
the last time the registers were read.
E Click Software Defaults to load the software defaults of the device. These values are not written to the hardware. Click Apply
Changes (Label A in Figure 8) to write the software default values to the hardware.
F The AD0 and AD1 check boxes set the device under test (DUT) address of the device and must correspond to the JP12 and JP14
links on the hardware. If either box is checked, this represents a high state. If either box is unchecked, this represents a low state.
G If the /RESET box is checked, the SDP-S sets the RESET pin high. Otherwise, the SDP-S pulls RESET low.
H If the /LDAC box is checked, the SDP-S sets the LDAC pin high. Otherwise, the SDP-S pulls LDAC low.
I The ACE plug-in monitors the FAULT pin. If the FAULT pin is low, the /FAULT indicator LED illuminates red.
K The VI_OUT field displays the calculated output at the VIOUT pin and displays if the output is in volts, milliamperes, or is high
impedance (high-Z).
Lx The graphical user interface (GUI) access on several registers. Pop-ups, dropdown menu, and hexadecimal text fields are available
in the GUI to configure several registers of the AD5758. To write the changes to the device, click Apply Changes. The functions
within the GUI that control various registers (Label L1 through Label L15 in Figure 8) are described in Table 4.
M The Calibration Memory Refresh button initiates a write to the key register to perform a calibration memory refresh.
N The SW LDAC button initiates a write to the key register to perform a software LDAC command.
O The NOP Command button initiates a write to Address 0x00 for a no operation (NOP) command.
P The Configure ADC button writes the data selected in the ADC Config pane (Label L15) to the ADC configuration register.

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 8 of 22
Label Function Description
Q The Two Stage Readback pane initiates two-stage readback through the two-stage readback select register. Click Readback to
initiate a write to the two-stage readback select register and issue a NOP command.
R In the DIGITAL DIAGNOSTIC RESULTS pane, click Update and Readback Digital Diagnostic Result button to trigger a write 1 to
clear operation and initiate a readback from the digital diagnostic result register.
S In the ANALOG DIAGNOSTIC RESULTS pane, click Update and Readback Analog Diagnostic Result button to trigger a write 1
to clear operation and initiate a readback from the analog diagnostic result register.
T If the HART_EN box is checked, the HART_EN bit = 1 in the General-Purpose Configuration 1 register.
U
Click Proceed to Memory Map to open the AD5758 memory map (see Figure 9).
V Click Example Sequences to open the example sequences window (see Figure 15).
Table 4. Register Controls Accessible via the GUI (See Label Lx in Table 3 and in Figure 8)
Label
Function Description
L1 The Diagnostic Configurationbutton activates the associated pop-up menu.
L2 When the GP Config button clicked, a pop-up menu appears.
L3 When the Key register menu is clicked, a dropdown list appears.
L4 When the Fault Pin Config button is clicked, a pop-up menu appears.
L5
When the WDT Config button is clicked, a pop-up menu appears.
L6 The Frequency Monitor text field displays the value in the frequency monitor when read.
L7 The Clear Code text field inserts a clear code value in hexadecimal format.
L8 The User Gain text field inserts a user gain value in hexadecimal format.
L9 The User Offset text field inserts a user offset value in hexadecimal format.
L10 The DAC Input Reg text field inserts the DAC value in hexadecimal format.
L11
The 16 Bit DAC block opens a pop-up menu when clicked.
L12 The DAC Output Reg control displays the hexadecimal value currently set in the DAC output register.
L13 The DC-DC Converter block opens the dc-to-dc configuration pop-up menu.
L14
The
Status Register
pane displays the contents of the status register including any ADC conversion result.
L15 The ADC Config pane contains a combination of dropdown menus and a text field to enter the ADC input data.

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 9 of 22
16710-007
Figure 9. AD5758 Memory Map in the ACE Software
INITIAL CONFIGURATION
An initial configuration wizard is available when opening the
AD5758 plug-in. The initial configuration wizard allows quick
configuration of the AD5758 and provides configuration of the
clock output in the general-purpose configuration register, the
dc-to-dc settings, DAC configuration, and the DAC input register.
Clicking the Apply button initiates the configured settings in
the order of the recommended power-up sequence described in
the AD5758 data sheet.
DC-TO-DC CONVERTER SETTINGS
If the VDPC+ pin is not tied directly to AVDD1, enable the dc-to-dc
converter for proper operation. This step must be completed before
configuring the DAC output. The DC-DC Configuration pop-up
menu, as shown in Figure 10, contains the dc-to-dc settings
required to configure the AD5758 output properly. After the
desired settings are selected, click the Close button and then click
Apply Changes.
16710-008
Figure 10. DC-DC Configuration Pop-Up Menu

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 10 of 22
SETTING THE DAC OUTPUT
To configure the DAC output, use the DAC Config Register pop-
up menu (see Figure 11). Click the 16 Bit DAC block in the block
diagram to display the DAC configuration register. Select the
appropriate settings, and then click Apply Changes. It is recom-
mended to disable the output until the correct value in the DAC
input register is written to the device.
To change the DAC voltage or current output level, write the
appropriate hexadecimal code to the DAC input register, and
then click Apply Changes. Click SW LDAC to issue a software
LDAC command, or pull the LDAC pin low to update the DAC
output register with the values in the DAC input register. Enable
the DAC output by checking the OUT_EN (Enable VI_OUT)
checkbox, and then click Apply Changes. The programmed
voltage or current is then reflected at the VIOUT pin.
16710-009
Figure 11. AD5758 DAC Config Register Pop-Up Menu
WRITING TO THE ADC CONFIGURATION REGISTER
The procedure to set up and configure the ADC input node is
discussed in the AD5758 data sheet. For this reason, writing to
the ADC configuration register through the Apply Changes
function is disabled.
The dropdown list in the SEQUENCE_COMMAND pane
contains only an initiate single conversion command. The
hexadecimal tex field in the SEQUENCE_DATA pane is unused
and remains at 0. The dropdown list in the ADC_IP_SELECT
pane is used to select the desired input node for the ADC to
conveirt. Click Configure ADC to initiate a write to the ADC
configuration register. A register read must be performed to
see the ADC result in the status register.
16710-010
Figure 12. AD5758 ADC Configuration Register
UPDATING DIAGNOSTIC RESULTS
The AD5758 has a digital diagnostic results register and an analog
diagnostic results register, which contain error flags for the on-chip
digital and analog diagnostic features. Writing 1 to the respective
error flags updates the error flag status.
To update the digital and analog diagnostic result registers, click
Update and Readback. This button initiates the writing of a 1 to
the selected error flag and then reads back the updated diagnostic
result. Figure 13 shows the digital diagnostic results register.
Figure 14 shows the analog diagnostic results register.
16710-011
Figure 13. AD5758 Digital Diagnostic Register
16710-012
Figure 14. AD5758 Analog Diagnostic Register

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 11 of 22
EXAMPLE CONFIGURATION SEQUENCES
Several example configuration sequences are available. Click
Example Sequences, and the window shown in Figure 15 appears.
To enable any of the sequences, click the relevant sequence button,
as shown in Figure 16. The sequence runs immediately and the
output changes accordingly. To return to the main window, click
Back to AD5758.
16710-114
Figure 15. Example Sequences Window

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Rev. A | Page 12 of 22
16710-115
Figure 16. Selecting an Example Sequence

EVAL-AD5758 User Guide UG-1268
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ACE TOOL VIEWS
The ACE software provides additional functionality to the main
view described in this user guide. Open these views from the View
menu on the application toolbar. The ACE software features a
macro tool, a register debugger tool, and an events tool.
MACRO TOOL
The macro tool records and saves commands as an ACE macro
file. This feature is useful when sharing macros with other users
to perform the same task multiple times. The user can import
and run an ACE macro file.
REGISTER DEBUGGER TOOL
Use the register debugger tool to perform raw writes to and
reads from the device. The register debugger affects only the
hardware and does not write to the memory map of the ACE
software.
EVENTS TOOL
The events tool view contains a list of errors, warnings, and
information messages generated within the application software.

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Rev. A | Page 14 of 22
EVALUATION BOARD SCHEMATICS AND ARTWORK
OPTIONAL RC FILTER ON REFOUT
IF = 2MA
SMD 13.7K RSET = +/–0.1% TOL, +/–10PPM/DEGC
THROUGH-HOLE C_COMP IN GOLD PINS
2.2UF
DNI
AGND
0.1UF 0.1UF
AD5758BCPZ-REEL
PGND_ISO
50V
47UH
13.7K
50V
PGND_ISO
AGND
AGND
1K
0
GRN
0
0.1UF
REFGND
AGND
AGND
0.1UF
50V
REFGND
AGND
AGND
0.1UF
AGND
2.2UF
AGND
AGND
JP2
JP1
VDPC+
R42
SCLK_
R44
VLDO_
JP11
C12 C13
JP12
AVSS
AVDD2
AVDD1
JP13
DS4
R43
/RESET_/LDAC_ SDI_/SYNC_SDO_/FAULT_
C27
CLKOUT_
U5 C14
D4
C15
P5 P4
R9
C21
C16 L2
JP6
+VSENSE
NC2
NC1
AVSS_ISO
VLOGIC
–VSENSE
/FAULT
AD0 AD1
/SYNC
SDI
SCLK
LDAC_N /RESET
SDO
CHART
REFIN
AVDD2_ISO
AVDD1_ISO
VLOGIC
SCLK/LDAC/RESET SDOSDI /FAULT
VLDO
VIOUT
/SYNC
CLKOUT
REFOUT
/FAULT
21
3
2
1
A
C
4
13 12
29
31
21
1
14 20 19 16 10
9 6
8 7
32
17 24
PAD
15 18
11 27
25
3
2
5
22 23
26 28
AC
1
1
21
A B
BA
EPAD
NIC
NIC
PGND1
VDPC+
VIOUT
+VSENSE
CCOMP
–VSENSE
AVSS
FAULT_N AD0 AD1 SYNC_N SDI SCLK CLKOUT LDAC_N RESET_N DGND SDO VLOGIC VLDO
CHART
REFOUT REFIN
RB RA
REFGND
AGND
AVDD2
AVDD1
SW+
16710-013
Figure 17. AD5758 Schematic

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 15 of 22
RED = POWER/VOLTAGE TESTPOINTS:
GROUND PLANE APPROACH = SHORT AGND, PGND_ISO -> TO PRODUCE "GND"
REFGND "ISLAND" PINNED TO OTHER GND PLAIN AT 1 POINT
OPTION TO TIE /LDAC LOW & AD PINS PERMANENTLY HIGH/LOW
PRIMARY SIDE
AGND = SECONDARY SIDE DGND = PRIMARY SIDE
RESET TOGGLE SWITCH
AD5758 REFIN OPTIONS
BLACK = GROUND GREEN = SIGNAL
FARNELL CODE 3705353 NEEDS TO BE ADDED TO BOM
VIN = 3V - 15V
1UF
1UF
1UF
ADR4525BRZ
1UF
AGND AGND
TL39P0050
0
BLKBLK
AGND
BLK BLK
RED
RED
DGND
RED
BLK REFGND
REFGND
REFGND
AGND
RED
REFGND
AGND
AGND AGND
JP8
JP7
C24
C22 C23
JP3
+3.3V_
JP4
S2
C20
EXT+3.3V_
ADR_REF_
REFIN_
JP10
U4
REFOUT_
JP5
R41AGND5AGND4AGND3AGND2AGND1
REFOUT
3.3V_SDP
EXT +3.3V
AD0
AVDD2_ISO
AD1
VLOGIC
/RESET
LDAC_N
ADR-REF
/LDAC
ADR-REF
VLDO
VLOGIC
REFIN
+3.3V
EXT +3.3V
VLOGIC
6
28
7
5
3
1
4
BA
NC
NC
NC
NC
VIN
GND
TP
VOUT
BA
AB
AB
A B
BA
16710-014
Figure 18. AD5758 Supplies and Reference Options Schematic

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 16 of 22
2 PIN 8 ROW HEADER
SDP DEBUG LED
0.1UF
DGND DGND
FX8-120S-SV(21)
DGND
DGNDDGND
DGND
DGND
100K100K DNI
100KDNI
100K
DGND
1K
24LC32A/SN
GRN
R35
R34
R33
R32
R31
DS2
P10
U2
R30
C11
PWRGD_#SDI_#SDO_#SCLK_#LDAC_#RESET_#FAULT_ #SYNC_
P2_
3.3V_SDP
SDI_SDP
/RESET_SDP
#FAULT
/FAULT_SDP
#RESET
#LDAC
#SCLK
#SDO
#SDI
#SYNC
SCLK_SDP
SDO_SDP
/SYNC_SDP
/LDAC_SDP
SDP_PWRGD
/RESET_SDP
/FAULT_SDP
3.3V_SDP
SCLK_SDP
SDO_SDP
3.3V_SDP
PWRGD
SDP_PWRGD
/SYNC_SDP
SDI_SDP
/LDAC_SDP
65
116
1
5
6259
7249 7348
87
89
30
29 92
90
32 88
31 91
38
37 85
39
84
83
34
33
82
64
35
41 80
42 79
57
60
10021 99
26 95
27
7114
8113
9112
10 111
110
12
13 108
14 107
15 106
16 105
18 103
19 102
20 101
22
94
24 97
25 96
120
119
70
68
67
6655
54
53
51
50
2
7447
7645 7744 7843
118
117
115
109
104
98
93
86
81
75
69
6358
52
46
40
36
28
23
17
11
6
4
3
56
71
61
7
4
8
5
6
3
2
1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SPI_SEL_A_N
CLKOUT
NC
NC
GND
GND
VIO(+3.3V)
GND
PAR_D22
PAR_D20
PAR_D18
PAR_D16
PAR_D15
GND
PAR_D12
PAR_D10
PAR_D8
PAR_D6
GND
PAR_D4
PAR_D2
PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2
PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0
SPORT_RFS
SPORT_TFS
SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI
SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0
GPIO1
GPIO3
GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC
NC
NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX
GND
RESET_OUT_N
EEPROM_A0
NC
NC
NC
GND
NC
NC
TMR_C
TMR_A
GPIO6
GND
GPIO4
GPIO2
GPIO0
SCL_1
SDA_1
GND
SPI_SEL1/SPI_SS_N
SPI_SEL_C_N
SPI_SEL_B_N
GND
SERIAL_INT
SPI_D3
SPI_D2
SPORT_DT1
SPORT_DR1
SPORT_TDV1
SPORT_TDV0
GND
PAR_FS1
PAR_FS3
PAR_A1
PAR_A3
GND
PAR_CS_N
PAR_RD_N
PAR_D1
PAR_D3
PAR_D5
GND
PAR_D7
PAR_D9
PAR_D11
PAR_D13
PAR_D14
GND
PAR_D17
PAR_D19
PAR_D21
PAR_D23
GND
USB_VBUS
GND
GND
NC
VIN
VCC
WP
SCL SDA
VSS
A2
A1
A0
OUT
16710-015
Figure 19. SDP-S Board Connections, Address Pins, and LDAC and RESET Pins Schematic

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 17 of 22
THROUGH-HOLE LOAD RESISTOR OPTION
GOLD PINS FOR RESISTOR
+VSENSE
C_HART
VI_OUT
RETURN
-VSENSE
AGND
DNI
2.0K
DNI 20
0.01UF
DNI
1.0UF
DNI
GRN
DNI
DNI
AGND
1K
2.0K
DNI
GRN
2.0K
DNI
0.01UF
AGND
AGND
GRN
GRN
GRN
AGND
GRN
10
SMAJ33CA-TR
GRN
0.047UF
DNI
200
GRN
1K
0.15UF
AGND
AGND
C18
RETURN
VIOUT_TERMINAL
C19
R38
D2
R36
C17
R39
+VSENSE
R13
CHART
–VSENSE
TP1
VIOUT
TP2
R37
JP9
P3
R12
P8
P9
P6
P7
C26
R10
R11
C25
VIOUT
NC2
NC1
+VSENSE
CHART
–VSENSE
1
1
2
1
1
1
1
1
1
1
21
5
4
3
2
1
1
1
1
1
16710-016
Figure 20. AD5758 Output Stage Schematic

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 18 of 22
MINIMUM SUPPLY = 7V
~–15.4V
PLACE BETWEEN PIN 10 & PIN 5 PLACE BETWEEN PIN 20 & PIN 16
FARNELL 3705353 NEEDS TO BE ADDED TO BOM
~26.7V
LOCATE BESIDE THE PWRGD TESTPOINT
LED ON INDICATES AN ISSUE ON ADP1031 SECONDARY SUPPLIES
IF = 2MA
4.7UF
PGND
4.7UF
1MEG
PGND
4.7UF AGND
0.1UF0.1UF
0.1UF
AGND
PGND PGND
PGND
AGND
100K 100UH 715K
ADP1031ACPZ-1
4.7UF
BLK
210K
100K 100K AGND
AGND
DGND
750316743
50V
AGND 39K
590K
DGND
16V
AGND
4.7UF
4.7UF 50V
AGND
18.2K AGND
50V
100UH
AGND
BLK
100K100K
22PF
1K
AGND
DGND
BLK
PGND
BLK
AGND
BLK
R20 R19
R16R15
R1
C2 C6C4
DS1
DGND3DGND2DGND1
PGND2PGND1
C1
PVIN_ C7
R6 R5
U1
R3 R2
PVIN
C3
T1
D1
C5
L1
R7
L3
R8
C9
C8
R4
C10
SLEW
#SDI
#SCLK
#FAULT
#RESET
#LDAC
PWRGD
/LDAC
/RESET
/FAULT
SCLK
SDI SDO
/SYNC
#SYNC
#SDO
CLKOUT
+3.3V
SCLK
VLOGIC
VLOGIC
AVSS_ISO
AVDD2_ISO
AVDD1_ISO
+3.3V
PWRGD
SDO SDI
A
C
111
11
2 1
6
2 31
12 15 18
30
14
29
13 17 20 10
7
32
8
22 23 21
27
16
4
5
9
35 28
PAD3
PAD2
PAD1
39 41 1 38 37 36
34
3
40 33
11 19
26
25
24
1
4 5
1 8A C
IN
EN
SGND2
GNDP PGNDP
PAD
PAD
PAD
MO MCK MVDD MGPO3 MGPI2 MGPI1 PWRGD
MGND
SLEW
VINP
SWP
DNC
DNC
DNC
SGPO1 SGPO2
SGPI3
SVDD2
FB1
VOUT1
SW2
SGND2
VOUT2
SYNC
SW3
VOUT3
FB3
SVDD1
SCK
SI
SO
SSS_N
SGND1
SGND2
MGND
MSS_N MI
16710-121
Figure 21. ADP1031-1 PMU Schematic

EVAL-AD5758 User Guide UG-1268
Rev. A | Page 19 of 22
16710-017
Figure 22. EVAL-AD5758, Silkscreen
16710-018
Figure 23. EVAL-AD5758, Primary Layer
16710-019
Figure 24. EVAL-AD5758 Ground Planes, Layer 2

UG-1268 EVAL-AD5758 User Guide
Rev. A | Page 20 of 22
16710-020
Figure 25. EVAL-AD5758 Ground and Power Plane, Layer 3
16710-020
Figure 26. EVAL-AD5758, Layer 4 (Secondary)