Fairchild FSB44104A User manual

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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15
www.fairchildsemi.com
AN-9111
Smart Power Module, Motion SPM®45 LV series User’s Guide
Table of Contents
1. Introduction ...................................................................................................................................2
1.1. Design Concept...............................................................................................................................2
1.2. Key Features...................................................................................................................................2
2. Product Selections........................................................................................................................3
2.1. Ordering information .......................................................................................................................3
2.2. Product Line-up...............................................................................................................................3
3. Package..........................................................................................................................................4
3.1. Pin Description................................................................................................................................5
3.2. Detailed Pin Definition and Notification...........................................................................................6
3.3. Package Outline..............................................................................................................................7
3.4. Marking Specification......................................................................................................................8
4. Product Synopsis..........................................................................................................................9
4.2. Electrical Characteristic (TJ= 25oC, unless otherwise specified). ................................................10
4.3. Recommended Operating Conditions...........................................................................................12
4.4. Mechanical Characteristics...........................................................................................................12
5. Operation Sequence for Protections ........................................................................................13
5.1. Under-Voltage Lockout Protection................................................................................................13
6. Key Parameter Design Guidance ..............................................................................................14
6.1. Selection of Shunt resistor............................................................................................................14
6.2. Fault Output Circuit .......................................................................................................................15
6.3. Circuit of Input Signal (IN(xH), IN(xL)) ..........................................................................................15
6.4. Bootstrap Circuit Design ...............................................................................................................16
7. Print Circuit Board (PCB) Design..............................................................................................19
7.1. General Application Circuit Example ............................................................................................19
7.2. PCB Layout Guidance...................................................................................................................20
Packing Information .......................................................................................................................................21
Related Resources .........................................................................................................................................22

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 2
1. Introduction
This application note supports the Motion SPM®45 LV-
series. It should be used in conjunction with Motion SPM
45 LV datasheets, and Motion SPM design reference (RD-
408).
1.1. Design Concept
The key design objective of the SPM 45 LV series is to
provide a compact and reliable inverter solution for small
power motor drive applications. Ongoing efforts have
improved the performance, quality, and power rating of
SPM 45 LV series products.
The MOSFETs in SPM 45 LV series are specially processed
to reduce the amount of body-diode reverse recovery charge
to minimize the switching loss and enable fast switching
operations. Softness of the reverse-recovery characteristics
is managed through advanced MOSFET design with
optimized gate resistor selections to contain
Electromagnetic Interference (EMI) noise within a
reasonable range.
SPM 45 LV series has six fast-recovery MOSFETs
(FRFET®), LVIC and three-in-one HVIC. An FRFET-based
power module has much better ruggedness and a larger Safe
Operation Area (SOA) than MOSFET-based module or
Silicon-On-Insulator modules.
The FRFET-based power module has a big advantage in
light-load efficiency because the voltage drop across the
transistor decreases linearly as current decrease. Some
applications require continuous operation at light load
except short transients and improving the efficiency in the
light-load condition is the key to saving energy.
Refrigerators, water circulation pumps, and some fans are
good examples.
Motion SPM 45 LV series achieves reduced board size and
improved reliability compared to existing discrete solutions.
Target applications are invert motor drives for industrial
use, such as general-purpose inverters, power tool and servo
motors.
1.2. Key Features
UL Certified No.E209204 (UL1557)
40 V, Low RDS(ON) 3-Phase MOSFET Inverter
Module with Gate Drivers and Protection
Low Thermal Resistance Using Ceramic Substrate
Three Separate Open-Emitter Pins from Low-Side
MOSFETs for Three-Leg Current Sensing
Single-Grounded Power Supply for Built-in HVIC
Isolation Rating: 800 VRMS / min
Figure 1. Package Outline of Motion SPM 45 LV
Series
Figure 2. Internal Equivalent Circuit, Input / Output Pins

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 3
2. Product Selections
2.1. Ordering information
FSB44104A
4 : SPM 45L Package
Max. RDS(on) ( ÷10 mΩ)
Voltage Rating ( X 10 )
Version Blank : Ver.1
A : Ver.2
B : No NTC Thermister
S : Divided N-Terminal
F : Fairchild Semiconductor
Figure 3. Ordering Information of SPM® 45 LV Series
2.2. Product Line-up
Table 1 shows the basic line up. Online loss & temperature simulation tool, Motion Control Design Tool (Motion-Control-
Design-Tool), is recommended to find out the right SPM product for the desired application.
Table 1. Product Line-up
Target Application
Fairchild Device
MOSFET Rating
Motor
Rating(Error!
Reference source
not found.)
Isolation Voltage
Small-Power Inverter,
Power Tool
FSB44104A
40 A / 40 V
0.8 kW
VISO = 800 VRMS
(Sine 60 Hz, 1 min.
Between all shorted pins
and heat sink)
FSB43004A
60 A / 40 V
1.2 kW
Note:
1. These motor ratings are general ratings, so may be changed by conditions.

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 4
3. Package
Since heat dissipation is an important factor that limits the power modules current capability, the heat dissipation
characteristics are critical in determining the SPM package performance. A trade-off exists among heat dissipation
characteristics, package size, and isolation characteristics. The key to a good package technology lies in the accomplishment
of optimization package size while maintaining outstanding heat dissipation characteristics without compromising the
isolation rating.
In the SPM package, technology was developed in which bare ceramic with good heat dissipation characteristics is attached
directly to the lead frame. This technology already applied in SPM, but was improved through new adhesion methods. This
made it possible to achieve improved reliability and heat dissipation, while maintaining cost effectiveness.
FRDMosfet
IC
Al Wiring
Cu Wiring Lead Frame
Ceramic (Isolation material)
EMC(Epoxy Molding Compound)
Epoxy Resin
Figure 4. Vertical Structure of SPM Package

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 5
3.1. Pin Description
Figure 5 shows the location of pins, the name and dummy pins of SPM 45 LV series.
P (1)
W (2)
V (3)
NW(5)
NV(6)
NU(7)
U (4)
(22) VB(W)
(21) VS(W)
(20) VB(V)
(19) VS(V)
(18) VB(U)
(17) VS(U)
(16) IN(WH)
(15) IN(VH)
(14) IN(UH)
(13) VCC
(12) COM
(11) IN(WL)
(10) IN(VL)
(9) IN(UL)
(8) VFO
Figure 5. Package Top-View and Pin Assignment
The detail functional descriptions are provided in Table 2.
Table 2. Pin Description
Pin Number
Name
Description
1
P
Positive DC-Link Input
2
W
W Phase Output
3
V
V Phase Output
4
U
U Phase Output
5
NW
Negative DC-Link Input
6
NV
Negative DC-Link Input
7
NU
Negative DC-Link Input
8
VFO
Fault Output
9
IN(UL)
PWM Input for Low-Side U-Phase MOSFET Drive
10
IN(VL)
PWM Input for Low-Side V-Phase MOSFET Drive
11
IN(WL)
PWM Input for Low-Side W-Phase MOSFET Drive
12
COM
Common Supply Ground
13
VCC
Common Supply Voltage for IC and Low-side MOSFET Drive
14
IN(UH)
PWM Input for High-Side U-Phase MOSFET Drive
15
IN(VH)
PWM Input for High-Side V-Phase MOSFET Drive
16
IN(WH)
PWM Input for High-Side W-Phase MOSFET Drive
17
VB(U)
Supply Voltage for High-Side U-Phase MOSFET Drive
18
VS(U)
Supply Ground for High-Side U-Phase MOSFET Drive
19
VB(V)
Supply Voltage for High-Side V-Phase MOSFET Drive
20
VS(V)
Supply Ground for High-Side V-Phase MOSFET Drive
21
VB(W)
Supply Voltage for High-Side W-Phase MOSFET Drive
22
VS(W)
Supply Ground for High-Side W-Phase MOSFET Drive

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 6
3.2. Detailed Pin Definition and Notification
High-Side Bias Voltage Pins for Driving the
MOSFET / High-Side Bias Voltage Ground
Pins for Driving the MOSFET
Pin: VB(U)-VS(U), VB(V)-VS(V), VB(W)-VS(W)
•These are drive power supply pins for providing gate
drive power to the high-side MOSFETs.
•The external power supplies dont need for the high
side MOSFET driving by using bootstrap circuit..
•Each bootstrap capacitor is charged from the VCC
supply during ON state of the corresponding low-
side MOSFET.
•To prevent malfunctions caused by noise and ripple
in the supply voltage, a low-ESR, low-ESL filter
capacitor should be mounted very close to these pins.
Low-Side Bias Voltage Pin / High-Side Bias
Voltage Pins:
Pin: VCC
•These are control supply pins for the built-in ICs.
•This pin should be connected externally.
•To prevent malfunctions caused by noise and ripple
in the supply voltage, a low-ESR, low-ESL filter
capacitor should be mounted very close to these pins.
Low-Side Common Supply Ground Pins
Pin: COM
•The common (COM) pin connects to the control
ground for the internal ICs.
•Important! To avoid noise influences, the main
power circuit current should not be allowed to blow
through this pin.
Signal Input Pins
Pin: IN(UL), IN(VL), IN(WL), IN(UH), IN(VH), IN(WH)
•These pins control the operation of the built-in
MOSFETs.
•They are activated by voltage input signals. The
terminals are internally connected to a Schmitt-
trigger circuit composed of 5 V-class CMOS.
•The signal logic of these pins is active HIGH. The
MOSFETs associated with each of these pins are
turn-on when a sufficient logic voltage is applied to
these pins.
•The wiring of each input should be as short as
possible to protect the Motion SPM®45 LV series
against noise influences.
•To prevent signal oscillations, an RC coupling as
illustrated in Figure 16 is recommended.
Fault Output Pin
Pin: VFO
•This is the fault output alarm pin. An active LOW
output is given on this pin for a fault state condition
in the SPM.
•The alarm condition is: low-side bias Under-Voltage
Lockout (UVLO).
•The VFO output is open drain configured. The VFO
signal line should be pulled to the 5 V logic power
supply with approximately 4.7 
Positive DC-Link Pin
Pin: P
•This is the DC-link positive power supply pin of the
inverter.
•It is internally connected to the drains of the high-
side MOSFETs.
•To suppress surge voltage caused by the DC-link
wiring or PCB pattern inductance, connect a
smoothing filter capacitor close to this pin (tip: metal
film capacitor is typically used).
Negative DC-Link Pins
Pin: NU, NV, NW
•These are the DC-link negative power supply pins
(power ground) of the inverter.
•These pins are connected to the low-side MOSFET
source of the each phase.
•These pins are used in connection with one shunt or
three shunt resistor
Inverter Power Output Pins
Pin: U, V, W
•Inverter output pins for connecting to the inverter
load (e.g. motor).

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 7
3.3. Package Outline

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 8
3.4. Marking Specification

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 9
4. Product Synopsis
This section discuss electrical specification, characteristics and mechanical characteristics
4.1. Absolute Maximum Ratings (TJ= 25°C, unless otherwise specified).
Table 3. Inverter Part
Symbol
Parameter
Conditions
Rating
Unit
VPN
Supply Voltage
Applied between P NU, NV,NW
40
V
* ±ID(2)
Each MOSFET Drain Current
TC=25°C, TJ 150°C
FSB44104A
57
A
FSB43004A
71
* ±ICP(2)
Each MOSFET Drain Current
(Peak)
TC=25°C, TJ 150°C, Under
1 ms Pulse Width
FSB44104A
110
A
FSB43004A
180
* PD(2)
Maximum Power Dissipation
TC=25°C, per One Chip,
TJ=150°C
FSB44104A
28
W
FSB43004A
31
TJ
Operating Junction Temperature
-40 ~ 150
oC
Note:
2. .
Table 4. Control Part
Symbol
Parameter
Conditions
Rating
Unit
VCC
Control Supply Voltage
Applied between VCC - COM
20
V
VBS
High-Side Control Bias Voltage
Applied between VB(U) - VS(U),VB(V) - VS(V), VB(W) -
VS(W),
20
V
VIN
Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL), - COM
-0.3~VCC+0.3
V
VFO
Fault Output Supply Voltage
Applied between VFO COM
-0.3~VCC+0.3
V
IFO
Fault Output Current
Sink Current at VFO Pin
1
mA
Table 5. Total System
Symbol
Parameter
Conditions
Rating
Unit
TC
Module Case Operation
Temperature
See Figure 6
-40~125
°C
TSTG
Storage Temperature
-40~150
°C
VISO
Isolation Voltage
60 Hz, Sinusoidal, 1-Minute, Connect Pins to
Heat Sink
800
Vrms
Table 6. Thermal Resistance
Symbol
Parameter
Conditions
Max.
Unit
Rth(j-c)
Junction-to-Case Thermal
Resistance(3)
Package center (per MOSFET)
FSB44104A
4.41
°C /W
FSB43004A
3.92
Note:
3. For the measurement point of case temperature (TC), please refer to Figure 6.

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 10
Figure 6. Case Temperature (TC) Detecting Point
4.2. Electrical Characteristic (TJ= 25oC, unless otherwise specified).
Table 7. Inverter Part (Based on FSB44104A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
BVDSS
DrainSource Breakdown
Voltage
VIN=0 V, ID=250µA(4)
40
V
RDS(ON)
Drain - Source
Turn-On Resistance
VCC = VBS = 15 V, VIN = 5 V, ID= 40 A
3.0
4.1
m
VSD
Source - Drain Diode
Forward Voltage
VCC = VBS = 15 V, VIN = 0 V, ISD = 40 A
0.8
1.1
V
HS
tON
Switching Times
VPN = 20 V, VCC = VBS = 15 V, ID= 40 A,
VIN = 0 V 5 V, Inductive Load,
See Figure 7
1200
µs
tC(ON)
1140
tOFF
1700
tC(OFF)
500
trr
70
Irr
5
LS
tON
1370
tC(ON)
1000
tOFF
1850
tC(OFF)
600
trr
75
Irr
4
IDSS
Drain - Source Leakage
Current
VDS=VDSS
250
µA
Note:
4. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET. VPN should be
sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any
case.

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 11
One-Leg Diagram of Motion SPM
VCC
IN
COM
LO
P
N
Inducotor
20V
15V
Switching Pulse
Switching Pulse
VCC
IN
COM
VB
HO
VS
Inducotor
Line stray Inductance < 100nH
Line stray Inductance < 100nH
15V Only for low side switching
OUT
Figure 7. Switching Evaluation Circuit
HINx
LINx
ICx
vCEx 10% ICx
10% VCEx 10% ICx
90% ICx
toff ton
tc(off) tc(on)
10% VCEx
trr
100% ICx
Figure 8. Switching Time Definition
Table 8. Control Part
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
IQCC
Quiescent VCC Supply
Current
VCC(H)=15 V,
IN(UH,VH,WH) = 0 V
VCC(H) - COM
2.75
mA
IQBS
Quiescent VBS Supply
Current
VBS=15 V,
IN(UH,VH,WH)=0 V
VB(U) VS(U)
VB(V) VS(V)
VB(W) VS(W)
0.3
mA
VFOH
Fault Output Voltage
VCC=15 V, VSC=0 V, VFO Circuit: 4.7 kto
5 V Pull-up
4.5
V
VFOL
VCC=15 V, VSC=1 V, VFO Circuit: 4.7 kto
5 V Pull-up
0.5
UVCCD
Supply Circuit,
Under-Voltage Protection
Detection Level
7.0
8.2
10.0
V
UVCCR
Reset Level
8.0
9.4
11.0
UVBSD
Detection Level
7.0
8.0
9.5
UVBSR
Reset Level
8.0
9.0
10.5
tFOD
Fault-Out Pulse Width
30
µs
VIN(ON)
ON Threshold Voltage
Applied between IN(UH,VH,WH) - COM,
IN(UL,VL,WL) - COM
2.6
V
VIN(OFF)
OFF Threshold Voltage
0.8

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 12
4.3. Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VPN
Supply Voltage
Applied between P - NU, NV, NW
20
V
VCC
Control Supply Voltage
Applied between VCC(UH,VH,WH) - COM,
VCC(L) - COM
13.5
15.0
16.5
VBS
High-Side Bias Voltage
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.0
15.0
18.5
V
dVCC/dt,
dVBS/dt
Control Supply Variation
-1
1
V/µs
VSEN
Voltage for Current Sensing
Applied between NU, NV, NWCOM
(Including Surge Voltage)
-4
4
V
4.4. Mechanical Characteristics
Figure 9. Flatness Measurement Position
Parameter
Conditions
Value
Unit
Min.
Typ.
Max.
Device Flatness
See Figure 9
120
µm
Mounting Torque
Mounting Screw: M3
0.51
0.62
0.72
Nm
Weight
Module weight
8.4
g

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 13
5. Operation Sequence for Protections
5.1. Under-Voltage Lockout Protection
The LVIC has an under-voltage lockout protection (UVLO) function to protect the low-side MOSFETs from operation with
insufficient gate driving voltage. A timing chart for this protection is shown in Figure 10.
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVCCR
Protection Circuit
State SET RESET
UVCCD
Filtering?
Restart
B1
B2
B3
B4
B6
B7
High-level (no fault output) B5
Figure 10. Timing Chart of Low-Side Under-Voltage Protection Function
Notes:
5. B1-control supply voltage rise: after the voltage rises UVCCR, the circuits starts to operate when the next input is applied.
6. B2-normal operation: MOSFET ON and carrying current.
7. B3-under-voltage detection (UVCCD).
8. B4-MOSFET OFF in spite of control input is alive and
9. B5-Fault output signal starts.
10. B6-under-voltage reset (UVCCR).
11. B7-normal operation: MOSFET ON and carrying current..
The HVIC has an under-voltage lockout function to protect the high-side MOSFET from insufficient gate driving voltage.
A timing chart for this protection is shown in Figure 11. A fault-out (FO) alarm is not given for low HVIC bias conditions.
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVBSR
Protection Circuit
State SET RESET
UVBSD
Filtering?
Restart
C1
C2
C3
C4
C5
C6
High-level (no fault output)
Figure 11. Timing Chart of High-Side Under-Voltage Protection Function
Notes:
12. C1-control supply voltage rises: after the voltage reaches UVBSR, the circuit starts when the next input is applied.
13. C2-normal operation: MOSFET ON and carrying current.
14. C3-under-voltage detection (UVBSD).
15. C4-MOSFET OFF in spite of control input is alive, but there is no fault output signal.
16. C5-under-voltage reset (UVBSR).
17. C6-normal operation: MOSFET ON and carrying current.
All low-side MOSFET
gate are locked with
VFO output.
Fault-out duration
(tFOD): keep fault signal
(0 V) until recover VCC.
Needed LOW-to-HIGH
input transition to turn
on MOSFET again.
(Edge Trigger)
High-side MOSFET
gate is locked
without VFO output.
Needed LOW-to-HIGH
input transition to turn
on MOSFET again.
(Edge Trigger)

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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 14
6. Key Parameter Design Guidance
For stable operation, there are recommended parameters for
passive components and bias conditions, considering
operating characteristics of Motion SPM®45 LV series.
6.1. Selection of Shunt resistor
Figure 12 shows an example circuit of the SC protection
using 1-shunt resistor. The line current on the N side DC-
link is detected and the protective operation signal is passed
through the RC filter. If the current exceeds the SC
reference level, all the gates of the N-side three-phase
MOSFETs are switched to the OFF state and the FOfault
signal is transmitted to MCU. Since SC protection is non-
repetitive, MOSFET operation should be immediately
halted when the FOfault signal is given.
VS
CSC
3ØMotor
HVIC
. Level Shift
. Gate Drive
. UVLO
LVIC
. Gate Drive
. UVLO
. SCP
RSHUNT
VFO
COM RF
CSC
VDC
Short Circuit
Current (ISC)
VCSC
VCC
Figure 12. Short circuit current protection circuit with
one shunt resistor
The value of shunt resistor is calculated by the following
equation.
Maximum SC current trip level : ISC(max)=1.5 * IC(rated
current)
SC trip referenced voltage (depends on user selection):
VSC = min. 0.027 V, typ. 0.03 V, max. 0.033 V
(Tolerance 10%, depends on system)
Shunt resistance : ISC(max)=VSC(max)/RSHUNT(min)
RSHUNT(min)=VSC(max)/ISC(max)
If the deviation of the shunt resistor is limited below ±
1%:
RSHUNT(typ)=RSHUNT(min)/0.99,RSHUNT(max)=RSHUNT(typ) 1.01
Actual SC trip current level becomes:
ISC(typ)=VSC(typ) / RSHUNT(min), ISC(min) = VSC(min) /
RSHUNT(max)
Inverter output power:
POUT =      
where:
VO,LL= Inverter output line to line voltage
MI = Modulation Index;
IRMS = Maximum load current of inverter; and
PF = Power Factor
Average DC current
IDC_AVG = VDC_Link / (Pout Eff)
where:
Eff = Inverter efficiency
The power rating of shunt resistor is calculated by the
following equation.
PSHUNT = (I2DC_AVGRSHUNTMargin)/Derating Ratio
Where;
RSHUNT = Shunt resistor typical value at TC= 25°C
Derating Ratio = Derating ratio of shunt resistor at
TSHUNT = 100°C
(From datasheet of shunt resistor); and
Margin = Safety margin (determined by user)
Shunt Resistor Calculation Examples
Calculation Conditions:
DUT: FSB44104A
Tolerance of shunt resistor: ±1%
SC Trip Reference Voltage(VSC) :
VSC(min) = 0.0297 V, VSC(typ) = 0.03 V, VSC(max) =
0.0303 V
VSC = Reference voltage of external comparator
(refer to the Fig. 3)
Maximum Load Current of Inverter (IRMS): 28.3 Arms
Maximum Peak Load Current of Inverter (IC(max)):
60 A
Modulation Index(MI) : 0.9
DC Link Voltage(VDC_Link): 20 V
Power Factor(PF): 0.8
Inverter Efficiency(Eff): 0.95
Shunt Resistor Value at TC= 25°C (RSHUNT): 0.5 m
Derating Ration of Shunt Resistor at TSHUNT =
100°C: 70%
Safety Margin: 20%

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 15
Calculation Results:
ISC(max): 1.5 IC(max) = 1.5 x 40 A = 60 A
RSHUNT(typ): VSC(typ) / ISC(max) = 0.03 V / 60 A =
0.5 m
RSHUNT(max): RSHUNT(typ) x 1.01 = 0.5 mx 1.01 =
0.505 m
RSHUNT(min) : RSHUNT(typ) x 0.99 = 0.5 mx 0.99 =
0.495 m
ISC(min) : VSC(min) / RSHUNT(max) = 0.0297 V / 0.505 m
= 58.8 A
ISC(typ) : VSC(typ) / RSHUNT(typ) = 0.03 V / 0.5 m= 60 A
VO,LL=
          
POUT =       = 11.028.3
0.8 = 431.4 W
IDC_AVG = (POUT/Eff) / VDC_Link = 22.7 A
PSHUNT = (I2DC_AVG RSHUNT Margin) / Derating
Ratio = (22.720.0005 1.2) / 0.7 = 0.31 W
(Therefore, the proper power rating of shunt resistor
is over 1.0 W)
Figure 13. Derating Curve Example of Shunt Resistor
(from RARA Elec.)
When over-current events are happened, an external circuit
is needed for over-current detection and short circuit
protection (SCP).
SPM
5V line
R12
0.5m
3W
R14 1.2K 1%
R15 100K 1%
R11 1.2K 1%
5V line
5V line
MCU
Internal port
MCU
C15
102
C16
104
R17
3.3k 1%
R18 20K
1%
R16
10k 1%
R19 1M
R20 100
1%
C17
102
Comparator
Amplifier
NU, NV, NW
VREF VSC
5V line
R21
10k 1%
Figure 14. Short-Circuit Protection (SCP) Circuit Using
MCU
Figure 14 is typical application circuits for SCP function
using MCU, needs external amplifier circuit and comparator
circuits. In this reference design, SC trip level (VSC) is 0.3 V
(ISC(max)=60 A) and VREF level is 2.5 V.
To prevent malfunction, it is recommended that an RC filter
be inserted at the CSC pin. To shut down MOSFETs within
3 µs when over-current situation occurs, a time constant of
1.5 ~ 2 µs is recommended.
6.2. Fault Output Circuit
VFO terminal is an open-drain type; it should be pulled up
via a pull-up resistor. The resistor must satisfy the above
specifications
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40 TJ=150[oC]
VFO [V]
IFO [mA]
Figure 15. Voltage-Current Characteristics of
VFO Terminal
6.3. Circuit of Input Signal (IN(xH), IN(xL))
Figure 17 shows the I/O interface circuit between the MCU
and Motion SPM®45 LV series. Because the Motion SPM
45 LV input logic is active high and there are built-in pull-
down resistors, external pull-down resistors are not needed.
MCU SPM
5V-Line
IN(UH), IN(VH), IN(WH)
IN(UL), IN(VL), IN(WL)
VFO
COM
RPF=4.7k
CPF=1nF
Figure 16. Recommended CPU I/O Interface Circuit
Table 9. Maximum Ratings of Input and VF Pins
Symbol
Item
Condition
Rating
Unit
VIN
Input
Signal
Voltage
Applied between
IN(xH), IN(xL)-COM
-0.3 ~
VCC +0.3
V
VF
Fault
Supply
Voltage
Applied between
VF-COM
-0.3 ~
VCC +0.3
V
The input and fault output maximum rating voltages are
shown in Table 9. Since the fault output is open-drain
configured, its rating is VCC+0.3 V, 15 V supply interface is
possible. However, it is recommended that the fault output
be configured with the 5 V logic supply, which is the same
Amplifier
Comparator

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 16
as the input signals. It is also recommended that the de-
coupling capacitors be placed at both the MCU and Motion-
SPM ends of the VFO and the signal line as close as
possible to each device. The RC coupling at each input
(parts shown dotted in Figure 17 might change depending
on the PWM control scheme used in the application and the
.
5V-Line
IN(UH), IN(VH), IN(WH)
IN(UL), IN(VL), IN(WL)
VF
COM
RPF=10k
CPF=1nF
Motion SPM 45L
MCU
Gate
Driver
Level-Shift
Circuit
Typ. 5 k
Input
Noise
Filter
Input
Noise
Filter
Gate
Driver
Typ. 5 k
Figure 17. Recommended CPU I/O Interface Circuit
The µMini DIP family of Motion-SPM products employs
active-HIGH input logic. This removes the sequence
restriction between the control supply and the input signal
during startup or shutdown operation. Therefore, it makes
the system fail-safe. In addition, pull-down resistors are
built-in to each input circuit. External pull-down resistors
are not needed, reducing external components. The input
noise filter inside the Motion-SPM product suppresses short
pulse noise and prevents the MOSFET from malfunction
and excessive switching loss. Furthermore, by lowering the
turn-on and turn-off threshold voltages of the input signal,
as shown in Error! Reference source not found., a direct
connection to 3.3 V-class MCU or DSP is possible.
Table 10. Input Threshold Voltage Ratings
(VDD=15 V, TJ=25°C)
Symbol
Item
Condition
Min.
Max.
Unit
VIN(ON)
Turn-On
Threshold
Voltage
IN(UH), IN(VH),
IN(WH)-COM
2.6
V
VIN(OFF)
Turn-Off
Threshold
Voltage
IN(UL), IN(VL),
IN(WL)-COM
0.8
V
6.4. Bootstrap Circuit Design
6.4.1. Operation of Bootstrap Circuit
The VBS voltage, which is the voltage difference between
VB(U,V,W) and VS(U,V,W), provides the supply to the HVIC
within the motion SPM®45 LV series. This supply must be
in the range of 13.0 V~18.5 V to ensure that the HVIC can
fully drive the high-side MOSFET. The SPM 45 LV series
includes an under-voltage lock out protection function for
the VBS to ensure that the HVIC does not drive the high-side
MOSFET, if the VBS voltage drops below a specified
voltage (refer to the datasheet). This function prevents the
MOSFET from operating in a high dissipation mode.
There are a number of ways in which the VBS floating
supply can be generated. One of them is the bootstrap
method described here (refer to Figure 18). This method has
the advantage of being simples and inexpensive. However,
the duty cycle and on-time are limited by the requirement to
refresh the charge in the bootstrap capacitor. The bootstrap
to ground (either through the low-side or the load), the
bootstrap capacitor (CBS) is charged through the bootstrap
diode (DBS) and the resistor (RBS) from the VCC supply.
VS
HVIC
LVIC
VDC
VCC(L)
VB
VCC(H) VCC
IN(L)
CBS
CVCC
Motion-SPMTM
DBS
COM
VCC
COM
HO
HO
VSL
COM
VCC
VBS
IN(H)
IN(H)
IN(H)
OFF
ON
VB
RBS
Figure 18. Current path of Bootstrap Circuit
6.4.2. Selection of Bootstrap Capacitor
Considering Initial Charging
Adequate on-time of the low-side MOSFET to fully charge
the bootstrap capacitor is required for initial bootstrap
charging. The initial charging time (tcharge) can be calculated
by:

  
where:
VF= Forward voltage drop across the bootstrap diode;
VBS(min) =The minimum value of the bootstrap capacitor;
VLS = Voltage drop across the low-side MOSFET or load;
and
 Duty ratio of PWM
When the bootstrap capacitor is charged initially; VCC drop
voltage is generated based on initial charging method, VCC
line SMPS output current, VCC source capacitance, and
bootstrap capacitance. If VCC drop voltage reaches UVCCD
level, the low side is shut down and a fault signal is
activated.
To avoid this malfunction, the related parameter and initial
charging method should be considered. To reduce VCC
voltage drop at initial charging, a large VCC source capacitor
and selection of optimized low-side turn-on method are
recommended. Adequate on-time duration of the low-side
MOSFET to fully charge the bootstrap capacitor is initially
required before normal operation of PWM starts.
Figure 19 shows an example of initial bootstrap charging
sequence. Once VCC establishes, VBS needs to be charged by
turning on the low-side MOSFETs. PWM signals are
typically generated by an interrupt triggered by a timer with
a fixed interval, based on the switching carrier frequency.

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 17
Therefore, it is desired to maintain this structure without
creating complementary high-side PWM signals. The
capacitance of VCC should be sufficient to supply necessary
charge to VBS capacitance in all three phases. If a normal
PWM operation starts before VBS reaches VUVLO reset level,
the high-side MOSFETs cannot switch without creating a
fault signal. It may lead to a failure of motor start in some
applications. If three phases are charged synchronously,
initial charging current through a single shunt resistor may
exceed the over-current protection level.
Therefore, initial charging time for bootstrap capacitors
should be separated, as shown in Figure 20. The effect of
the bootstrap capacitance factor and charging method (low-
side MOSFET driving method) is shown in Figure 18.
VPN
VCC
VBS
VIN(L)
ON
Start PWM
VIN(H) OFF
0V
0V
0V
0V
0V
Section of charge pumping for VBS
: Switching or Full Turn on
Figure 19. Timing Chart of Initial Bootstrap Charging
…
…
…
…
…
VDC
VCC
Bootstrap capacitor charging(W phase)
IN(WL)
IN(VL)
IN(UL)
Bootstrap capacitor charging(V phase)
Bootstrap capacitor charging(U phase)
Bootstrap capacitor charging period System operating periode
…
Figure 20. Recommended Initial Bootstrap Capacitors
Charging Sequence
Figure 21 and Figure 22 shows waveform initial bootstrap
capacitor charging voltage and current.
Figure 21. Each Part Initial Operating Waveform of
Bootstrap Circuit (Conditions: VDC=20 V, VCC=15 V,
CBS=22 μF, LS MOSFET Turn-on Duty=200 μsec)
Figure 22. Each Part Operating Waveform of Bootstrap
Circuit (Conditions: VDC=20 V, VCC=15 V, CBS=22 μF, LS
MOSFET Full Turn-on)
6.4.3. Selection of Bootstrap Capacitor
Considering Operating
The bootstrap capacitance can be calculated by:
   

where:
t: maximum on pulse width of high-side MOSFET;
VBS: the allowable discharge voltage of the CBS
(voltage ripple); and
ILeak: maximum discharge current of the CBS.
Mainly via the following mechanisms:
Gate charge for turning the high-side MOSFET on
Quiescent current to the high-side circuit in HVIC
Level-shift charge required by level-shifters in HVIC
Leakage current in the bootstrap diode
CBS capacitor leakage current (ignored for non-
electrolytic capacitors)
Bootstrap diode reverse recovery charge
Practically, 2 mA of ILeak is recommended for FSB44104A
(IPBS, operating VBS supply current at 20 kHz, is max. 2 mA
in the datasheet). By considering dispersion and reliability,
the capacitance is generally selected to be 2~3 times the
calculated one. The CBS is only charged when the high-side
MOSFET is off and the VS(x) voltage is pulled down to
ground.
The on-time of the low-side MOSFET must be sufficient to
for the charge drawn from the CBS capacitor to be fully
replenished. This creates an inherent minimum on-time of
the low-side MOSFET (or off-time of the high-side
MOSFET).

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 18
0 2 4 6 8 10 12 14 16 18 20
0
10
20
30
40
50
60
70
80
90
100
110
6.8[F]
Continuous Sinusoidal Current Control
10[F]
22[F]
33[F]
47[F]
100[F]
CBS_min=(ILeak*t)/VBS
Conditions : VBS=0.1 [V], ILeak=4.5 [mA]
Minimum Value
Recommend Value
Commercial Capacitance
Bootstrap Capacitance, CBS [F]
Switching Frequency, FSW [kHz]
Figure 23. Capacitance of Bootstrap Capacitor on
Variation of Switching Frequency
Based on switching frequency and recommended BS
ILeak: circuit current = 10 mA
BS: discharged voltage = 2.0 V (recommended value)
: maximum on pulse width of high-side MOSFET =
2 ms (depends on user system)
   
    
More than 2~3 times 20~30 
Standard nominal capacitance 22 ~ 35 μF
6.4.4. Selection of Bootstrap Resistor Considering
Operating
A resistor must be added in series with the bootstrap diode
to slow down the dVBS/dt and determine the time to charge
the bootstrap capacitor. If the minimum ON pulse width of
low-side MOSFET or the minimum OFF pulse width of
high-side MOSFET is tO; the bootstrap capacitor must be
charged      V during this period.
Therefore, the value of bootstrap resistance can be
calculated by:
BS
ΔV
)(



BS
oBSCC
BS CtVV
R
where:
VCC = Supply voltage;
VBS = Minimum bootstrap voltage;
tO= Minimum ON pulse width;
CBS = Bootstrap capacitor value; and
VBS = Ripple voltage of VBS.
Calculation Examples of RBS:
VCC = 15 V, VBS = 13 V (minimum voltage)
tO= 200 µs (if carrier frequency is 5 kHz, 1-cylce is 200 µs)
CBS = 20 µF (obtained bootstrap capacitor value)
BS = 2 V (recommended value)
 






10
220 2001315 ΔV
)(
BS VF sV
CtVV
R
BS
oBSCC
BS


If the rising dVBS/dt is slowed significantly, it could cause
missing pulses during the startup phase due to insufficient
VBS voltage.
Note:
18. The capacitance value can be changed according to the
switching frequency, the capacitor selected, and the
recommended VBS voltage of 13.0~18.5 V (from
datasheet). The above result is just a calculation
example. This value can be changed according to the
actual control method and lifetime of the component.

AN-9111 APPLICATION NOTE
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.1 6/26/15 19
7. Print Circuit Board (PCB) Design
7.1. General Application Circuit Example
Figure 24 shows a general application circuitry of interface schematic with control signals connected directly to a MCU.
Figure 25 shows guidance of PCB layout for the Motion SPM®45 LV series.
Fault
+15V
CBS
CBS
CSP15
+5V
RPF
Motor VDC
CDCS
Gating UH
Gating VH
Gating WL
Gating VL
Gating UL
CPF
M
C
U
RSH
Current Sensing
RS
RS
RS
RS
RS
RS
RBS DBS
RBS DBS
LVIC
VFO
VCC
IN(UL)
IN(VL)
IN(WL)
COM
OUT(UL)
OUT(VL)
OUT(WL)
NW(5)
U (4)
V (3)
W (2)
P (1)
(21) VS(W)
(22) VB(W)
(19) VS(V)
(20) VB(V)
(8) VFO
(11) IN(WL)
(10) IN(VL)
(9) IN(UL)
(12) COM
HVIC
VB(W)
COM
VS(W)
(16) IN(WH)
(15) IN(VH)
(17) VS(U)
(18) VB(U)
(14) IN(UH)
OUT(WH)
NV(6)
NU(7)
VB(V)
VS(V)
VB(U)
VS(U)
VCC
IN(WH)
IN(VH)
IN(UH)
OUT(VH)
OUT(UH)
VS(W)
VS(V)
VS(U)
(13) VCC
CBS
RBS DBS
CPS CPS
CPS
Gating WH
CPS CPS
CPS
CBSF
CBSF
CBSF
CSP15F
Figure 24. General Application Circuitry for Motion SPM 45 LV series