Analog Devices EVAL-AD5679RSDZ User manual

EVAL-AD5679RSDZ User Guide
UG-1463
One Technology Way •P. O . Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluation Board for the AD5679R 16-Bit, 16-Channel, Voltage Output DAC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 13
FEATURES
Full featured evaluation board for the AD5679R
Various link options
PC control in conjunction with the Analog Devices, Inc., SDP
board
EVALUATION KIT CONTENTS
EVAL-AD5679RSDZ
USB cable
HARDWARE REQUIRED
EVAL-SDP-CB1Z (SDP-B) board, must be purchased separately
SOFTWARE REQUIRED
Analysis | Control | Evaluation software, available for
download from the EVAL-AD5679RSDZ product page
GENERAL DESCRIPTION
This user guide details the operation of the EVAL-AD5679RSDZ
for the AD5679R 16-bit, 16-channel, voltage output, digital-to-
analog converter (DAC).
The EVAL-AD5679RSDZ allows users to quickly prototype
AD5679R circuits and reduce design time. The AD5679R
operates from a single 2.7 V to 5.5 V supply range. The
AD5679R incorporates an internal 2.5 V reference to give an
output voltage of 2.5 V or 5 V. The EVAL-AD5679RSDZ also
incorporates additional voltage references.
The EVAL-AD5679RSDZ interfaces to the USB port of a PC
via a system demonstration platform (SDP-B) board. The
Analysis | Control | Evaluation (ACE) software is available for
download from the EVAL-AD5679RSDZ product page to use
with the evaluation board to allow the user to program the
AD5679R. A peripheral module interface (PMOD) connection
is also available to allow the connection of microcontrollers to
the evaluation board without the SDP-B board. When a
microcontroller is used through the PMOD connection, the
SDP-B board must be disconnected, and the user is unable to
operate the ACE software.
The EVAL-AD5679RSDZ is compatible with any Analog
Devices, Inc., SDP-B board, which can be purchased separately.
A typical connection between the EVAL-AD5679RSDZ and the
SDP-B controller board is shown in Figure 1.
For full details, see the AD5679R data sheet, which must be
used in conjunction with this user guide when using the EVAL-
AD5679RSDZ.
EVALUATION BOARD PHOTOGRAPH
17275-001
Figure 1. EVAL-AD5679RSDZ

UG-1463 EVAL-AD5679RSDZ User Guide
Rev. 0 | Page 2 of 13
TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Hardware Required .......................................................................... 1
Software Required ............................................................................ 1
General Description......................................................................... 1
Evaluation Board Photograph......................................................... 1
Revision History ............................................................................... 2
Evaluation Board Software Quick Start Procedures .................... 3
Installing the Software ................................................................. 3
Initial Setup ................................................................................... 3
Functional Block Diagram and Description..................................4
Memory Map .................................................................................5
Evaluation Board Hardware.............................................................6
Power Supplies...............................................................................6
Link Options ..................................................................................6
On-Board Connectors ..................................................................6
Evaluation Board Schematics and Artwork...................................7
Ordering Information.................................................................... 12
Bill of Materials........................................................................... 12
REVISION HISTORY
8/2019—Revision 0: Initial Version

EVAL-AD5679RSDZ User Guide UG-1463
Rev. 0 | Page 3 of 13
EVALUATION BOARD SOFTWARE QUICK START PROCEDURES
INSTALLING THE SOFTWARE
The E VA L -AD5679RSDZ uses the ACE evaluation
software, which allows the evaluation and control of multiple
evaluation systems.
The ACE installer installs the necessary SDP-B drivers and the
Microsoft® .NET Framework 4 by default. The ACE software is
available for download from the E VA L-AD5679RSDZ product
page and must be installed before connecting the SDP-B board
to the USB port of the PC to ensure that the SDP-B board is
recognized connected to the PC. For full instructions on how to
install and use this software, see the ACE software page on the
Analog Devices website.
After the installation is finished, the E VA L -AD5679RSDZ plug-
in appears when the ACE software is opened.
INITIAL SETUP
To se t up the evaluation board, take the following steps:
1. Connect the evaluation board to the SDP-B board, and
then connect the USB cable between the SDP-B board and
the PC.
2. Run the ACE application. The EVAL-AD5679RSDZ plug-
ins appear in the attached hardware section of the Start
tab.
3. Double-click the board plug-in to open the board view
seen in Figure 2.
4. Double-click the AD5679Rchip to access the chip block
diagram. This view provides a basic representation of the
functionality of the board. The main functions of the board
are labeled in Figure 3.
17275-002
Figure 2. Board View of the EVAL-AD5679RSDZ
17275-003
Figure 3. Chip Block Diagram of the AD5679R

UG-1463 EVAL-AD5679RSDZ User Guide
Rev. 0 | Page 4 of 13
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION
The EVAL-AD5679RSDZ software is organized to appear
similarly to the functional block diagram shown in the
AD5679R data sheet, which simplifies correlating the functions
on the E VA L -AD5679RSDZ with the description in the
AD5679R data sheet.
For a full description of each block, register, and its settings, see
the AD5679R data sheet.
Some of the blocks and their functions are described in this
section as they pertain to the evaluation board. The full screen
block diagram is shown in Figure 4. Table 1 describes the
functionality of each block.
AC
B
FG
EH
D
J
I
17275-004
Figure 4. AD5679R Block Diagram with Labels
Table 1. Block Diagram Functions (See Figure 4)
Label Button/Function Name Function
A CONFIGURATION
wizard
Used to set the initial configuration for the board. Select the reference gain case from the Output Gain
dropdown menu. A gain of 1 is the default. After setting up the initial configuration, click Apply to
apply the values. These settings can be modified at any stage while evaluating the board.
B LDAC and RESET (GPIO
buttons)
Act as external GPIO pulses to the LDAC pin and RESET pin. The LDAC button pushes data from both
input registers (Label D) to the DAC registers (Label E). The RESET button clears all data from input
registers and DAC registers. These buttons are live and there is no need to click Apply Changes (Label J).
C Select a Command Command option dropdown menu selects how the data being transferred to the device affects the
input registers and DAC registers. After a data value is entered in an input register (Label D), this menu
determines if the data is transferred to the input register only, or to the channel input register (Label D)
and the channel DAC register (Label E).
D Input Register 0
through Input
Register 3
16-bit data word to be transferred to the device. Click Apply Changes (Label J) to transfer this 16-bit
data word to the device.
E DAC Register 0 through
DAC Register 3
Displays the value that is currently present in the DAC register on the device. Update the DAC registers
by selecting the appropriate command option or by toggling LDAC (Label B).
F Software RESET Returns the evaluation board and software to default values. This button is live. Therefore, there is no
need to click Apply Changes.
G Load DAC Users can individually control which channel loads the values from the input registers to the DAC register.
H DAC
DAC configuration options provide access to individual channel configuration options such as power-
down options and hardware LDAC mask enable and disable settings.
I Internal Reference Select Enable from this setting to enable the on-chip reference for the evaluation board. If Disable is
selected, an external reference must be applied. This control is only available on the AD5679R.
J Apply Changes Applies all modified values to the device. Note that if an evaluation board is not connected, values
entered in the input registers are not transferred to the DAC registers.

EVAL-AD5679RSDZ User Guide UG-1463
Rev. 0 | Page 5 of 13
MEMORY MAP
All registers are fully accessible from the AD5679R Memory
Map tab, shown in Figure 5. This tab allows registers to be
edited at bit level. The bits shaded in dark gray are read-only
bits and cannot be accessed from the ACE software. All other
bits are toggled.
Clicking the Apply Changes button transfers data to the device.
All changes made in the memory map tab correspond to the
block diagram. For example, if the internal register bit is enabled,
it displays as enabled on the block diagram. Any bits or registers
that are shown in bold in the memory map tab are modified
values that have not been transferred to the evaluation board
(see Figure 6). Click Apply Changes to transfer the data to the
evaluation board.
17275-005
Figure 5. AD5679R Memory Map Tab
17275-006
Figure 6. AD5679R Memory Map with Unapplied Changes in the
DAC0_Input Register

UG-1463 EVAL-AD5679RSDZ User Guide
Rev. 0 | Page 6 of 13
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5679RSDZ provides on-board 3.3 V and 5 V
regulators powered through the USB supply or from an external
source. If a different supply is required or if the evaluation board
is controlled through the PMOD connector, an external supply
must be provided by the external supply voltage (EXTSUP)
connector. See Table 2 for more details.
Every supply is decoupled to ground with 10 µF tantalum and
0.1 µF ceramic capacitors.
LINK OPTIONS
A number of link options are incorporated on the E VA L -
AD5679RSDZ and must be set for the required operating
conditions before using the board. The functions of these link
options are described in Table 3.
Table 2. Power Supply Connectors
Connector Label External Voltage Supplies Description
EXT S U P, Pin 1 External analog power supply from 2.7 V to 5.5 V.
E X T S U P, Pin 2 Analog ground.
VREF_CONN External voltage reference.
Table 3. Link Functions
Link Description
LK1
This link selects the primary analog voltage source for the 3.3 V output and 5 V output for LK2. There are two options,
as follows:
The USB option selects the USB supply from Pin 5 of the 120-pin connector of the SDP-B board.
The EXT option selects an EXTSUP connector. Voltage applied to EXTSUP must be between 2.7 V to 5.5 V.
LK2 This link selects the DAC analog voltage source. There are three options, as follows:
The 5V0 option selects the on-board 5 V source from the LTC3536.
The 3V3 option selects the on-board 3.3 V source from the ADM7160.
The EXT option selects an EXTSUP connector. Voltage applied to EXTSUP must be between 2.7 V to 5.5 V.
LK3 This link selects the gain setting for the DAC. There are three options, as follows:
The gain option allows the ACE plugin to control the gain setting of the device.
The high option selects gain = 2.
The low option selects gain = 1.
ON-BOARD CONNECTORS
Table 4 shows the connectors on EVAL-AD5679RSDZ.
Table 4. On-Board Connectors
Connector Function
EXTSUP
External analog power supply from 2.7 V to 5.5 V.
VREF_CONN External voltage reference.
P2 DAC outputs from VOUT0 to VOUT7.
P3 DAC outputs from VOUT8 to VOUT15.

EVAL-AD5679RSDZ User Guide UG-1463
Rev. 0 | Page 7 of 13
EVALUATION BOARD SCHEMATICS AND ARTWORK
SDP, PMOD AND ARDUINO INTERFACE
AGND
GAIN
6-PIN I2C PMOD CONNECTOR
SDIN SDO SCLK SDA_0 SCL_0 LDACB
VDD VIO
VIO: USE TO SET IO VOLTAGE MAX DRAW 20MA USE ONLY TOPOWER THE EEPROM(3MA MAX DRAW)
12-PIN SPI PMOD CONNECTOR
VIO AGND SDA_0 SCL_0 RESETB
THE SDP CONNECTOR IMPLEMENTS THE E13 CONNECTOR SPECIFICATIONS STANDARD. THIS IS A STANDARD FOR USE ACROSS ADIAND CANNOT BE MODIFIED
LDACB
VIN:USE THIS PIN TO POWER THE SDP REQUIRES 5V 300MA
BMODE1:PULL UP WITH A 10K RESISTOR TO SET SDP TOBOOT FROM A SPI FLASH ON THEDAUGHTER BOARD
WHEN USINGSPI INTERFACE,BE AWARE OFADDING A PULL UP
SYNCB RESETB
ARDUINOINTERFACE HEADERS
SINCE SPIIS A SHARED BUS, ENSURE THAT ANY SPI DEVICE ON DAUGHTER BOARD IS NOT ACTIVELY DRIVING THE MISODATA LINE UNLESS PROPERLY ADDRESSED WITH AN ACTIVE LOW CHIP SELECT. ENSURE ALSOTHAT THE SPI CLK LINE IS NOT HELD RESULT TO A NON-FUNCTIONAL SYSTEM.
SPI_SEL1/SPI_SS MUST BE ONLY USED WITH EXTERNAL SPI FLASH
12C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED (CONNECTED TOBLACKFIN GPIO - USE 12C_0 FIRST)
MAIN 12C BUS (CONNECTED TO BLACKFIN TWI- PULL UP RESISTORS NOT REQUIRED)
HIGH OR LOWBY YOUR BOARD AT POWER UP. FAILURE TOMEET THIS ON THE SPI_SEL_A/B/C LINES THAT ARE ACTIVE LOW ENABLED
SDP CONNECTOR
FX8-120S-SV(21)
0
DNI
0
DNI
0DNI
0
0
0
SSQ-106-03-G-S
DNI 0
0
DNI SSQ-108-03-G-S
SSQ-108-03-G-S
DNI
2.7K
DNI
2.7K
DNI
DNI SSQ-110-03-G-S
DNI
DNI
DNI
TSW-106-08-G-D TSW-106-08-G-S
0
DNI TOL = 1
TOL = 1
DNI
24LC32A-I/ST
EEPROM BOARD ID EEPROM(24LC32)MUST BE ON I2C BUS 0
TSSOP8
TOL=1
R43
R44
R42
R41
R39
R38
R37
R12
SPI_PMOD
R32
R31
I2C_PMOD
P6
P7
P5
P1
C2 10UF
SDP C25
0.1UF
U1
R1 100K R0603 R3 100K R0603
R2 100K R0603
R20 R0603 100K
R13
SDIN SDO SCLK
LDACB
RESET GAIN
USB_SUPPLY
RESETB LDACB GAIN
VIO
SDO
SYNCB
SCLK SDIN
SDA_0 SCL_0
VIO
VDD
RESETB
LDACB
GAIN AGND
RESETB
SYNCB VIO
LDACB SCL_0 SDA_0
VIO
AGND SDIN
VIO
SDO SCLK
VIO
VIO
SYNCB
SCL_0 SDA_0
VIO
AGND
126
10 9 8 7
4 3 2 1
115
6 5 4 3 2 1
10
9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1 6 5 4 3 2 1
116 65
1 5
6259 7249 7348 87 89
30 29 92
90
32
88
31
91
38 37
85
39
84 83
34 33
82 64
35 41 80 42 79 57 60
10021 99
26 95 27
7114 8113 9112
10 111
110
12 13 108 14 107 15 106 16 105 18 103 19 102 20 101 22
94
24 97 25 96
120 119 70 68 67 6655
54 53 51 50
2
7447 7645 7744 7843 118 117 115 109 104 98 93 86 81 75 69 6358
52 46 40 36 28 23 17 11
6 4 3
56
71 61
7
4 8
5
6 3 2 1
VCC
GND
P10
P9 P8 P7
VCC GND P4 P3 P2 P1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
SPI_SEL_A_N
CLKOUT
NC NC
GND GND
VIO
GND
PAR_D22 PAR_D20 PAR_D18 PAR_D16 PAR_D15
GND
PAR_D12 PAR_D10
PAR_D8 PAR_D6
GND
PAR_D4 PAR_D2 PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2 PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0 SPORT_RFS
SPORT_TFS SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0 GPIO1 GPIO3 GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC NC NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX GND RESET_OUT_N EEPROM_A0 NC NC NC GND NC NC TMR_C TMR_A GPIO6 GND GPIO4 GPIO2 GPIO0 SCL_1 SDA_1 GND SPI_SEL1/SPI_SS_N SPI_SEL_C_N SPI_SEL_B_N GND SERIAL_INT SPI_D3 SPI_D2 SPORT_DT1 SPORT_DR1 SPORT_TDV1 SPORT_TDV0 GND PAR_FS1 PAR_FS3 PAR_A1 PAR_A3 GND PAR_CS_N PAR_RD_N PAR_D1 PAR_D3 PAR_D5 GND PAR_D7 PAR_D9 PAR_D11 PAR_D13 PAR_D14 GND PAR_D17 PAR_D19 PAR_D21 PAR_D23 GND USB_VBUS GND GND NC VIN
VSS
VCC
WP A2 A1 A0 SCL
SDA
17275-007
Figure 7. EVAL-AD5679RSDZ Schematic, SDP, Arduino®-Compatible, PMOD Connectors

UG-1463 EVAL-AD5679RSDZ User Guide
Rev. 0 | Page 8 of 13
LABEL LINKS: A: USB_SUPPLY B: EXTSUP
PWR_SEL
CONNECT PGND AND AGND IN SUCH A WAY
TO MINIMIZE THE NOISE TO COUPLE
VDD_SEL
VDD CIRCUIT
PGND AGND INTERCONNECT
VREF CIRCUIT
MAIN CIRCUIT
– +
LABEL LINKS: 1–2: 5V 3–4: 3.3V 5–6: EXT_SUP
LABEL LINKS: 1-2: GAIN
DAC CIRCUIT
5-6: LOW 3-4: HIGH
SPI <-> I2C OPTION
GAIN_SEL
1UF
M20-9990345
LTC3536EDD#PBF
4.7UH
100K
150K
DNI
15PF
68PF
150K
21.5K 15PF
1.1MEG
22UF
1UF
OSTTC022162
0
RED
0 0
DNI
TSW-103-08-G-D
AD5679RBCPZ-1
0.1UF 10UF
DNI
0.1UF
DNI
0 0
DNI
0 0
DNI
0 0 0DNI 0
4.7UF
4.7UF
0.1UF
10UF
10UF
1-1337482-0
ADM7160ACPZN3.3
TSW-103-08-G-D
BLK
U2
C22
C23
R46
R45
C21
C33
C5
L1
R35
C9
R47
C8
R36
R40
TP1
TP2
VREF_CONN
C12
C11
LK3
C3
C18
LK1
U4
R33 R34
C4 C6
C1
U3
R8 R4 R5 R9
R14 R15 R16 R17
LK2
EXTSUP
USB_SUPPLY
VIO VREF
VDD
GAIN_IN
GAIN
SYNCB_SCL
VOUT0 VOUT1
VOUT14
RESETB
SYNC_SCL SCLK_A0 SDIN_A1
VREF
VOUT15 VOUT11
SDIN
LDACB VDD
VIO
SDIN_A1
VOUT5
SDO
VIO
SDO_SDA
VOUT12
GAIN_IN
SDO_SDA
SDA_0
VOUT7
SCLK_A0
SCL_0
VOUT2 VOUT3 VOUT4
VOUT13
SYNCB SCLK VIO
VREF
VOUT10
VOUT8 VOUT9 VOUT6
VDD
67 10 54 82
1
PAD
3 9
1
1
5432
1
65 43 21
N P
3
2
1
16
PAD
5 2
34
21
2 81
3
19
5 4
20 17
6
PAD
11 12 13 14 22 23 24 25 7 8 9 10 26 27 28 1
15 61
65 43 21
2 1
B A
PAD
VIN NC ENGND NC
VOUT
AGNDAGND
AGND
VREFOUT
VLOGICVDD
SYNC
SDO
SDI SCLK RESET LDAC GAIN
EPAD
DAC15 DAC14 DAC13 DAC12 DAC11 DAC10
DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
AGNDAGND
PGND
VC
FB
SHDN_N
VIN VOUT
SW2SW1
MODE/SYNC SGND RT
PGND
PGND
PGND
PGNDPGND
PGNDPGND
PGND
AGNDPGND
PGND
PGND
PGND
PGNDPGNDPGND
AGND
AGND
AGND
AGND
17275-008
RESET LDAC
Figure 8. EVAL-AD5679RSDZ Schematic, Main Circuit

EVAL-AD5679RSDZ User Guide UG-1463
Rev. 0 | Page 9 of 13
BNC OUTPUTS
HEADER OUTPUTS
VOUT1
VOUT0
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
200PF 2.0K
1-1337482-0
1-1337482-0
200PF
DNI
1-1337482-0
DNI
67996-416HLF
DNI
2.0K
DNI
1-1337482-01-1337482-0
DNI
2.0K
2.0K
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNIDNI
1-1337482-0
1-1337482-0
DNIDNI
2.0K
DNI
2.0K
DNI
DNI
1-1337482-0
DNI
DNI
DNI
DNI
200PF
DNI
200PF
DNI
200PF
DNI
200PF
DNI
200PF
DNI
DNI
200PF
DNI
DNI
200PF
DNI
2.0K
DNI
2.0K
1-1337482-0
200PF
2.0K
1-1337482-0
DNI
DNIDNI
1-1337482-0 1-1337482-0
DNI
1-1337482-0
1-1337482-0
2.0K
DNI
1-1337482-0
DNI
DNI
DNI DNI
1-1337482-0
67996-416HLF
DNI DNI
2.0K
200PF
DNI
2.0K
2.0K
2.0K
2.0K
DNI
200PF
200PF
200PF
200PF
DNI
200PF
DNI
2.0K
C24
C26
C27
C28
C29
C30
C31
C32C20
C19
C17
C16
C15
C14
C13
C7
P3
R6
VOUT_0
R30
R29
R28
R27
R26
R25
VOUT_15
VOUT_14
VOUT_13
VOUT_12
VOUT_11
VOUT_10
R24
R23
VOUT_9
VOUT_8
R22
VOUT_7
VOUT_6
R21
VOUT_5
R19
VOUT_4
R18
VOUT_3
R11
VOUT_2
R10
R7
VOUT_1
P2
VOUT5
VOUT7
VOUT3
VOUT9
VOUT8
VOUT6
VOUT7
VOUT3
VOUT4
VOUT14
VOUT0
VOUT4
VOUT5
VOUT1
VOUT6
VOUT10
VOUT2
VOUT11
VOUT13
VOUT12
VOUT15
VOUT11
VOUT14
VOUT0
VOUT2
VOUT13
VOUT12
VOUT10
VOUT1
VOUT15
VOUT9
VOUT8
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGND
AGND
AGND
17275-009
Figure 9. EVAL-AD5679RSDZ Schematic, Output Connectors

UG-1463 EVAL-AD5679RSDZ User Guide
Rev. 0 | Page 10 of 13
17275-010
Figure 10. EVAL-AD5679RSDZ Top Side Component Placement
17275-011
Figure 11. EVAL-AD5679RSDZ Top Side Routing
17275-012
Figure 12. EVAL-AD5679RSDZ Bottom Side Component Placement