Analog Devices EVAL-AD5693RSDZ User manual

EVAL-AD5693RSDZ User Guide
UG-675
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the AD5693R Single-Channel, 16-Bit, Serial, Voltage Output DAC
Rev. A | Page 1 of 12
FEATURES
Full featured evaluation board for the AD5693R
On-board reference
Various link options
PC control in conjunction with the Analog Devices, Inc., SDP
PC software for control of DACs
On-board ADC for voltage readback
EVALUATION KIT CONTENTS
EVAL-AD5693RSDZ evaluation board
AD5693R device
HARDWARE REQUIRED
EVAL-SDP-CB1Z (SDP-B) board or EVAL-SDP-CS1Z (SDP-S)
board, must be ordered separately
SOFTWARE REQUIRED
ACE evaluation software, available for download from the
EVAL-AD5693RSDZ product page
GENERAL DESCRIPTION
This user guide details the operation of the EVAL-AD5693RSDZ
evaluation board for the AD5693R single-channel, serial, voltage
output, digital-to-analog converter (DAC).
The EVAL-AD5693RSDZ is designed to help customers quickly
prototype AD5693R circuits and reduce design time. The
AD5693R operates from a single 2.7 V to 5.5 V supply. The
AD5693R incorporates an internal 2.5 V on-board reference to
give an output voltage span of 2.5 V or 5 V.
The EVAL-AD5693RSDZ evaluation board interfaces to the USB
port via the SDP board. The analysis control evaluation (ACE)
software is available for download from the EVAL-AD5693RSDZ
product page to use with the evaluation board to allow the user
to program the AD5693R. The EVAL-AD5693RSDZ evaluation
board requires the purchase of the EVAL-SDP-CB1Z (SDP-B)
board or the EVAL-SDP-CS1Z (SDP-S) board.
For full details, consult the AD5693R data sheet, which must be
used in conjunction with this user guide when using the
evaluation board.
EVAL-AD5693RSDZ EVALUATION BOARD CONNECTED TO THE SDP-S BOARD
12145-001
Figure 1.

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TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Hardware Required .......................................................................... 1
Software Required ............................................................................ 1
General Description ......................................................................... 1
E VA L-AD5693RSDZ Evaluation Board Connected to the SDP-S
Board .................................................................................................. 1
Revision History ............................................................................... 2
Evaluation Board Quick Start Procedures..................................... 3
Installing the Software ................................................................. 3
Initial Setup ....................................................................................3
Block Diagram and Description......................................................5
Memory Map .................................................................................6
Evaluation Board Hardware.............................................................7
Power Supplies ...............................................................................7
Link Options ..................................................................................7
Evaluation Board Schematics and Artwork...................................8
Ordering Information.................................................................... 11
Bill of Materials........................................................................... 11
REVISION HISTORY
7/2017—Rev. 0 toRev. A
Reorganized Layout............................................................Universal
Deleted Additional Equipment Needed Section .......................... 1
Added Hardware Required Section and Software Required
Section................................................................................................ 1
Changes to Title, Evaluation Kit Contents Section, General
Description Section, E VA L -AD5693RSDZ Evaluation Board
Connected to the SDP-S Board Section, and Figure 1 Caption . 1
Deleted Getting Started Section ..................................................... 3
Added Evaluation Board Quick Start Procedures Section,
Initial Setup Section, and Figure 2; Renumbered Sequentially .. 3
Changes to Installing the Software Section................................... 3
Added Figure 3.................................................................................. 4
Deleted How to Use the Software Section, Running the Software
Section, Figure 2, and Figure 3, and Figure 4; Renumbered
Sequentially ....................................................................................... 5
Added Block Diagram and Description Section, Figure 4,
Table 1; Renumbered Sequentially..................................................5
Deleted Software Operation Section and Figure 5........................6
Added Memory Map Section, Figure 5, and Figure 6 ..................6
Moved Evaluation Board Hardware Section..................................7
Changes to Power Supplies Section, Table 2, Link Options
Section, and Table 4...........................................................................7
Changes to Figure 7 Caption............................................................8
Changes to Figure 8 Caption............................................................9
Changes to Figure 9 Caption, Figure 10 Caption, and Figure 11
Caption ............................................................................................ 10
Deleted Components List Section................................................ 11
Added Bill of Materials Section.................................................... 11
Changes to Table 5.......................................................................... 11
3/2014—Revision 0: Initial Version

EVAL-AD5693RSDZ User Guide UG-675
Rev. A | Page 3 of 12
EVALUATION BOARD QUICK START PROCEDURES
INSTALLING THE SOFTWARE
The EVAL-AD5693RSDZ evaluation board uses the ACE
software, a desktop software application that allows the
evaluation and control of multiple evaluation systems.
The ACE installer installs necessary SDP drivers and the
Microsoft® .NET Framework 4 by default. The ACE software is
available for download from the EVAL-AD5693RSDZ product
page and must be installed before connecting the SDP board to the
USB port of the PC, to ensure that the SDP board is recognized
when it connects to the PC. For full instructions on how to install
and use this software, see the ACE software page on the Analog
Devices website.
After the installation is finished, the EVAL-AD5693RSDZ
evaluation board plug in appears when the ACE software is
opened.
INITIAL SETUP
To set up the evaluation board, take the following steps:
1. Connect the evaluation board to the SDP board, and then
connect a USB cable between the SDP board and the PC.
2. Run the ACE application. The EVAL-AD5693RSDZ board
plug ins appear in the attached hardware section of the
Start tab.
3. Double click the board plug in to open the board view,
shown in Figure 2.
4. Double click the AD5693R chip to access the chip block
diagram. This view provides a basic representation of
functionality of the board. The main function blocks of the
board are labeled in Figure 3.
12145-102
Figure 2. Board View of the EVAL-AD5693RSDZ

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Rev. A | Page 4 of 12
12145-103
Figure 3. Chip Block Diagram View of the AD5693R

EVAL-AD5693RSDZ User Guide UG-675
Rev. A | Page 5 of 12
BLOCK DIAGRAM AND DESCRIPTION
The EVAL-AD5693RSDZ software is organized to appear
similar to the functional block diagram shown in the AD5693R
data sheet. Therefore, correlating the functions on the EVAL-
AD5693RSDZ evaluation board with the description in the
AD5693R data sheet is simplified.
For a full description of each block, register, and its settings, see
the AD5693R data sheet.
Some of the blocks and their functions are described in this section
as they pertain to the evaluation board. The block diagram is
shown in Figure 4. Table 1 describes the functionality of each block.
12145-104
J
ACI
BFDGE H
Figure 4. AD5693R Block Diagram with Labels
Table 1. Block Diagram Functions (See Labels in Figure 4)
Label Button/Function Name Description
A CONFIGURATION Wizard Used to set the initial configuration for the board. Select the reference gain case from the Output
Gain dropdown menu. A gain of 1 is the default. After setting up the initial configuration, click Apply to
apply the values. These settings can be modified at any stage while evaluating the board.
B LDAC and RESET (GPIO
buttons)
Act as external GPIO pulses to the LDAC and RESET pins. The LDAC button transfers data from the input
register (D) to the DAC register (E). The RESET button clears all data from the input register and the
DAC register. These buttons are live; therefore, there is no need to click Apply Changes (J).
C Select a Command Command option dropdown menu selects how the data being transferred to the device affects the
input and DAC registers. After a data value is entered in the input register (D), this menu determines
the internal DAC registers affected by updating the input register (D). After a new value is written in
the input register (D), the data can be transferred to the DAC input register, or to the DAC input
register and the DAC register simultaneously. If the data is transferred to both registers, the channel
DAC register (E) reflects the new value.
D Input register 16-bit data word to be transferred to the device. Click Apply Changes (J) to transfer this 16-bit data
word to the device.
E DAC register Displays the value that is currently present in the DAC register on the device. Update the DAC register
by selecting the appropriate command option or by toggling LDAC (B).
F Software RESET Returns the evaluation board and software to default values. This button is live; therefore, there is no
need to click Apply Changes (J).
G Load DAC Users can individually control which channel loads the values from the input register to the DAC register.
Note that the AD5693R is a single-channel DAC and only offers one channel option for the Load DAC
function.
H DAC DAC configuration options provide access to individual channel configuration options such as power-
down options and hardware LDAC mask enable/disable settings.
I Internal Reference Select Enable from this setting to enable the on-chip reference for the evaluation board. If Disable is
selected, an external reference must be applied. This control is only available on the AD5693R.
J Apply Changes Applies all modified values to the device. Note that if an evaluation board is not connected, values
entered into the input register are not transferred to the DAC register.

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MEMORY MAP
All registers are fully accessible from the AD5693R Memory
Map tab, shown in Figure 5. To navigate to this tab, click the
Proceed to Memory Map button, shown in Figure 4. This tab
allows registers to be edited at the bit level. The bits shaded in
dark gray are read-only bits and cannot be accessed from the
ACE software. All other bits are toggled.
Clicking the Apply Changes button transfers data to the device.
All changes made in the memory map tab correspond to the block
diagram. For example, if the internal register bit is enabled, it
displays as enabled on the block diagram. Any bits or registers
that are in bold in the memory map tab are modified values that
have not been transferred to the evaluation board (see Figure 6).
Click Apply Changes to transfer the data to the evaluation board.
12145-105
Figure 5. AD5693R Memory Map Tab
12145-106
Figure 6. AD5693R Memory Map with Unapplied Changes in the
DAC0_Input Register

EVAL-AD5693RSDZ User Guide UG-675
Rev. A | Page 7 of 12
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The AD5693R evaluation board can be powered through the
SDP board or externally by the VPOS_EXT and AGND
connectors.
Both AGND and DGND inputs are provided on the board. The
AGND and DGND planes are connected at one location close to
the AD5693R. To avoid ground loop problems, it is recommended
not to connect AGND and DGND elsewhere in the system.
All supplies are decoupled to ground with 10 µF tantalum and
0.1 µF ceramic capacitors.
Table 2. Power Supply Connectors
Connector No. Voltage
J2, Pin 1 Analog positive power supply, V_EXT
J2, Pin 2 AGND
LINK OPTIONS
Various link and switch options are incorporated on the E VA L -
AD5693RSDZ evaluation board and must be set for the required
operating conditions before using the board. The functions of
these link options are described in detail in Table 4.
Table 3 describes the positions of the different links controlled
by the PC via the USB port. An SDP board operating in single-
supply mode is required.
Table 3. Link Options Setup for SDP Control (Default)
Link No. Options
A11 A
LINK Disconnected
A1 A
Table 4. Link Functions
Link No. Options
A1 This link selects the DAC digital voltage source.
Position A selects an external reference source via the SMB input, EXT_REF.
Position B selects the REF192 external reference.
Position C selects the ADR431 external reference.
LINK Connect only if the EVAL-AD5693RSDZ board of the AD5693R is controlled through the PMOD connector and the SDP
board is not connected.
A11 This link selects the DAC analog voltage source.
Position A VPOS is powered at 3.3 V.
Position B VPOS is powered from an unregulated USB supply.
Position C VPOS is powered from an external supply voltage (V_EXT).

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EVALUATION BOARD SCHEMATICS AND ARTWORK
PLEASE LABEL TP AS PER THE NET IT IS CONNECTED TO
PLEASE LABEL TP AS PER
THE NET IT IS CONNECTED TO
PMOD CONNECTOR
nanoDAC+
ANALOG SUPPLY
REFERENCE
DIGITAL SUPPLY
CONNECT ONLY IF
THE SDP IS NOT CONNECTED
LABELS:
EXT
REF192
ADR431
LABELS:
3V3
5V
V_EXT
C8
0.1µF +C7
10µF
±20%
1VIN 2GND 3EN
5
VOUT
4
NC
U5
ADP121
C4
1µF
C5
1µF
6
OUTPUT
2VS 3SLEEP
4
GND
U3
REF192
8SDA 6A0 7SCL 4LDAC
10
VOUT
2VLOGIC 3RESET
1
VDD 9
VREF
5
GND
U1
AD5693R
C10 0.1µF
+
C9
10µF
±20%
TP6TP9TP3 TP1 TP2
R12
DNP
VOUT
TP4
C6
DNP
EXT_REF
J2-1
J2-2
2+VIN
4
GND
5
TRIM
7COMP
6
VOUT
U8
ADR431BRZ
J5-1 J5-2
J5-3 J5-4
J5-5 J5-6
J5-7 J5-8
J5-9 J5-10
J5-11 J5-12
C1 0.1µF
+
C2
10µF
±20%
A
B C
A11
A
B C
A1
LINK
LDAC
RESET
SYNC/SCL
SCLK/A0
SDIN/SDA
V_IO
VPOS
VPOS
+5V
VPOS VREF
VREF
VPOS
VREF
RESET
SCLK
SYNC
SDIN
LDAC
VPOS V_IO
V_IO SDA
SCL
+5V
+5V
VPOS
DGND
12145-006
Figure 7. EVAL-AD5693RSDZ Schematic—Power Supply and Signal Routes

EVAL-AD5693RSDZ User Guide UG-675
Rev. A | Page 9 of 12
VIN: USE THIS PIN TO POWER THE SDP REQUIRES 5V 200mA
VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA
BOARD ID EEPROM (24LC32) MUST BE ON I2C BUS 0
BMODE1: PULL UP WITH A 10kΩ RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD.
MAIN I2C BUS (CONNECTED TO BLACKFIN TWI; PULL UP RESISTORS NOT REQUIRED)
AD5683R -> AD5693R
CONNECTOR
STANDARD
SDP
PARALLEL
PORT
SPORT
SPI
I2C
GENERAL
INPUT/OUTPUT
TIMERS
*NC ON BLACKFIN SDP 120
NC
119
NC
118
GND
117
GND
116
VIO(+3.3V)
115
GND
114
*PAR_D22
113
*PAR_D20
112
*PAR_D18
111
*PAR_D16
110
PAR_D15
109
GND
108
PAR_D12
107
PAR_D10
106
PAR_D8
105
PAR_D6
104
GND
103
PAR_D4
102
PAR_D2
101
PAR_D0
100
PAR_WR
99
PAR_INT 98
GND
97
PAR_A2
96
PAR_A0
95
PAR_FS2
94
PAR_CLK
93
GND
92
SPORT_RSCLK
91
SPORT_DR0
90
SPORT_RFS
89
SPORT_TFS
88
SPORT_DT0
87
SPORT_TSCLK
86
GND
85
SPI_SEL_A
84
SPI_MOSI
83
SPI_MISO
82
SPI_CLK
81
GND
80
SDA_0
79
SCL_0
78
GPIO1
77
GPIO3
76
GPIO5
75
GND
74
GPIO7
73
TMR_B
72
TMR_D
71
NC
70
NC
69
GND
68
NC
67
NC
66
NC
65
NC
64
NC
63
GND
62
UART_TX
61
BMODE1
60 RESET_IN
59 UART_RX 58 GND 57 NC 56 EEPROM_A0 55 NC 54 NC 53 NC 52 GND 51 NC 50 NC 49 TMR_C* 48 TMR_A 47 GPIO6 46 GND 45 GPIO4 44 GPIO2 43 GPIO0 42 SCL_1 41 SDA_1 40 GND 39 SPI_SEL1/SPI_SS 38 SPI_SEL_C 37 SPI_SEL_B 36 GND 35 SPORT_INT 34 SPORT_DT3* 33 SPORT_DT2* 32 SPORT_DT1 31 SPORT_DR1 30 SPORT_DR2* 29 SPORT_DR3* 28 GND 27 PAR_FS1 26 PAR_FS3 25 PAR_A1 24 PAR_A3 23 GND 22 PAR_CS
21 PAR_RD 20 PAR_D1 19 PAR_D3 18 PAR_D5 17 GND 16 PAR_D7 15 PAR_D9 14 PAR_D11 13 PAR_D13 12 PAR_D14 11 GND 10 PAR_D17*
9PAR_D19* 8PAR_D21** 7PAR_D23 6GND 5USB_VBUS 4GND 3GND 2NC 1VIN
J1
1A0 2A1 3A2 4VSS
8
VCC 7
WP 6
SCL 5
SDA
U6
24LC32
R3
DNP
R2
100kΩ
R1
100kΩ
TP5
R6 0Ω
R8
100kΩ
R18
100kΩ
L2
BEAD
R21
1.6Ω
+
C34
4.7µF
C21
0.1µF
+C22
10µF
R4 0Ω
R5 0Ω
R7 0Ω
R9 0Ω
R10 0Ω
R11 0Ω R13 0Ω
V_IO
SCL SDA
V_IO
SCLK SDO SDIN SYNC
V_IO
RESET
LDAC
DGND
+5V
V_IO
V_IO
SDIN/SDA
SCLK/A0
SYNC/SCL
SYNC
SCL
SCLK
SDIN
SDA
V_IO
12145-007
Figure 8. EVAL-AD5693RSDZ Schematic—SDP Connector

UG-675 EVAL-AD5693RSDZ User Guide
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12145-008
Figure 9. EVAL-AD5693RSDZ Component Placement Drawing
12145-009
Figure 10. EVAL-AD5693RSDZ Component Side Printed Circuit Board (PCB) Drawing
12145-010
Figure 11. EVAL-AD5693RSDZ Solder Side PCB Drawing