Analog Devices EVAL-AD5753SDZ User manual

EVAL-AD5753SDZ User Guide
UG-1492
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the AD5753 Single-Channel, 16-Bit Current and Voltage Output DAC with
Dynamic Power Control and HART Connectivity
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 22
FEATURES
Fully featured evaluation board for the AD5753
On-board, 2.5 V ADR4525 reference
SPI communication
EVALUATION KIT CONTENTS
EVAL-AD5753SDZ evaluation board
Analog Devices, Inc., EVAL-SDP-CS1Z (SDP-S) board
EQUIPMENT NEEDED
PC
EVAL-SDP-CS1Z (SDP-S) board
Bench top power supply and connector cables
DOCUMENTS NEEDED
AD5753 data sheet
EVAL-AD5753SDZ board user guide
ACE user manual
SOFTWARE NEEDED
ACE software
GENERAL DESCRIPTION
This user guide explains how to use the EVAL-AD5753SDZ to
evaluate the AD5753, a single-channel, 16-bit voltage and
current output, digital-to-analog converter (DAC) with on-chip
positive and negative dynamic power control (DPC) that
minimizes package power dissipation.
The EVAL-SDP-CS1Z system demonstration platform (SDP-S)
board is required when using the EVAL-AD5753SDZ board.
The EVAL-AD5753SDZ (see Figure 1) interfaces to the USB
port of the PC via the EVAL-SDP-CS1Z (SDP-S). Analysis
Control Evaluation (ACE) software is available to use with the
EVAL-AD5753SDZ, and allows the programming of the AD5753.
For full details on the AD5753, refer to the AD5753 data sheet.
Consult the AD5753 data sheet in conjunction with this user
guide when using the EVAL-AD5753SDZ. The configuration of
the various link options is explained in the Evaluation Board
Hardware section. The installation of the companion software is
discussed in the Software Quick Start Procedures section.

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Equipment Needed........................................................................... 1
Documents Needed.......................................................................... 1
Software Needed ............................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Evaluation Board Photograph......................................................... 3
Evaluation Board Hardware............................................................ 4
Power Supplies .............................................................................. 4
Serial Communication................................................................. 4
AD5753 Address Pins ................................................................... 4
Software Quick Start Procedures.................................................... 6
Installing the ACE Software and AD5753 Plugins .................. 6
Initial Setup ................................................................................... 6
AD5753 Block Diagram and Functions..........................................8
Configuring the Evaluation Board........................................... 10
DC-to-DC Converter Settings.................................................. 10
Configuring the DAC Output................................................... 11
Writing to the ADC Configuration Register .......................... 11
Updating Diagnostic Results .................................................... 11
Example Sequences .................................................................... 12
ACE Tool Views.............................................................................. 14
Macro Tool .................................................................................. 14
Register Debugger Tool ............................................................. 14
Events Tool .................................................................................. 14
Evaluation Board Schematics and Artwork................................ 15
Ordering Information.................................................................... 21
Bill of Materials........................................................................... 21
REVISION HISTORY
5/2019—Revision 0: Initial Version

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 3 of 22
EVALUATION BOARD PHOTOGRAPH
17332-001
Figure 1.

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 4 of 22
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5753SDZ requires power supply inputs for the
AVDD1, AVDD2, AVSS, and VLOGIC supplies. If there is only one
positive rail available, connect the AVDD2 pin to the AVDD1 pin
via the AVDD1 -AVDD2-SHRT link. Select the VLOGIC supply from
the 3.3V_SDP evaluation board pin or the VLDO pin through the
VLOGIC_SOURCE link. See Table 1 for the default link positions
and see Table 2 for more linking options.
The EVAL-AD5753SDZ operates with a power supply range of
−33 V on AVSS to +33 V on AVDD1, with a maximum voltage of
60 V between the two rails. AVDD2 requires a voltage between
5 V and 33 V. To bypass the positive dc-to-dc circuitry, connect
the VDPC+ pin directly to AVDD1 via the JP6 jumper. To bypass the
negative dc-to-dc circuitry, connect the VDPC− pin directly to the
AVSS pin via the JP5 jumper. The recommended supply voltages are
AVDD2 = +5 V, AVDD1 = +24 V, and AVSS = −24 V.
SERIAL COMMUNICATION
The EVAL-SDP-CS1Z (SDP-S) handles communication to the
EVAL-AD5753SDZ via the PC. The EVAL-SDP-CS1Z (SDP-S)
handles the serial port interface (SPI) communication, controls
the RESET pin and the LDAC pin, and monitors the FAULT pin
of the AD5753.
Remove the appropriate links on P2 to disconnect the EVAL-
AD5753SDZ from the EVAL-SDP-CS1Z (SDP-S) and drive the
digital signals from an external source. The S1 link and the JP11
link allow the user to tie RESET and LDAC to high or low levels.
AD5753 ADDRESS PINS
The AD0 address pin and the AD1 address pin are used in
conjunction with the address bits within the SPI frame to
determine which AD5753 device is being addressed by the system
controller. Configure the AD0 pin and the AD1 pin through the
JP12 link and the JP14 link.
Table 1. EVAL-AD5753SDZ Link Option Functions
Link Default Position Function
AVDD1-AVDD2-SHRT Not inserted Connects AVDD2 to AVDD1.
VLOGIC_SOURCE A Position A selects 3.3 V from the EVAL-SDP-CS1Z (SDP-S). Position B selects 3.3 V from the VLDO
pin of the AD5753.
JP1 A
Position A powers the ADR4525 reference (ADR-REF) from the VLDO pin. Position B powers the
ADR-REF from AVDD2. The maximum supply for the ADR4525 is 15 V.
JP2 Inserted Selects the ADR-REF pin as the input to the REFIN pin.
JP4 Not inserted Selects the REFOUT pin as the input to the REFIN pin.
JP5 Not inserted Shorts the VDPC− pin to the AVSS pin to bypass the negative dc-to-dc circuitry.
JP6 Not inserted Shorts the VDPC+ pin to the AVDD1 pin to bypass the positive dc-to-dc circuitry.
JP7 Inserted Shorts the ADC2 pin to the +VSENSE pin.
JP8 Inserted Connects the VIOUT pin to the +VSENSE pin.
JP9 Not inserted Connects the RETURN signal to the GND position on the EVAL-AD5753SDZ.
JP10 Inserted Connects the −VSENSE pin to the RETURN signal.
JP11 A
Position A connects the LDAC pin to the GND position. Position B connects the LDAC pin to the
VLOGIC pin.
JP12 A
Position A connects the AD0 pin to the GND position. Position B connects the AD0 pin to the
VLOGIC pin.
JP13 B
Position A connects the GPIO_0 pin to the GND position. Position B connects the GPIO_0 pin to
the VLOGIC pin.
JP14 A
Position A connects the AD1 pin to the GND position. Position B connects the AD1 pin to the
VLOGIC pin.
JP15 B
Position A connects the GPIO_2 pin to the GND position. Position B connects the GPIO_2 pin to
the VLOGIC pin.
JP16 B
Position A connects the GPIO_1 pin to the GND position. Position B connects the GPIO_1 pin to
the VLOGIC pin.
JP17 Not inserted Connects the AVSS pin to the GND position for the unipolar supply option (current output only).
P2 Inserted
Provides options to disconnect from the EVAL-SDP-CS1Z (SDP-S) and to drive digital signals
from an external source. See Table 2 for the specific link options.
S1 2-3
Position 2-1 (on position to the right of off) connects the RESET pin to the GND position.
Position 2-3 (on position to the left of off) connects the RESET pin to the VLOGIC pin.

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 5 of 22
Table 2. Link Options for P2
Pin Number Position Function
1, 2 Inserted Connects the FAULT signal from the EVAL-SDP-CS1Z (SDP-S) to the FAULT pin on the AD5753.
Not inserted
Disconnects the FAULT signal from the EVAL-SDP-CS1Z (SDP-S) to the FAULT pin on the AD5753.
3, 4 Inserted Connects the RESET signal from the EVAL-SDP-CS1Z (SDP-S) to the RESET pin on the AD5753.
Not inserted
Disconnects the RESET signal from the EVAL-SDP-CS1Z (SDP-S) to the RESET pin on the AD5753.
5, 6 Inserted Connects the LDAC signal from the EVAL-SDP-CS1Z (SDP-S) to the LDAC pin on the AD5753.
Not inserted
Disconnects the LDAC signal from the EVAL-SDP-CS1Z (SDP-S) to the LDAC pin on the AD5753.
7, 8 Inserted Connects the SCLK signal from the EVAL-SDP-CS1Z (SDP-S) to the SCLK pin on the AD5753.
Not inserted Disconnects the SCLK signal from the EVAL-SDP-CS1Z (SDP-S) to the SCLK pin on the AD5753.
9, 10 Inserted Connects the SDO signal from the EVAL-SDP-CS1Z (SDP-S) to the SDO pin on the AD5753.
Not inserted Disconnects the SDO signal from the EVAL-SDP-CS1Z (SDP-S) to the SDO pin on the AD5753.
11, 12 Inserted Connects the SDI signal from the EVAL-SDP-CS1Z (SDP-S) to the SDI pin on the AD5753.
Not inserted Disconnects the SDI signal from the EVAL-SDP-CS1Z (SDP-S) to the SDI pin on the AD5753.
13, 14 Inserted Connects the SYNC signal from the EVAL-SDP-CS1Z (SDP-S) to the SYNC pin on the AD5753.
Not inserted
Disconnects the SYNC signal from the EVAL-SDP-CS1Z (SDP-S) to the SYNC pin on the AD5753.

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 6 of 22
SOFTWARE QUICK START PROCEDURES
INSTALLING THE ACE SOFTWARE AND AD5753
PLUGINS
The EVAL-AD5753SDZ software uses the Analog Devices ACE
software. For instructions on how to install and use the ACE
software, go to www.analog.com/ACE.
When the installation is finished, open the ACE software to
open the EVAL-AD5753SDZ plugin (see Figure 2).
17332-002
Figure 2. EVAL-AD5753SDZ Plugin Window
INITIAL SETUP
To set up the EVAL-AD5753SDZ with the ACE software, take
the following steps:
1. Connect one end of the USB cable to the PC, and connect
the other end to the EVAL-SDP-CS1Z (SDP-S).
2. Connect the EVAL-SDP-CS1Z (SDP-S) to the EVAL-
AD5753SDZ. The PC recognizes the EVAL-AD5753SDZ.
3. Power up the EVAL-AD5753SDZ with the power supplies
described in the Power Supplies section.
4. If not opened already, open the ACE software. The EVAL-
AD5753SDZ appears in the Attached Hardware section of
the ACE software window.
5. The first time the EVAL-AD5753SDZ is set up, the plugin
may need to be installed. If the plugin appears as shown in
Figure 6, then go to Step 7. If the plugin appears as shown
in Figure 3, click on the button circled in red to open the
pop-up window shown in Figure 4, then click Yes.
6. A new window (see Figure 5) opens. Select the
Board.AD5753 plugin and click the Install Selected button.
The installed EVAL-AD5753SDZ plugin displays as shown
in Figure 6.
17332-003
Figure 3. EVAL-AD5753SDZ Plugin Not Installed
17332-004
Figure 4. Installing the Plugin Pop-Up Window
17332-005
Figure 5. Plugin Manager Window

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 7 of 22
17332-006
Figure 6. Attached Hardware Section with Connected EVAL-AD5753SDZ
7. Double-click EVAL-AD5753SDZ to open the AD5753 block
diagram (see Figure 7). The INITIAL CONFIGURATION
menu appears on the left side of the window. Several
register settings can be configured under this menu, and
are written to the device in the appropriate order. The
DIG_DIAG_STATUS, RESET_OCCURED, and
CAL_MEM_UNREFRESHEDLED indicators are
highlighted red. Write the initial configuration values to
clear the error flags. If the device is power cycled, or if the
USB cable is disconnected and reconnected while the ACE
software is open, contact with the EVAL-AD5753SDZ is
lost. If contact is lost, click the System tab, click the USB
symbol on the EVAL-AD5753SDZ, and then click Acquire
to restore communication with the EVAL-AD5753SDZ.
17332-007
Figure 7. AD5753 Block Diagram in ACE Software

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 8 of 22
AD5753 BLOCK DIAGRAM AND FUNCTIONS
The AD5753 ACE plugin appears similar to the block diagram
shown in the AD5753 data sheet. This similarity allows the user
to correlate the functions on the EVAL-AD5753SDZ to the
descriptions in the AD5753 data sheet.
A full description of each block and register setting is available
in the AD5753 data sheet. The full screen AD5753 block diagram is
shown in Figure 8 with all blocks labeled. Table 3 describes the
functionality of each block.
A B C D E
F
G
H
I
L1
L2
L3
L4
L5
QRS
U
V
L16
L6
L7
L8
L9
O
N
M
L10
L11
L12
K
L13
P
L14 L15
T
17332-008
L13
Figure 8. AD5753 Block Diagram with Labels

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 9 of 22
Table 3. AD5753 Block Diagram Label Functions (See Figure 8)
Label Function
A Apply Changes. Applies any changes made to the block diagram or to register values in the memory map to the device.
B Read All. Click to read back all of the registers of the device.
C Reset Chip. Click to reset the AD5753. Reset Chip has the same functionality as the software reset of the AD5753.
D Diff. Click to show the registers that are different from the data stored on the device. This function shows changes from the last
time the registers were read.
E Software Defaults. Click to load the software defaults of the device. These values are not written to the hardware. Click Apply
Changes (Label A) to write the software default values to the hardware.
F AD0 and AD1. These check boxes set the address of the device and must correspond to the JP12 link and the JP14 link on the
hardware. When either box is checked, this represents a high state. When either box is unchecked, this represents a low state.
G /RESET. Check the EVAL-SDP-CS1Z (SDP-S) to set the RESET pin high. Otherwise, the EVAL-SDP-CS1Z (SDP-S) pulls RESET low.
H /LDAC. Check the EVAL-SDP-CS1Z (SDP-S) to set the LDAC pin high. Otherwise, the EVAL-SDP-CS1Z (SDP-S) pulls LDAC low.
I /FAULT. Indicator LED lights up red if the FAULT pin is low. The ACE plugin monitors the FAULT pin.
K VI_OUT. Displays the calculated output at VI_OUT and shows if the output is in voltage, milliamps, or is high impedance (high-Z).
Lx Graphical user interface (GUI) access on several registers. Pop-up windows, dropdown menus, and hexadecimal textboxes are
available in the GUI to configure several registers of the AD5753. To write the changes to the device, click the Apply Changes
button (Label A). The functions within the GUI that control various registers (Label L1 through Label L15) are described in Table 4.
M Calibration Memory Refresh button. Initiates a write to the key register to perform a calibration memory refresh.
N SW LDAC button. Initiates a write to the key register to perform a software LDAC command.
O NOP Command button. Initiates a write to Address 0x00 for a no operation (NOP) command.
P Configure ADC button. Writes the data selected in the ADC Config menu (Label L15) to the ADC configuration register.
Q Two Stage Readback menu. Initiate two-stage readback through the two-stage readback select register. Click the Readback
button to initiate a write to the two-stage readback select register and issue a no operation command.
R DIGITAL DIAGNOSTIC RESULTS menu. Click the Update and Readback digital diagnostic result button to trigger a write of 1 to
clear operation and a readback from the digital diagnostic results register.
S ANALOG DIAGNOSTIC RESULTS menu. Click the Update and Readback analog diagnostic result button to trigger a write of 1 to
clear operation and a readback from the analog diagnostic results register.
T HART_EN box. Check this box to allow the HART_EN bit = 1 in the General-Purpose Configuration 1 register.
U Proceed to Memory Map button. Click this button to open the AD5753 memory map (see Figure 9).
V Example Sequences button. Click this button to open the example sequences window (see Figure 15).
Table 4. Register Controls Accessible via the GUI (See Label Lx in Table 3 and in Figure 8)
Label Function
L1 Diagnostic Configuration button. Click this button to open the associated pop-up menu.
L2 GP Config menu. Click this menu to open the associated pop-up menu.
L3 Key register menu. Click this menu to open the associated dropdown menu.
L4 Fault Pin Config button. Click this button to open the associated pop-up menu.
L5 WDT Config button. Click this button to open the associated pop-up menu.
L6 Frequency Monitor menu. This menu displays the value in the frequency monitor when read.
L7 Clear Code menu. Use the textbox in this menu to insert a clear code value in hexadecimal format.
L8 User Gain menu. Use the textbox in this menu to insert a user gain value in hexadecimal format.
L9 User Offset menu. Use the textbox in this menu to insert a user offset value in hexadecimal format.
L10 DAC Input Reg menu. Use the textbox in this menu to insert the DAC value in hexadecimal format.
L11 16 Bit DAC symbol. Click this button to open the associated pop-up menu.
L12 DAC Output Reg menu. This menu displays the hexadecimal value currently set in the DAC output register.
L13 DC-DC Converter. Click this button to open the dc-to-dc configuration pop-up menu.
L14 Status Register menu. This menu displays the contents of the status register.
L15 ADC Config menu. This menu contains a combination of dropdown menus and a textbox to enter the sequence data.
L16 GPIO Config/Data. Click this button to bring up a pop-up menu that allows control of the GPIOs.

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 10 of 22
17332-009
Figure 9. AD5753 Memory Map in ACE Software
CONFIGURING THE EVALUATION BOARD
An initial configuration wizard is available when opening the
AD5753 plugin. The initial configuration wizard allows
configuration of the AD5753 and provides configuration of the
clock output in the General-Purpose Configuration Register 1,
the dc-to-dc settings, the DAC configuration, and the DAC input
register. Click the Apply button to initiate the configured
settings in the order of the recommended power-up sequence
described in the AD5753 data sheet.
DC-TO-DC CONVERTER SETTINGS
If the VDPC+ pin is not tied directly to the AVDD1 pin, enable the
dc-to-dc converter for correct operation. Complete this step
before configuring the DAC output. The DC-DC Configuration
pop-up menu, shown in Figure 10, contains the dc-to-dc settings
required to configure the AD5753 output correctly. After the
proper settings are selected, click the Close button and then click
Apply Changes.
17332-010
Figure 10. DC-DC Configuration Pop-Up Menu

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 11 of 22
CONFIGURING THE DAC OUTPUT
To configure the DAC output, use the pop-up menu for the DAC
configuration register (see Figure 11), available in the GUI. Click
the 16 Bit DAC (Label L11, Figure 8) symbol in the GUI to display
the DAC configuration register. Select the appropriate settings and
then click Apply Changes (Label A, Figure 8). It is recommended
to disable the output until the correct value in the DAC input
register is written to the device.
To change the DAC voltage or current output level, write the
appropriate hexadecimal code to the DAC input register and
then click Apply Changes. Issue a software LDAC command
using the SW LDAC (Label N, Figure 8) button, or pull the
LDAC pin low to update the DAC output register with the
values in the DAC input register. Select the OUT_EN checkbox
to enable the DAC output and then click Apply Changes. The
programmed voltage or current is reflected at the VIOUT pin.
17332-011
Figure 11. AD5753 DAC Config Register Pop-Up Menu
WRITING TO THE ADC CONFIGURATION REGISTER
The procedure to set up and configure the ADC sequencer is
discussed in the AD5753 data sheet. Writing to the ADC
configuration register is simplified because of the multiple
configuration modes.
Dropdown menus and a hexadecimal textbox are available within
the GUI (see Figure 12) to access the ADC configuration register.
Click the Configure ADC button instead of the Apply Changes
button to write to the ADC configuration register.
17332-012
Figure 12. AD5753 ADC Configuration Register
UPDATING DIAGNOSTIC RESULTS
The AD5753 has a digital diagnostic results register and an
analog diagnostic results register, both of which contain error
flags for the on-chip digital and analog diagnostic features.
Write 1 to the respective error flags to update the error flag status.
The Update and Readback button shown in Figure 13 is
available on the ACE GUI to update the digital and analog
diagnostic results registers. Click this button to initiate a write
of 1 (by selecting the box) to the selected error flag, and then
read back the updated diagnostic result. Figure 13 shows the
digital diagnostic results register. Figure 14 shows the analog
diagnostic results register.
17332-013
Figure 13. AD5753 Digital Diagnostic Results Register

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 12 of 22
17332-014
Figure 14. AD5753 Analog Diagnostic Results Register
EXAMPLE SEQUENCES
There are several example sequences available. Click the Example
Sequences button (Label V, Figure 8) and the window shown in
Figure 15 appears. To enable any of the sequences, click on the
relevant sequence button, as shown in Figure 16. The sequence
runs immediately and the output changes accordingly. To return
to the main window, click the Back to AD5753 button.
17332-015
Figure 15. Example Sequences Window

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 13 of 22
17332-016
Figure 16. Selecting an Example Sequence

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 14 of 22
ACE TOOL VIEWS
The ACE software provides additional functionality to the main
view described in this user guide. Open these views from the view
menu item on the application toolbar. The ACE software features a
macro tool, a register debugger tool, and an events tool.
MACRO TOOL
The macro tool records and saves commands as an ACE macro
file. This feature is useful when sharing macros with other users
to perform the same task multiple times. The user can import
and run an ACE macro file.
REGISTER DEBUGGER TOOL
The register debugger tool performs raw writes to, and reads
from, the device. The register debugger only affects the hardware
and does not write to the memory map of the ACE software.
EVENTS TOOL
The events tool view contains a list of errors, warnings, and
information messages generated within the application software.

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 15 of 22
EVALUATION BOARD SCHEMATICS AND ARTWORK
TERMINAL BLOCK DECOUPLING CAPACITORS
SCHEMATIC PAGE - DUT & SUPPLY
OPTION TO SHORT AVSS TO GND => UNIPOLAR SUPPLY
GROUND PLANE APPROACH = SHORT AGND, DGND, PGND1 AND PGND2 TO PRODUCE "GND"
AD5753 REFIN OPTIONS
ZENER CLAMPS VIN TO 15V IF A LARGER VOLTAGE IS APPLIED
VLOGIC SOURCE OPTIONS
VIN = 3V - 15V
REFGND "ISLAND" PINNED TO OTHER GND PLAIN AT 1 POINT
0.1µF RED
1µF
REFGND REFGND
ADR-REF
REFGND
RED
BLK
REFGND
GND
GND
GND
GND
0Ω
BLK
BLK
BLKBLK
GND
BLK BLK BLK
BLK
GND
1727023
GND
GND
4.7µF
RED
1727010
BLK
BLK
RED
RED
GND
4.7µF
4.7µF
1µF 0.1µF
RED
RED
REFGND
ADR4525BRZ
0.1µF
0.1µF
D1
JP17
JP1
R2
VLOGIC_SOURCE
ADR-REF
REFOUT
REFIN
JP4
JP2
C11
C9
C8
TP10TP8TP6TP4 TP12
TP9TP7TP5TP3 TP11
GND
VLOGIC
AVDD1-AVDD2-SHRT
AVDD2_
C4 C7
AVSS
AVDD1
C5
C6C3
C2
AVDD2
AVDD1/AVSS
U1
AV
SS
AV
DD2
VLDO
ADR-REF
AVSS
GND
AVDD1
AV
DD2
GND
AVDD2
VLDO
3.3V_SDP
AV
DD2
AV
DD1
VLOGIC
ADR-REF
REFIN
REFOUT
A
C
12
3
2
1
321
1
1
1
21
12
11111
11111
1
1
2
1
1
1
1
6
2
8
7 5 3 1 4
NIC NIC NIC NIC
VIN
GND
DNC
VOUT
BA
BA
17332-017
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
Figure 17. AD5753 Supplies and Reference Options

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 16 of 22
GPIO CIRCUITRY
VF = 2.2V
SIGNALS FROM EXTERNAL SOURCE E.G. PXI
OPTION TO DISCONNECT FROM SDP & DRIVE DIGITAL
OPTION TO TIE /LDAC AND /RESET PERMANENTLY HIGH/LOW
SDP DEBUG LED SCHEMATIC PAGE - SDP/DIGITAL INTERFACE
IF = 20MA
CENTRE-OFF TOGGLE SWITCH FOR /RESET
NOTE - THE SDP SIGNAL SERIES 0 OHM RESISTORS SHOULD BE INCREASED TO 1KOHM IF THERE IS A RISK THAT THE USER COULD OVER-DRIVE THESE INPUTS WITHOUT REMOVING THE NECESSARY JUMPERS AT P2.
FLEXIBILITY TO MODIFY EEPROM ADDRESS
HARDWARE TIE AD0 AND AD1 HIGH/LOW
FX8-120S-SV(21)
GND
GRNGRNGRNGRNGRNGRNGRNGRNGRNGRN
24LC32A/SN
100kΩ
GND
DNI100K
DNI
TSW-110-08-G-D
GND
GND
GND
GND
1kΩ
0Ω 0Ω
GND
GND
GND
0Ω
GND
GND GND
100kΩ
GND
GND
GND GND
GND
1kΩ
DS3
DS5
DS2
DS4
S1
R14
R28 R29
JP15
R31 R32
JP16
R30
JP13
JP11
/SYNC
SDI
SDO
SCLK
/LDAC
/RESET
/FAULT
GPIO0
GPIO1
R15 R16 R17 R21
R20 R19
R25 R24 R23 R22
P2
GPIO2
R27 R26
R18
JP14
JP12
U3
P1
3.3V_SDP
VLOGIC
/LDAC
GPIO0
3.3V_SDP
GPIO_2_SDP
/LDAC_SDP
GPIO_0_SDP
/SYNC
SDI
SDO
SCLK
/RESET
/RESET_SDP
/LDAC
/SYNC_SDP
SDI_SDP
SDO_SDP
SCLK_SDP
/LDAC_SDP
GPIO2
GPIO1
/FAULT
AD1
/SYNC_SDP SDI_SDP SDO_SDP SCLK_SDP
GPIO_1_SDP /FAULT_SDP /RESET_SDP
/RESET
VLOGIC
ADO
VLOGIC
VLOGIC
VLOGIC
3.3V_SDP
VLOGIC
VLOGIC
GPIO2
GPIO_2_SDP
GPIO2
GPIO_1_SDP GPIO_0_SDP
GPIO1
/FAULT_SDP
GPIO0
A
C
A
C
A
C
A
C
3 1
2
3
2
13
2
1
3
2
1
3
2
1
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
1111111111
3
2
1
3
2
1
7
4 8
5
6 3 2 1
116 85 65
1 5
6259 7249 7348 87 89
30 29 92
90
32
88
31
91
38 37 39
84 83
34 33
82 64
35 41 80 42 79 57 60
10021 99
26 95 27
7 114 8 113 9 112
10 111
110
12 13 108 14 107 15 106 16 105 18 103 19 102 20 101 22
94
24 97 25 96
120 119 70 68 67 6655
54 53 51 50
2
7447 7645 7744 7843 118 117 115 109 104 98 93 86 81 75 69 6358
52 46 40 36 28 23 17 11
6 4 3
56
71 61
BI
A
A
B
B
SPI_SEL_A_N
CLKOUT
NC NC
GND GND
VIO
GND
PAR_D22 PAR_D20 PAR_D18 PAR_D16 PAR_D15
GND
PAR_D12 PAR_D10
PAR_D8 PAR_D6
GND
PAR_D4 PAR_D2 PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2 PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0 SPORT_RFS
SPORT_TFS SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0 GPIO1 GPIO3 GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC NC NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX GND RESET_OUT_N EEPROM_A0 NC NC NC GND NC NC TMR_C TMR_A GPIO6 GND GPIO4 GPIO2 GPIO0 SCL_1 SDA_1 GND SPI_SEL1/SPI_SS_N SPI_SEL_C_N SPI_SEL_B_N GND SERIAL_INT SPI_D3 SPI_D2 SPORT_DT1 SPORT_DR1 SPORT_TDV1 SPORT_TDV0 GND PAR_FS1 PAR_FS3 PAR_A1 PAR_A3 GND PAR_CS_N PAR_RD_N PAR_D1 PAR_D3 PAR_D5 GND PAR_D7 PAR_D9 PAR_D11 PAR_D13 PAR_D14 GND PAR_D17
PAR_D19 PAR_D21 PAR_D23 GND USB_VBUS GND GND NC VIN
OUT
IN
VCC
WP SCL
SDA
VSS
A2 A1 A0
ABAB
OUT
IN BI
OUT
OUT OUT OUT
IN BI
BI
OUT
IN
IN
1kΩ
AB
BI
IN
BI
IN
IN
1kΩ
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
0Ω 0Ω 0Ω
0Ω 0Ω 0Ω 0Ω
AB
IN
OUT
IN
OUT
17332-018
Figure 18. EVAL-SDP-CS1Z (SDP-S) Board Connections, Address Pins, LDAC Pins, and RESET Pins

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 17 of 22
C_DCDC - SURFACE MT & THROUGH-HOLE OPTIONS
OPTION TO DRIVE VDPC- WITH AVSS (BYPASS NEGATIVE DC-DC)
OPTIONAL RC FILTER ON REFOUT
OPTION TO DRIVE VDPC+ WITH AVDD1 (BYPASS POSITIVE DC-DC)
VF = 1.8V
IF = 2MA
LPS4018-473ML
AVDD2
GND
GND
GND
0.1UF
13.7K
0.1UF
0.1UF
4.7UF
47UH
REFGND
0
RED
1K
GRN
2.2UF
RED
0.1UF
GND
GND
4.7UF
GND
47UH
GND
DNI 0.1UF
RED
DNI
2.2UF
2.2UF DNI
DNI
GND
GND GND
REFGND
AD5753BCPZ
C23
DS1
R5
C13
CLKOUT
C19
VLDO
C10
R6
L1
L2
C22
C15
U2
R8
JP5
C14 C17 C20
VDPC-
JP6
VDPC+
C21
C16 C18
AVDD2
AVDD1
/RESET
SCLK
SW-
SW+
GPIO1
GPIO2
ADC1
ADC2
GPIO0
AVDD1
REFOUT
VLDO
VDPC-
CLKOUT
VLOGIC
/FAULT
SW+
VLOGIC
SDO
/LDAC
/SYNC
AD1
ADO
AVSS
SW-
VDPC-
-VSENSE
+VSENSE
VI_OUT
VDPC+
C_HART
SDI
CCOMP
VDPC-
REFIN
A
C
1
1
13
37
32
39
24 30
1
14
23
22
8
7
16
12
11
10
6
31 40 38 33 28
4
20
19
18
17 27
PAD
15
21
9
35
29 3
2
5
25
26 34
36
21
1
21
1
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
OUT
PAD PGND1
VDPC+
ADC2
VIOUT
+VSENSE
CCOMP
-VSENSE
NIC
VDPC- PGND2
SW-
AVSS NIC
FAULT_N
AD0
AD1
SYNC_N
SDI
SCLK CLKOUT
LDAC_N
GPIO_2
GPIO_1
GPIO_0
RESET_N
DGND
SDO
VLOGIC
VLDO
REFOUT
REFIN
CHART
RB
RA
REFGND AGND ADC1
AVDD2 AVDD1
SW+
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
17332-119
Figure 19. AD5753 Device

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 18 of 22
PLACEHOLDER TO EXPERIMENT WITH SETTLING TIME
THROUGH-HOLE LOAD RESISOR OPTION IN GOLD PINS
THROUGH-HOLE COMPONENTS USED FOR SERIES RESISTORS
–VSENSE
C_HART
RETURN
VI_OUT
+VSENSE
GRN
1.0µF
2.0kΩ
GND
GRN
GRN
GRN
1kΩ
1kΩ
DNI
GND GND
1727049
20Ω
GND
10Ω
1µF
GRN
1kΩ
GRN
GRN
GRN
0.15µF
GND
0.047µF
ADC1
ADC2
R1
C1
R12
R3 JP9
JP7
P6
P4
P7
P5
C24
P3
C_HART
C25
C26
RTN_TERMINAL
VI_OUT_TERMINAL
JP10
JP8
–VSENSE
R13
+VSENSE
VI_OUT
R11
R10
ADC1
ADC2
VI_OUT
+VSENSE
VI_OUT_TERMINAL
C_HART
–
VSENS
E
1
1
21
1
1
12
11
11
5
4
3
2
1
1
1
1
2
2
1
1
1
IN
IN
IN
OUT
OUT
OUT
17332-019
Figure 20. AD5753 Output Stage

EVAL-AD5753SDZ User Guide UG-1492
Rev. 0 | Page 19 of 22
17332-020
Figure 21. Silkscreen
17332-021
Figure 22. Layer 1

UG-1492 EVAL-AD5753SDZ User Guide
Rev. 0 | Page 20 of 22
17332-022
Figure 23. Ground and Power Plane, Layer 2, and Layer 3
17332-023
Figure 24. Layer 4 (Secondary)