Analog Devices ADM1063 User manual

Multisupply Supervisor/Sequencer
with ADC and Temperature Monitoring
ADM1063
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision of
supplies up to
14.4 V on VH
6 V on VP1 to VP4
5 dual-function inputs, VX1 to VX5
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers, PDO1 to PDO10
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output, 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
1 internal and 2 external temperature sensors
Reference input, REFIN, has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved
ADC performance
Device powered by the highest of VP1 to VP4, VH for
improved redundancy
User EEPROM: 256 bytes
Industry-standard, 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
FUNCTIONAL BLOCK DIAGRAM
04632-001
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
VDD
ARBITRATOR
GNDVCCP
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
A
GND
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
SDA SCL A1 A0
SMBus
INTERFACE
REFOUTREFIN REFGND
VREF
12-BIT
SAR ADC
MUX
EEPROM
CLOSED-LOOP
MARGINING SYSTEM
ADM1063
D2ND1N D2PD1P
TEMP
SENSOR INTERNAL DIODE
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1063 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1063 integrates a 12-bit ADC and six 8-bit
voltage output DACs. These circuits can be used to implement a
closed-loop margining system, which enables supply adjustment
by altering either the feedback node or reference of a dc-to-dc
converter using the DAC outputs.
(continued on Page 3)

ADM1063
Rev. 0 | Page 2 of 36
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
Pin Configurations and Function Descriptions ........................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics ............................................. 9
Powering the ADM1063 ................................................................ 12
Inputs................................................................................................ 13
Supply Supervision..................................................................... 13
Programming the Supply Fault Detectors............................... 13
Input Comparator Hysteresis.................................................... 14
Input Glitch Filtering ................................................................. 14
Supply Supervision with VXn Inputs ...................................... 14
VXn Pins as Digital Inputs........................................................ 15
Outputs ............................................................................................ 16
Supply Sequencing Through Configurable
Output Drivers............................................................................ 16
Sequencing Engine ......................................................................... 17
Overview...................................................................................... 17
Warnings...................................................................................... 17
SMBus Jump (Unconditional Jump)........................................ 17
Sequencing Engine Application Example ............................... 18
Sequence Detector...................................................................... 19
Monitoring Fault Detector ........................................................ 19
Timeout Detector ....................................................................... 19
Fault Reporting........................................................................... 19
Voltage Readback............................................................................ 20
Supply Supervision with the ADC ........................................... 20
Supply Margining ........................................................................... 21
Overview ..................................................................................... 21
Open-Loop Margining .............................................................. 21
Closed-Loop Supply Margining ............................................... 21
Writing to the DACs .................................................................. 22
Choosing the Size of the Attenuation Resistor....................... 22
DAC Limiting and Other Safety Features............................... 22
Temperature Measurement System.............................................. 23
Remote Temperature Measurement ........................................ 23
Applications Diagram .................................................................... 25
Communicating with the ADM1063........................................... 26
Configuration Download at Power-Up................................... 26
Updating the Configuration ..................................................... 26
Updating the Sequencing Engine............................................. 27
Internal Registers........................................................................ 27
EEPROM ..................................................................................... 27
Serial Bus Interface..................................................................... 27
SMBus Protocols for RAM and EEPROM.............................. 29
Write Operations........................................................................ 29
Read Operations......................................................................... 31
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 34
REVISION HISTORY
4/05—Revision 0: Initial Version

ADM1063
Rev. 0 | Page 3 of 36
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining loop can be used for
in-circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or it can be used dynamically to accurately control the output
voltage of a dc-to-dc converter.
The device also provides up to 10 programmable inputs for
monitoring under, over, or out-of-window faults on up to 10
supplies. In addition, 10 programmable outputs can be used as
logic enables. Six of these programmable outputs can provide
up to a 12 V output for driving the gate of an N-channel FET,
which can be placed in the path of a supply.
Temperature measurement is possible with the ADM1063. The
device contains one internal temperature sensor and two pairs
of differential inputs for remote thermal diodes. These are
measured by the 12-bit ADC.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
04632-002
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
DEVICE
CONTROLLER
OSC
EEPROM
SDA SCL A1 A0
SMBus
INTERFACE
REFOUTREFIN REFGND
VREF
12-BIT
SAR ADC
ADM1063
CONFIGURABLE
O/P DRIVER
(HV) PDO1
PDO2
PDOGND
PDO3
VCCPGND
PDO4
PDO5
PDO8
PDO9
CONFIGURABLE
O/P DRIVER
(HV) PDO6
CONFIGURABLE
O/P DRIVER
(LV) PDO7
CONFIGURABLE
O/P DRIVER
(LV) PDO10
SEQUENCING
ENGINE
VX2
VX3
VX4
VP2
VP3
VP4
VH
VP1
VX1
AGND
VX5
VDDCAP VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
D2ND1N D2PD1P
TEMP
SENSOR INTERNAL DIODE
Figure 2. Detailed Block Diagram

ADM1063
Rev. 0 | Page 4 of 36
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPn 3.0 V Minimum supply required on one of VH, VPn.
VP 6.0 V Maximum VDDCAP = 5.1 V, typical.
VH 14.4 V VDDCAP = 4.75 V.
VDDCAP 2.7 4.75 5.4 V Regulated LDO output.
CVDDCAP 10 µF Minimum recommended decoupling capacitance.
POWER SUPPLY
Supply Current, IVH, IVPn 4.2 6 mA
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off,
ADC off.
Additional Currents
All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 µA
each, PDO7 to PDO10 off.
Current Available from VDDCAP 2 mA Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP.
DACs Supply Current 2.2 mA Six DACs on with 100 µA maximum load on each.
ADC Supply Current 1 mA Running round-robin loop.
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V.
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error ±0.05 % Midrange and high range.
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPn Pins
Input Attenuator Error ±0.05 % Low range and midrange.
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error.
VXn Pins
Input Impedance 1 MΩ
Detection Range
Ultralow Range 0.573 1.375 V No input attenuation error.
Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator offset
error + input attenuation error.
Threshold Resolution 8 Bits
Digital Glitch Filter 0 µs Minimum programmable filter length.
100 µs Maximum programmable filter length.
ANALOG-TO-DIGITAL CONVERTER
Signal Range 0 VREFIN V The ADC can convert signals presented to the VH,
VPn, and VXn pins. VPn and VH input signals are
attenuated depending on selected range. A signal
at the pin corresponding to the selected range is
from 0.573 V to 1.375 V at the ADC input.
Input Reference Voltage on REFIN Pin, VREFIN 2.048 V
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, VREFIN = 2.048 V.
Gain Error ±0.05 % VREFIN = 2.048 V.

ADM1063
Rev. 0 | Page 5 of 36
Parameter Min Typ Max Unit Test Conditions/Comments
Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, 16x averaging enabled
Offset Error ±2 LSB VREFIN = 2.048 V
Input Noise 0.25 LSBrms Direct input (no attenuator)
TEMPERATURE SENSOR2
Local Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Local Sensor Supply Voltage Coefficient −1.7 °C/V
Remote Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Remote Sensor Supply Voltage Coefficient −3 °C
Remote Sensor Current Source 200 µA High level
12 µA Low level
Temperature for Code 0x800 0 °C VDDCAP = 4.75 V
Temperature for Code 0xC00 128 °C VDDCAP = 4.75 V
Temperature Resolution per Code 0.125 °C
BUFFERED VOLTAGE OUTPUT DACs
Resolution 8 Bits
Code 0x80 Output Voltage Six DACs are individually selectable for centering
on one of four output voltage ranges
Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V
Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Load Regulation −4 mV Sourcing current, IREFOUTMAX = −200 µA
2 mV Sinking current, IREFOUTMAX = 100 µA
Maximum Load Capacitance 50 pF
Settling Time to 50 pF Load 2 µs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC
40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, IDACnMAX = −100 µA
0.25 mV Sinking current, IDACnMAX = 100 µA
Minimum Load Capacitance 1 µF Capacitor required for decoupling, stability
Load Regulation 2 mV Per 100 µA
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge-Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0
10.5 12 13.5 V IOH = 1 µA
IOUTAVG 20 µA 2 V < VOH < 7 V

ADM1063
Rev. 0 | Page 6 of 36
Parameter Min Typ Max Unit Test Conditions/Comments
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPn = 6.0 V, IOH = 0 mA
V
PU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
VOL 0 0.50 V IOL = 20 mA
IOL320 mA Maximum sink current per PDO pin
ISINK360 mA Maximum total sink for all PDO pins
RPULL-UP 20 kΩ Internal pull-up
ISOURCE (VPn)32 mA
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
Three-State Output Leakage Current 10 µA VPDO = 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 µA VIN = 5.5 V
Input Low Current, IIL 1 µA VIN = 0
Input Capacitance 5 pF
Programmable Pull-Down Current,
IPULL-DOWN
20 µA
VDDCAP = 4.75, TA= 25°C if known logic state is
required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL30.4 V IOUT = −3.0 mA
SERIAL BUS TIMING
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 4.7 µs
Start Setup Time, tSU;STA 4.7 µs
Start Hold Time, tHD;STA 4 µs
SCL Low Time, tLOW 4.7 µs
SCL High Time, tHIGH 4 µs
SCL, SDA Rise Time, tr1000 µs
SCL, SDA Fall Time, tf300 µs
Data Setup Time, tSU;DAT 250 ns
Data Hold Time, tHD;DAT 5 ns
Input Low Current, IIL 1 µA VIN = 0
SEQUENCING ENGINE TIMING
State Change Time 10 µs
1At least one of the VH, VP1 to VP4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3Specification is not production tested, but is supported by characterization data at initial product release.

ADM1063
Rev. 0 | Page 7 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04632-003
ADM1063
TOP VIEW
(Not to Scale)
GND
40
VDDCAP
39
D1P
38
D1N
37
D2P
36
D2N
35
A1
34
A0
33
VCCP
32
PDOGND
31
AGND
11
REFGND
12
REFIN
13
REFOUT
14
NC
15
NC
16
SCL
17
SDA
18
NC
19
NC
20
V
X1 1
V
X2 2
V
X3 3
V
X4 4
V
X5 5
V
P1 6
V
P2 7
V
P3 8
V
P4 9
VH 10
PDO130
PDO2
29
PDO3
28
PDO427
PDO526
PDO625
PDO7
24
PDO8
23
PDO922
PDO1021
PIN 1
INDICATOR
Figure 3. LFCSP Pin Configuration
04632-004
NC = NO CONNECT
NC
48
GND
47
VDDCAP
46
D1P
45
D1N
44
D2P
43
D2N
42
A1
41
A0
40
VCCP
39
PDOGND
38
NC
37
NC
13
AGND
14
REFGND
15
REFIN
16
REFOUT
17
NC
18
NC
19
SCL
20
SDA
21
NC
22
NC
23
NC
24
NC 1
V
X1 2
V
X2 3
V
X3 4
V
X4
5
V
X5
6
V
P1
7
V
P2
8
V
P3
9
V
P4
10
VH
11
NC 12
NC 36
PDO1 35
PDO2 34
PDO3 33
PDO4
32
PDO5
31
PDO6
30
PDO7
29
PDO8
28
PDO9
27
PDO10
26
NC 25
ADM1063
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
LFCSP TQFP Mnemonic Description
15, 16,
19, 20
1, 12, 13,
18, 19, 22
to 25, 36,
37, 48
NC No Connection.
1 to 5 2 to 6 VX1 to VX5 High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10 VP1 to VP4 Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply fault
detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
10 11 VH High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply fault
detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
11 14 AGND Ground Return for Input Attenuators.
12 15 REFGND Ground Return for On-Chip Reference Circuits.
13 16 REFIN Reference Input for ADC. Nominally, 2.048 V.
14 17 REFOUT Reference Output, 2.048 V.
17 20 SCL SMBus Clock Pin. Open-drain output requires external resistive pull-up.
18 21 SDA SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Output Drivers.
31 38 PDOGND Ground Return for Output Drivers.
32 39 VCCP Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and GND.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 D2N External Temperature Sensor 1 Cathode Connection.
36 43 D2P External Temperature Sensor 1 Anode Connection.
37 44 D1N External Temperature Sensor 1 Cathode Connection.
38 45 D1P External Temperature Sensor 1 Anode Connection.
39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest voltage on the VP1 to VP4 and VH pins to a
typical voltage of 4.75 V.
40 47 GND Ground Supply.

ADM1063
Rev. 0 | Page 8 of 36
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VP Pins 7 V
Voltage on VX Pins −0.3 V to +6.5 V
Voltage on DxN, DxP, and REFIN Pins −0.3 V to +5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
40-lead LFCSP package: θJA = 25°C/W.
48-lead TQFP package: θJA = 14.8°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADM1063
Rev. 0 | Page 9 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
6
0
1
2
3
4
5
0654321
04632-050
V
VP1
(V)
V
VDDCAP
(V)
Figure 5. VVDDCAP vs. VVP1
6
0
1
2
3
4
5
0161412108642
04632-051
V
VH
(V)
V
VDDCAP
(V)
Figure 6. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00123456
04632-052
V
VP1
(V)
I
VP1
(mA)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
180
160
140
120
100
80
60
40
20
00123456
04632-053
V
VP1
(V)
I
VP1
(µA)
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00161412108642
04632-054
V
VH
(V)
I
VH
(mA)
Figure 9. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
00654321
04632-055
V
VH
(V)
I
VH
(µA)
Figure 10. IVH vs. VVH (VH Not as Supply)

ADM1063
Rev. 0 | Page 10 of 36
14
12
10
8
6
4
2
00 15.012.510.07.55.02.5
04632-056
I
LOAD
( µ A)
CHARGE-PUMPED V
PDO1
(V)
Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00654321
04632-057
I
LOAD
(mA)
V
PDO1
(V)
VP1 = 5V
VP1 = 3V
Figure 12. VPDO1 (Strong Pull-Up to VP) vs. ILOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00605040302010
04632-058
I
LOAD
( µ A)
V
PDO1
(V)
VP1 = 5V
VP1 = 3V
Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
40001000 2000 30000
04632-066
CODE
DNL (LSB)
Figure 14. DNL for ADC
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 4000300020001000
04632-063
CODE
INL (LSB)
Figure 15. INL for ADC
12000
10000
8000
6000
4000
2000
0204920482047
04632-064
CODE
HITS PER CODE
81
9894
25
Figure 16. ADC Noise, Midcode Input, 10,000 Reads

ADM1063
Rev. 0 | Page 11 of 36
04632-059
CH1 200mV M1.00µs CH1 756mV
1
DAC
BUFFER
OUTPUT PROBE
POINT
47pF
20kΩ
Figure 17. Transient Response of DAC Code Change into Typical Load
04632-060
CH1 200mV M1.00µs CH1 944mV
1
DAC
BUFFER
OUTPUT 1V
PROBE
POINT
100kΩ
Figure 18. Transient Response of DAC to Turn-On from HI-Z State
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
–40 –20 0 20 40 60 10080
04632-065
TEMPERATURE (°C)
DAC OUTPUT
VP1 = 3.0V
VP1 = 4.75V
Figure 19. DAC Output vs. Temperature
2.058
2.038
2.043
2.048
2.053
–40 –20 0 20 40 60 10080
04632-061
TEMPERATURE (°C)
REFOUT (V)
VP1 = 3.0V
VP1 = 4.75V
Figure 20. REFOUT vs. Temperature

ADM1063
Rev. 0 | Page 12 of 36
POWERING THE ADM1063
The ADM1063 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy,
because the device is not dependent on any particular voltage
rail to keep it operational. The same pins are used for supply
fault detection (discussed in the Programming the Supply Fault
Detectors section). A VDD arbitrator on the device chooses
which supply to use. The arbitrator can be considered an OR’ing
of five LDOs together. A supply comparator determines which
of the inputs is highest and selects it to provide the on-chip
supply. There is minimal switching loss with this architecture
(~0.2 V), resulting in the ability to power the ADM1063 from a
supply as low as 3.0 V. Note that the supply on the VXn pins
cannot be used to power the device.
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 21. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPn or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDDCAP can then
act as a reservoir to keep the device active until the next highest
supply takes over the powering of the device. For this
reservoir/decoupling function, 10 µF is recommended.
Note that when two or more supplies are within 100 mV of each
other, the supply that takes control of VDD first keeps control.
For example, if VP1 is connected to a 3.3 V supply, then VDD
powers up to approximately 3.1 V through VP1. If VP2 is then
connected to another 3.3 V supply, VP1 still powers the device,
unless VP2 goes 100 mV higher than VP1.
SUPPLY
COMPARATOR
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
VH
VP4
VP3
VP2
VP1 VDDCAP
INTERNAL
DEVICE
SUPPLY
0
4632-022
Figure 21. VDD Arbitrator Operation

ADM1063
Rev. 0 | Page 13 of 36
INPUTS
SUPPLY SUPERVISION
The ADM1063 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VP1 to VP4 by default. The other five inputs
are labeled VX1 to VX5 and have dual functionality. They can
be used as either SFDs with similar functionality to VH and
VP1 to VP4, or CMOS-/TTL-compatible logic inputs to the
devices. Therefore, the ADM1063 can have up to 10 analog
inputs, a minimum of five analog inputs and five digital inputs,
or a combination. If an input is used as an analog input, it
cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no digital inputs available.
Table 5 shows the details of each of the inputs.
04632-023
+
–
+
–
UV
COMPARATOR
VREF
FAULT TYPE
SELECT
OV
COMPARATOR
FAULT
OUTPUT
GLITCH
FILTER
VPn
MID
LOW
RANG
E
SELECT
ULTRA
LOW
Figure 22. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1063 can have up to 10 SFDs on its 10 input
channels. These highly programmable reset generators enable
the supervision of up to 10 supply voltages. The supplies can be
as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
drops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value), or an out-of-
window fault (an undervoltage or overvoltage). The thresholds
can be programmed to an 8-bit resolution in registers provided
in the ADM1063. This translates to a voltage resolution that is
dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 4.8 V)/255 = 37.6 mV
Table 4 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 4. Voltage Range Limits
Voltage Range (V) VB(V) VR(V)
0.573 to 1.375 0.573 0.802
1.25 to 3.00 1.25 1.75
2.5 to 6.0 2.5 3.5
4.8 to 14.4 4.8 9.6
The threshold value required is given by
VT= (VR× N)/255 + VB
where:
VTis the desired threshold voltage (UV or OV).
VRis the voltage range.
Nis the decimal value of the 8-bit code.
VBis the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N= 255 × (VT− VB)/VR
For example, if the user wants to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed in the AN-698 application note) is given by
N= 255 × (5 − 2.5)/3.5
Therefore, N= 182 (1011 0110 or 0xB6).
Table 5. Input Functions, Thresholds, and Ranges
Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (µs)
VH High V analog input 2.5 to 6.0 425 mV 13.7 0 to 100
4.8 to 14.4 1.16 V 37.6 0 to 100
VPn Positive analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXn High Z analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital input 0 to 5 N/A N/A 0 to 100

ADM1063
Rev. 0 | Page 14 of 36
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 22 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these compara-
tors have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 5.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the UV threshold that the input must rise to before a UV fault is
deasserted. Similarly, the user can program the amount below
the OV threshold that an input must fall to before an OV fault
is deasserted.
The hysteresis figure is given by
VHYST = VR× NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges are listed in Table 5.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions, such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 µs.
For example, when the glitch filter timeout is 100 µs, any pulse
appearing on the input of the glitch filter block that is less than
100 µs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 µs
does appear on the output of the glitch filter block. The output
is delayed with respect to the input by 100 µs. The filtering
process is shown in Figure 23.
04632-024
T
0TGF T0TGF
T
0TGF T0TGF
INPUT
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT INPUT PULSE LONGER THAN GLITCH FILTER TIMEOUT
OUTPUT
PROGRAMMED
TIMEOUT PROGRAMMED TIMEOUT
INPUT
OUTPUT
Figure 23. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXn INPUTS
The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as an
analog (SFD) input, the VXn pins function similarly to the VH
and VPn pins. The primary difference is that the VXn pins have
only one input range: 0.573 V to 1.375 V. Therefore, these inputs
can directly supervise only the very low supplies. However, the
input impedance of the VXn pins is high, allowing an external
resistor divide network to be connected to the pin. Thus,
potentially any supply can be divided down into the input range
of the VXn pin and supervised. This enables the ADM1063 to
monitor other supplies such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VP1 to VP4 and VH. The analog function
of VX1 is mapped to VP1, VX2 is mapped to VP2, and so on;
VX5 is mapped to VH. In this case, these SFDs can be viewed as
a secondary or warning SFD.
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be gener-
ated on a single supply using only one pin. For example, if VP1
is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the SE, allowing warnings to generate
interrupts on the PDOs. Therefore, in the previous example, if
the supply drops to 3.1 V, a warning is generated and remedial
action can be taken before the supply drops out of tolerance.

ADM1063
Rev. 0 | Page 15 of 36
VXn PINS AS DIGITAL INPUTS
As discussed in the Supply Supervision with VXn Inputs, the
VXn input pins on the ADM1063 have dual functionality. The
second function is as a digital input to the device. Therefore, the
ADM1063 can be configured for up to five digital inputs. These
inputs are TTL-/CMOS-compatible. Standard logic signals
can be applied to the pins: RESET from reset generators,
POWER_GOOD signals, fault flags, manual resets, and so on.
These signals are available as inputs to the SE and, therefore,
can be used to control the status of the PDOs. The inputs can
be configured to detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block once the logic transition is detected. The width
is programmable from 0 µs to 100 µs.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
When configured as digital inputs, each of the VXn pins has a
weak (10 µA) pull-down current source available for placing the
input into a known condition, even if left floating. The current
source, if selected, weakly pulls the input to GND.
04632-027
DETECTOR
VXn
(DIGITAL INPUT) GLITCH
FILTER
VREF = 1.4V
TO
SEQUENCING
ENGINE
+
–
Figure 24. VXn Digital Input Function

ADM1063
Rev. 0 | Page 16 of 36
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1063 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is taken with the
PDOs based on the condition of the inputs of the ADM1063.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc-to-dc converters, which generate supplies locally on
a board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
•Open-drain (allowing the user to connect an external
pull-up resistor)
•Open-drain with weak pull-up to VDD
•Push/pull to VDD
•Open-drain with weak pull-up to VPn
•Push/pull to VPn
•Strong pull-down to GND
•Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only)
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-channel FET, which is used to isolate, for example, a
card-side voltage from a backplane supply (a PDO can sustain
greater than 10.5 V into a 1 µA load). The pull-down switches
can also be used to drive status LEDs directly.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOnCFG con-
figuration register (see the AN-698 application note for details).
The data sources are as follows:
•Output from the SE.
•Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
•On-Chip Clock. A 100 kHz clock is generated on the
device. This clock can be made available on any of the
PDOs. It can be used, for example, to clock an external
device such as an LED.
By default, the PDOs are pulled to GND by a weak (20 kΩ) on-
chip, pull-down resistor. This is the case upon power-up until
the configuration is downloaded from EEPROM and the
programmed setup is latched. The outputs are actively pulled
low once a supply of 1 V or greater is on VPn or VH. The outputs
remain high impedance prior to 1 V appearing on VPn or VH.
This provides a known condition for the PDOs during power-
up. The internal pull-down can be overdriven with an external
pull-up of suitable value tied from the PDO pin to the required
pull-up voltage. The 20 kΩ resistor must be accounted for in
calculating a suitable value. For example, if PDOn must be pulled
up to 3.3 V and 5 V is available as an external supply, the pull-up
resistor value is given by
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 = 10 kΩ
04632-028
PDO
SE DATA
CFG4 CFG5 CFG6
S
MBus DAT
A
CLK DATA
10Ω
20kΩ
10Ω
20kΩ
VP1
SEL VP4
10Ω
20kΩ
V
DD
V
FET (PDO1 TO PDO6 ONLY)
20kΩ
Figure 25. Programmable Driver Output

ADM1063
Rev. 0 | Page 17 of 36
SEQUENCING ENGINE
OVERVIEW
The ADM1063 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
and so on. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
•Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
•Can be entered from any other state.
•Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
•Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
•Output condition of the 10 PDO pins is defined and fixed
within a state.
•Transition from one state to the next is made in less than
20 µs, which is the time needed to download a state definition
from EEPROM to the SE.
04632-029
SEQUENCE
TIMEOUT
MONITOR
FAULT STATE
Figure 26. State Cell
The ADM1063 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be
generated when the ADC readings violate their limit register
value or when the secondary voltage monitors detect a warning
on VP1 to VP4 and VH. The warnings are OR’ed together and
available as a single warning input to each of the three blocks
that enable exiting a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state uncondition-
ally. This enables the user to force the SE to advance. Examples
of where this might be used include moving to a margining
state or debugging a sequence. The SMBus jump or go-to
command can be seen as another input to sequence and
timeout blocks, which provide an exit from each state.
Table 6. Sample Sequence State Entries
State Sequence Timeout Monitor
IDLE1 If VX1 is low , go to state IDLE2.
IDLE2 If VP1 is okay, go to state EN3V3.
EN3V3 If VP2 is okay, go to state EN2V5. If VP2 is not okay after 10 ms, go to
state DIS3V3.
If VP1 is not okay, go to state IDLE1.
DIS3V3 If VX1 is high, go to state IDLE1.
EN2V5 If VP3 is okay, go to state PWRGD. If VP3 is not okay after 20 ms, go to
state DIS2V5.
If VP1 or VP2 is not okay, go to state FSEL2.
DIS2V5 If VX1 is high, go to state IDLE1.
FSEL1 If VP3 is not okay, go to state DIS2V5. If VP1 or VP2 is not okay, go to state FSEL2.
FSEL2 If VP2 is not okay, go to state DIS3V3. If VP1 is not okay, go to state IDLE1.
PWRGD If VX1 is high, go to state DIS2V5. If VP1, VP2, or VP3 is not okay, go to state
FSEL1.

ADM1063
Rev. 0 | Page 18 of 36
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 27 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
3-supply system.
Table 7 lists the PDO outputs for each state in the same SE
implementation. In this system, the triggers required to start a
power-up sequence are the presence of a good 5 V supply on VP1
and the VX1 pin held low. The sequence intends to turn on the
3.3 V supply next, then the 2.5 V supply (assuming successful
turn-on of the 3.3 V supply). Once all three supplies are good,
the POWER_GOOD state is entered, where the SE remains until
a fault occurs on one of the three supplies, or until it is instructed
to go through a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following sections, which describe the
individual blocks, use this sample application to demonstrate
the state machine’s actions.
04632-030
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES TIMEOUT STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
(VP1 +
VP2) = 0
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
Figure 27. Sample Application Flow Diagram
Table 7. PDO Outputs for Each State
PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1

ADM1063
Rev. 0 | Page 19 of 36
SEQUENCE DETECTOR
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the inputs to
the SE to change state and is most often used as the gate for
successful progress through a power-up or power-down sequence.
A timer block is included in this detector, which can insert delays
into a power-up or power-down sequence if required. Timer
delays can be set from 10 µs to 400 ms. Figure 28 is a block
diagram of the sequence detector.
04632-032
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX5
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
Figure 28. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 27, the FSEL1
and FSEL2 states identify which of the VP1,VP2, or VP3 pins
has faulted, and then they take the appropriate action.
MONITORING FAULT DETECTOR
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the POWER_GOOD state, where the monitor
block indicates that a failure on one or more of the VP1, VP2,
or VP3 inputs has occurred.
No programmable delay is available in this block, because the
triggering of a fault condition is likely to be caused when a supply
falls out of tolerance. In this situation, the user should react as
quickly as possible. Some latency occurs when moving out of
this state, because it takes a finite amount of time (~20 µs) for the
state configuration to download from EEPROM into the SE.
Figure 29 is a block diagram of the monitoring fault detector.
04632-033
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
V
P1
V
X5
MONITORING FAULT
DETECTOR
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
1-BIT FAULT
DETECTOR
FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
Figure 29. Monitoring Fault Detector Block Diagram
TIMEOUT DETECTOR
The timeout detector allows the user to trap a failure and,
thus ensuring proper progress through a power-up or power-
down sequence.
In the sample application shown in Figure 27, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its UV threshold, which is set in the
supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit over-
loading this supply), the timeout block traps the problem. In this
example, if the 3.3 V supply fails within 10 ms, the SE moves to
the DIS3V3 state and turns off this supply by bringing PDO1
low. It also indicates that a fault has occurred by taking PDO3
high. Timeout delays of 100 µs to 400 ms can be programmed.
FAULT REPORTING
The ADM1063 has a fault latch for recording faults. Two registers
are set aside for this purpose. A single bit is assigned to each
input of the device, and a fault on that input sets the relevant
bit. The contents of the fault register can be read out over the
SMBus to determine which input(s) faulted. The fault register
can be enabled/disabled in each state. This ensures that only
real faults are captured and not, for example, undervoltage
trips when the SE is executing a power-down sequence.

ADM1063
Rev. 0 | Page 20 of 36
VOLTAGE READBACK
The ADM1063 has an on-board, 12-bit, accurate ADC for
voltage readback over the SMBus. The ADC has a 12-channel
analog mux on the front end. The 12 channels consist of the
10 SFD inputs (VH, VP1 to VP4, and VX1 to VX5) plus two
channels for temperature readback (discussed in the Remote
Temperature Measurement section). Any or all of these inputs
can be selected to be read, in turn, by the ADC. The circuit
controlling this operation is called the round-robin circuit. The
round-robin circuit can be selected to run through its loop of
conversions once or continuously. Averaging is also provided
for each channel. In this case, the round-robin circuit runs
through its loop of conversions 16 times before returning a
result for each channel. At the end of this cycle, the results are
written to the output registers.
The ADC samples single-sided inputs with respect to the AGND
pin. A 0 V input gives out Code 0, and an input equal to the
voltage on REFIN gives out full code (4095 decimal).
The inputs to the ADC come directly from the VXn pins and
from the back of the input attenuators on the VPn and VH pins,
as shown in Figure 30 and Figure 31.
04632-025
V
Xn
2.048V VREF
NO ATTENUATION
12-BIT
ADC
DIGITIZED
VOLTAGE
READING
Figure 30. ADC Reading on VXn Pins
04632-026
2.048V VREF
ATTENUATION NETWOR
K
(DEPENDS ON RANGE SELECTED)
12-BIT
ADC
DIGITIZED
VOLTAGE
READING
V
Pn/VH
Figure 31. ADC Reading on VPn/VH Pins
The voltage at the input pin can be derived from the
following equation:
V= 4095
CodeADC × Attenuation Factor × 2.048 V
The ADC input voltage ranges for the SFD input ranges
are listed in Table 8.
Table 8. ADC Input Voltage Ranges
SFD Input
Range (V) Attenuation Factor
ADC Input Voltage
Range (V)
0.573 to 1.375 1 0 to 2.048
1.25 to 3 2.181 0 to 4.46
2.5 to 6 4.363 0 to 6.01
4.8 to 14.4 10.472 0 to 14.41
1The upper limit is the absolute maximum allowed voltage on these pins.
The normal way to supply the reference to the ADC on the
REFIN pin is to simply connect the REFOUT pin to the
REFIN pin. REFOUT provides a 2.048 V reference. As such,
the supervising range covers less than half of the normal ADC
range. It is possible, however, to provide the ADC with a more
accurate external reference for improved readback accuracy.
Supplies can also be connected to the input pins purely for ADC
readback, even though they might go above the expected super-
visory range limits (as long as they are not above 6 V, because
this violates the absolute maximum ratings on these pins). For
instance, a 1.5 V supply connected to the VX1 pin can be correctly
read out as an ADC code of approximately 3/4 full scale, but it
always sits above any supervisory limits that can be set on that
pin. The maximum setting for the REFIN pin is 2.048 V.
SUPPLY SUPERVISION WITH THE ADC
In addition to the readback capability, a further level of supervi-
sion is provided by the on-chip, 12-bit ADC. The ADM1063 has
limit registers on which the user can program a maximum or
minimum allowable threshold. Exceeding the threshold generates
a warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1063 should take. Only one register is provided for each
input channel; therefore, either a UV or OV threshold (but not
both) can be set for a given channel. The round-robin circuit
can be enabled via an SMBus write, or it can be programmed to
turn on in any state in the SE program. For example, it can be
set to start once a power-up sequence is complete and all
supplies are known to be within expected tolerance limits.
Note that a latency is built into this supervision, dictated by
the conversion time of the ADC. With all 12 channels selected,
the total time for the round-robin operation (averaging off) is
approximately 6 ms (500 µs per channel selected). Supervision
using the ADC, therefore, does not provide the same real time
response as the SFDs.