Analog Devices AD9396 User manual

Analog/DVI
Dual-Display Interface
AD9396
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Analog/DVI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
150 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
DVI 1.0
150 MHz DVI receiver
Supports HDCP 1.1
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
FUNCTIONAL BLOCK DIAGRAM
05690-001
DATACK
DE
VSYNC
SYNC
PROCESSING
AND
CLOCK
GENERATION
DATACK
2
REF
HSOUT
VSOUT
SOGOUT
DVI RECEIVER
DIGITAL INTERFACE
REFOUT
REFIN
CLAMP A/D
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2
HDCP
2DATACK
HSOUT
VSOUT
SOGOUT
DE
MUXES
R/G/B 8 × 3
OR YCbCr
R/G/B 8 × 3
OR YCbCr
YCbCr (4:2:2
OR 4:4:4)
AD9396
R/G/B OR YPbPr
IN0
R/G/B OR YPbPr
IN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
CKINV
CKEXT
FILT
SCL
SDA
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
MCL
MDA
DDCSCL
DDCSDA
Rx0+
Rx0–
HSYNC
R/G/B 8 × 3
RGB YCbCr MATRIX
SERIAL REGISTER
AND
POWER MANAGEMENT
ANALOG INTERFACE
Figure 1.
GENERAL DESCRIPTION
The AD9396 offers designers the flexibility of an analog
interface and digital visual interface (DVI) receiver integrated
on a single chip. Also included is support for high bandwidth
digital content protection (HDCP).
The AD9396 is a complete 8-bit, 150 MSPS monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and 720p) and FPD resolutions up
to SXGA (1280 × 1024 @ 80 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), program-
mable gain, offset, and clamp control. The user provides only
1.8 V and 3.3 V power supply, analog input, and HSYNC.
Three-state CMOS outputs may be powered from 1.8 V to 3.3V.
The on-chip PLL generates a pixel clock from HSYNC. Pixel
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9396 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
The AD9396 contains a DVI-compatible receiver and supports
all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive
encrypted video content. The AD9396 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9396 is pro-
vided in a space-saving, 100-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0ºC to 70ºC temperature range.

AD9396
Rev. 0 | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Analog Interface Electrical Characteristics............................... 3
Digital Interface Electrical Characteristics ............................... 4
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels........................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Design Guide................................................................................... 11
General Description................................................................... 11
Digital Inputs .............................................................................. 11
Analog Input Signal Handling.................................................. 11
HSYNC and VSYNC Inputs...................................................... 11
Serial Control Port ..................................................................... 11
Output Signal Handling............................................................. 11
Clamping ..................................................................................... 11
Timing.......................................................................................... 15
DVI Receiver ............................................................................... 19
DE Generator .............................................................................. 19
4:4:4 to 4:2:2 Filter ...................................................................... 19
Timing Diagrams........................................................................ 20
2-Wire Serial Register Map ........................................................... 21
2-Wire Serial Control Register Details ........................................ 29
Chip Identification..................................................................... 29
PLL Divider Control .................................................................. 29
Clock Generator Control .......................................................... 29
Input Gain ................................................................................... 30
Input Offset ................................................................................. 30
Sync .............................................................................................. 30
Coast and Clamp Controls........................................................ 31
Status of Detected Signals ......................................................... 31
Polarity Status ............................................................................. 32
BT656 Generation...................................................................... 36
Macrovision................................................................................. 36
Color Space Conversion............................................................ 37
2-Wire Serial Control Port ............................................................ 39
PCB Layout Recommendations.................................................... 41
Analog Interface Inputs............................................................. 41
Power Supply Bypassing ............................................................ 41
PLL ............................................................................................... 41
Outputs (Both Data and Clocks).............................................. 42
Digital Inputs .............................................................................. 42
Color Space Converter (CSC) Common Settings...................... 43
Outline Dimensions ....................................................................... 45
Ordering Guide .......................................................................... 45
REVISION HISTORY
10/05—Revision 0: Initial Version

AD9396
Rev. 0 | Page 3 of 48
SPECIFICATIONS
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
VDD, VD= 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 1.
AD9396KSTZ-100 AD9396KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25°C I –0.6 +1.6/–1.0 ±0.7 +1.8/–1.0 LSB
Integral Nonlinearity 25°C I ±1.0 ±2.1 ±1.1 ±2.25 LSB
No Missing Codes Full Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p–p
Maximum Full VI 1.0 1.0 V p–p
Gain Tempco 25°C V 100 220 ppm/°C
Input Bias Current 25°C V 0.2 1 μA
Input Full-Scale Matching 25C
Full
VI
VI
1.25
1.50
5
7
1.25
1.50
5
7
%FS
%FS
Offset Adjustment Range Full V 50 50 %FS
SWITCHING PERFORMANCE1
Maximum Conversion Rate Full VI 100 150 MSPS
Minimum Conversion Rate Full VI 10 10 MSPS
Data to Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns
SERIAL PORT TIMING
tBUFF Full VI 4.7 4.7 μs
tSTAH Full VI 4.0 4.0 μs
tDHO Full VI 0 0 μs
tDAL Full VI 4.7 4.7 μs
tDAH Full VI 4.0 4.0 μs
tDSU Full VI 250 250 ns
tSTASU Full VI 4.7 4.7 μs
tSTOSU Full VI 4.0 4.0 μs
HSYNC Input Frequency Full VI 15 110 15 110 KHz
Maximum PLL Clock Rate Full VI 100 150 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter 25°C IV 700 700 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/°C
DIGITAL INPUTS (5 V Tolerant)
Input Voltage, High (VIH) Full VI 2.6 2.6 V
Input Voltage, Low (VIL) Full VI 0.8 0.8 V
Input Current, High (IIH) Full V −82 −82 μA
Input Current, Low (IIL) Full V 82 82 μA
Input Capacitance 25°C V 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.4 0.4 V
Duty Cycle, DATACK Full V 45 50 55 45 50 55 %
Output Coding Binary Binary

AD9396
Rev. 0 | Page 4 of 48
AD9396KSTZ-100 AD9396KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit
POWER SUPPLY
VDSupply Voltage Full IV 3.15 3.3 3.47 3.15 3.3 3.47 V
DVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
VDD Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V
PVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
IDSupply Current (VD) 25°C VI 260 300 330 mA
IDVDD Supply Current (DVDD) 25°C VI 45 60 85 mA
IDD Supply Current (VDD)225°C VI 37 10031303mA
IPVDD Supply Current (PVDD) 25°C VI 10 15 20 mA
Total Power Full VI 1.1 1.4 1.15 1.4 W
Power-Down Dissipation Full VI 130 130 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full
Power
25°C V 330 330 MHz
Signal-to-Noise Ratio (SNR) 25°C I 46 46 dB
Without Harmonics
fIN = 40.7 MHz Full V 45 45 dB
Crosstalk Full V 60 60 dBc
THERMAL CHARACTERISTICS
θJA Junction-to-Ambient V 35 35 °C/W
1Drive strength = high.
2DATACK load = 15 pF, data load = 5 pF.
3Specified current and power values with a worst-case pattern (on/off).
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
VDD = VD= 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 2.
AD9396KSTZ-100 AD9396KSTZ-150
Parameter
Test
Level Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bit
DC DIGITAL I/O Specifications
High Level Input Voltage, (VIH) VI 2.5 2.5 V
Low Level Input Voltage, (VIL) VI 0.8 0.8 V
High Level Output Voltage, (VOH) VI VDD − 0.1 V
Low Level Output Voltage, (VOL) VI VDD − 0.1 0.1 0.1 V
DC SPECIFICATIONS
Output High Level IV Output drive = high 36 36 mA
(IOHD) (VOUT = VOH) IV Output drive = low 24 24 mA
Output Low Level IV Output drive = high 12 12 mA
IOLD, (VOUT = VOL) IV Output drive = low 8 8 mA
DATACK High Level IV Output drive = high 40 40 mA
VOHC, (VOUT = VOH) IV Output drive = low 20 20 mA
DATACK Low Level IV Output drive = high 30 30 mA
VOLC, (VOUT = VOL) IV Output drive = low 15 15 mA
Differential Input Voltage, Single-
Ended Amplitude
IV 75 700 75 700 mV

AD9396
Rev. 0 | Page 5 of 48
AD9396KSTZ-100 AD9396KSTZ-150
Parameter
Test
Level Conditions Min Typ Max Min Typ Max Unit
POWER SUPPLY
VDSupply Voltage IV 3.15 3.3 3.47 3.15 3.3 3.47 V
VDD Supply Voltage IV 1.7 3.3 347 1.7 3.3 347 V
DVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V
PVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V
IVD Supply Current (Typical Pattern)1V 80 100 80 110 mA
IVDD Supply Current (Typical Pattern)2V 40 100355 1753mA
IDVDD Supply Current (Typical Pattern)1, 4V 88 110 110 145 mA
IPVDD Supply Current (Typical Pattern)1V 26 35 30 40 mA
Power-Down Supply Current (IPD) VI 130 130 mA
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew
(TDPS)
IV 360 ps
Channel-to-Channel Differential Input
Skew (TCCS)
IV 6
Clock
Period
Low-to-High Transition Time for Data and
Controls (DLHT)
IV Output drive = high;
CL= 10 pF
900 ps
IV
Output drive = low;
CL= 5 pF
1300 ps
Low-to-High Transition Time for
DATACK (DLHT)
IV Output drive = high;
CL= 10 pF
650 ps
IV
Output drive = low;
CL= 5 pF
1200 ps
High-to-Low Transition Time for Data and
Controls (DHLT)
IV Output drive = high;
CL= 10 pF
850 ps
IV
Output drive = low;
CL= 5 pF
1250 ps
High-to-Low Transition Time for
DATACK (DHLT)
IV Output drive = high;
CL= 10 pF
800 ps
IV
Output drive = low;
CL= 5 pF
1200 ps
Clock to Data Skew5(TSKEW) IV –0.5 +2.0 –0.5 2.0 ns
Duty Cycle, DATACK5IV 45 50 55 %
DATACK Frequency (FCIP) VI 20 150 MHz
1The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2The typical pattern contains a gray scale area, output drive = high.
3Specified current and power values with a worst-case pattern (on/off).
4DATACK load = 10 pF, data load = 5 pF.
5Drive strength = high.

AD9396
Rev. 0 | Page 6 of 48
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 4.
Level Test
I 100% production tested.
II 100% production tested at 25°C and sample
tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by
design and characterization testing.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Parameter Rating
VD3.6 V
VDD 3.6 V
DVDD 1.98 V
PVDD 1.98 V
Analog Inputs VDto 0.0 V
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature Range −25°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

AD9396
Rev. 0 | Page 7 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05690-002
V
DD
RED 0 RED 1 RED 2 RED 3 RED 4 RED 5 RED 6 RED 7 GND V
DD
DATACK DE HSOUT SOGOUT VSOUT O/E FIELD SDA SCL PWRDN V
D
R
AIN0
GND R
AIN1
V
D
26
CTL1
27
CTL0
28
NC
29
GND
30
DV
DD 31
GND
32
DV
DD 33
V
D
34
Rx0–
35
Rx0+
36
GND
37
Rx1–
38
Rx1+
39
GND
2
GREEN 7
3
GREEN 6
4
GREEN 5
7
GREEN 2
6
GREEN 3
5
GREEN 4
1
GND
8
GREEN 1
9
GREEN 0
10
V
DD
12
BLUE 7
13
BLUE 6
14
BLUE 5
15
BLUE 4
16
BLUE 3
17
BLUE 2
18
BLUE 1
19
BLUE 0
20
NC
NC = NO CONNECT
21
NC
22
NC
23
NC
24
CTL3
25
CTL2
11
GND
74
G
AIN0
GND
73
SOGIN 0
72
V
D
69
GND
70
SOGIN 1
71
G
AIN1
75
68
B
AIN0
67
V
D
66
B
AIN1
64
HSYNC 0
63
HSYNC 1
62
EXTCLK/COAST
61
VSYNC 0
60
VSYNC 1
59
PV
DD
58
PGND
57
FILT
56
PV
DD
55
PGND
54
PV
DD
53
GND
52
MDA
51
MCL
65
GND
40
Rx2–
41
Rx2+
42
GND
43
RxC+
44
RxC–
45
V
D
46
RTERM
47
GND
48
DV
DD 49
DDCSCL
50
DDCSDA
100
99
98
97 96
95
94
93 92
91 90
89 88 87
86 85
84
83
82 81
80 79
78 77 76
PIN 1
AD9396
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Complete Pinout List
Pin Type Pin No. Mnemonic Function Value
INPUTS 79 RAIN0 Analog Input for Converter R Channel 0 0.0 V to 1.0 V
77 RAIN1 Analog Input for Converter R Channel 1 0.0 V to 1.0 V
74 GAIN0 Analog Input for Converter G Channel 0 0.0 V to 1.0 V
71 GAIN1 Analog Input for Converter G Channel 1 0.0 V to 1.0 V
68 BBAIN0 Analog Input for Converter B Channel 0 0.0 V to 1.0 V
66 BBAIN1 Analog Input for Converter B Channel 1 0.0 V to 1.0 V
64 HSYNC 0 Horizontal SYNC Input for Channel 0 3.3 V CMOS
63 HSYNC 1 Horizontal SYNC Input for Channel 1 3.3 V CMOS
61 VSYNC 0 Vertical SYNC Input for Channel 0 3.3 V CMOS
60 VSYNC 1 Vertical SYNC Input for Channel 1 3.3 V CMOS
73 SOGIN 0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V
70 SOGIN 1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V
62 EXTCLK External Clock Input—Shares Pin with COAST 3.3 V CMOS
62 COAST PLL COAST Signal Input—Shares Pin with EXTCLK 3.3 V CMOS
81 PWRDN Power-Down Control 3.3 V CMOS
OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB VDD
2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB VDD
12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB VDD

AD9396
Rev. 0 | Page 8 of 48
Pin Type Pin No. Mnemonic Function Value
OUTPUTS 89 DATACK Data Output Clock VDD
87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) VDD
85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) VDD
86 SOGOUT SOG Slicer Output VDD
84 O/E FIELD Odd/Even Field Output VDD
24, 25, 26, 27 CTL(3-0) Control 3, 2, 1, and 0. VDD
REFERENCES 57 FILT Connection for External Filter Components for PLL
POWER SUPPLY 80, 76, 72,
67, 45, 33
VDAnalog Power Supply and DVI Terminators 3.3 V
100, 90, 10 VDD Output Power Supply 1.8 V to 3.3 V
59, 56, 54 PVDD PLL Power Supply 1.8 V
48, 32, 30 DVDD Digital Logic Power Supply 1.8 V
GND Ground 0 V
CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS
82 SCL Serial Port Data Clock 3.3 V CMOS
HDCP 49 DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS
50 DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS
51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS
52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS
DIGITAL VIDEO DATA 35 Rx0+ Digital Input Channel 0 True TMDS
34 Rx0− Digital Input Channel 0 Complement TMDS
38 Rx1+ Digital Input Channel 1 True TMDS
37 Rx1− Digital Input Channel 1 Complement TMDS
41 Rx2+ Digital Input Channel 2 True TMDS
40 Rx2− Digital Input Channel 2 Complement TMDS
DIGITAL VIDEO CLOCK
INPUTS
43 RxC+ Digital Data Clock True TMDS
44 RxC− Digital Data Clock Complement TMDS
DATA ENABLE 88 DE Data Enable 3.3 V CMOS
RTERM 46 RTERM Sets Internal Termination Resistance 500 Ω
Table 6. Pin Function Descriptions
Mnemonic Description
INPUTS
RAIN0 Analog Input for the Red Channel 0.
GAIN0 Analog Input for the Green Channel 0.
BBAIN0 Analog Input for the Blue Channel 0.
RAIN1 Analog Input for the Red Channel 1.
GAIN1 Analog Input for the Green Channel 1.
BBAIN1 Analog Input for Blue Channel 1.
High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three channels
are identical and can be used for any colors, but colors are assigned for convenient reference. They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation
(see Figure 3 for an input reference circuit).
Rx0+ Digital Input Channel 0 True.
Rx0− Digital Input Channel 0 Complement.
Rx1+ Digital Input Channel 1 True.
Rx1− Digital Input Channel 1 Complement.
Rx2+ Digital Input Channel 2 True.
Rx2− Digital input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel rate)
from a digital graphics transmitter.

AD9396
Rev. 0 | Page 9 of 48
Mnemonic Description
RxC+ Digital Data Clock True.
RxC− Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
HSYNC 0 Horizontal Sync Input Channel 0.
HSYNC 1 Horizontal Sync Input Channel 1.
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency
reference for pixel clock generation. The logic sense of this pin is controlled by Serial Register 0x12, Bits 5:4 (HSYNC
polarity). Only the leading edge of HSYNC is active; the trailing edge is ignored. When HSYNC polarity = 0, the falling
edge of HSYNC is used. When HSYNC polarity = 1, the rising edge is active. The input includes a Schmitt trigger for
noise immunity.
VSYNC 0 Vertical Sync Input Channel 0.
VSYNC 1 Vertical Sync Input Channel 1.
These are the inputs for vertical sync.
SOGIN 0 Sync-on-Green Input Channel 0.
SOGIN 1 Sync-on-Green Input Channel 1.
These inputs are provided to assist with processing signals with embedded sync, typically on the green channel. The
pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be
programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal.
The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical
and horizontal sync (HSYNC) information that must be separated before passing the horizontal sync signal to HSYNC.)
When not used, this input should be left unconnected. For more details on this function and how it should be
configured, refer to the HSYNC and VSYNC Inputs section.
EXTCLK/COAST Coast Input to Clock Generator (Optional).
This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue producing a
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce
horizontal sync pulses during the vertical interval. The coast signal is generally not required for PC-generated signals.
The logic sense of this pin is controlled by coast polarity (Register 0x18, Bits 6:5). When not used, this pin may be
grounded and input coast polarity programmed to 1 (Register 0x18, Pin 5), or tied high (to VDthrough a 10 kΩ resistor)
and input coast polarity programmed to 0. Input coast polarity defaults to 1 at power-up. This pin is shared with the
EXTCLK function, which does not affect coast functionality. For more details on coast, see the description in the Clock
Generation section.
EXTCLK/COAST External Clock.
This allows the insertion of an external clock source rather than the internally generated PLL-locked clock. This pin is
shared with the coast function, does not affect EXTCLK functionality.
RTERM RTERM is the termination resistor used to drive the AD9396 internally to a precise 50 Ω termination for TMDS lines. This
should be a 500 Ω 1% tolerance resistor.
PWRDN Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
FILT External Filter Connection.
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to
this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the section on
PCB Layout Recommendations.
OUTPUTS
HSOUT Horizontal Sync Output.
A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be
programmed via the serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.
VSOUT Vertical Sync Output.
The separated VSYNC from a composite signal or a direct passthrough of the VSYNC signal. The polarity of this output
can be controlled via serial bus bit (Register 0x24 [6]).
SOGOUT Sync-on-Green Slicer Output.
This pin outputs one of four possible signals (controlled by Register 0x24 [2:1]): raw SOG, raw HSYNC, regenerated
HSYNC from the filter, or the filtered HSYNC. See Figure 8, the Sync Processing Block Diagram, to view how this pin is
connected. (Note: besides slicing off SOG, the output from this pin is not processed on the AD9396. VSYNC separation
is performed via the sync separator.
O/E FIELD Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd
or even. The polarity of this signal is programmable via Register 0x24 [4].

AD9396
Rev. 0 | Page 10 of 48
Mnemonic Description
DATA ENABLE Data Enable that defines valid video. Can be received in the signal or generated by the AD9396.
CTL(3 to 0) Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0 specification for
explanation.
SERIAL PORT
SDA Serial Port Data I/O for Programming AD9396 Registers—I2C® Address is 0x98.
SCL Serial Port Data Clock for Programming AD9396 Registers.
DDCSDA Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76.
DDCSCL Serial Port Data Clock for HDCP Communications to Transmitter.
MDA Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0.
MCL Serial Port Data Clock to EEPROM with HDCP Keys.
DATA OUTPUTS
Red [7:0] Data Output, Red Channel.
Green [7:0] Data Output, Green Channel.
Blue [7:0] Data Output, Blue Channel.
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the
color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is
shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is
maintained.
DATA CLOCK
OUTPUT
DATACK Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
POWER SUPPLY1
VD(3.3 V) Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
VDD
(1.8 V to 3.3 V)
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VDpins, so take care to minimize output noise
transferred into the sensitive analog circuitry. If the AD9396 is interfacing with lower voltage logic, VDD may be
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
PVDD (1.8 V) Clock Generator Power Supply.
The most sensitive portion of the AD9396 is the clock generation circuitry. These pins provide power to the clock PLL
and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
DVDD (1.8 V) Digital Input Power Supply.
This supplies power to the digital logic.
GND Ground.
The ground return for all circuitry on-chip. It is recommended that the AD9396 be assembled on a single solid ground
plane, with careful attention to ground current paths.
1The supplies should be sequenced such that VDand VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VDor VDD.

AD9396
Rev. 0 | Page 11 of 48
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9396 is a fully integrated solution for capturing analog
RGB or YUV signals and digitizing them for display on flat
panel monitors, projectors, or PDPs. In addition, the AD9396
has a digital interface for receiving DVI signals and is capable of
decoding HDCP-encrypted signals through connections to an
external EEPROM. The circuit is ideal for providing an
interface for HDTV monitors or as the front end to high
performance video scan converters.
Implemented in a high performance CMOS process, the
interface can capture signals with pixel rates of up to 150 MHz.
The AD9396 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. Included in the output formatting is a
color space converter (CSC), which accommodates any input
color space and can output any color space. All controls are
programmable via a 2-wire serial interface. Full integration of
these sensitive analog functions makes system design straight-
forward and less sensitive to the physical and electrical
environment.
DIGITAL INPUTS
All digital control inputs (HSYNC, VSYNC, I2C) on the
AD9396 operate to 3.3 V CMOS levels. In addition, all digital
inputs except the TMDS (HDMI/DVI) inputs are 5 V tolerant.
(Applying 5 V to them does not cause any damage.) TMDS
inputs (Rx0+/Rx0−, Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−)
must maintain a 100 Ω differential impedance (through proper
PCB layout) from the connector to the input where they are
internally terminated (50 Ω to 3.3 V). If additional ESD
protection is desired, use of a California Micro Devices (CMD)
CM1213 (among others) series low capacitance ESD protection
offers 8 kV of protection to the HDMI TMDS lines.
ANALOG INPUT SIGNAL HANDLING
The AD9396 has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V p-p to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or RCA-type con-
nectors. The AD9396 should be located as close as practical to
the input connector. Signals should be routed via 75  matched
impedance traces to the IC input pins.
At the input pins, the signal should be resistively terminated
(75  to the signal ground return) and capacitively coupled to
the AD9396 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9396
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitizes the pixel during a
long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 HIGH SPEED
SIGNAL CHIP BEAD inductor in the circuit, as shown in
Figure 3, gives good results in most applications.
RGB
INPUT
47nF
75Ω
05690-003
R
AIN
G
AIN
B
AIN
Figure 3. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a prepro-
cessed TTL or CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer for
immunity to noise and signals with long rise times. In typical
PC-based graphic systems, the sync signals are TTL-level
drivers feeding unshielded wires in the monitor cable. As such,
no termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.
OUTPUT SIGNAL HANDLING
The digital outputs are designed to operate from 1.8 V to 3.3 V
(VDD).
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADC.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.

AD9396
Rev. 0 | Page 12 of 48
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9396.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the ADCs producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC, called the back porch, where
a good black reference is provided. This is the time when
clamping should be done.
Clamp timing employs the AD9396 internal clamp timing
generator. The clamp placement register is programmed with
the number of pixel periods that should pass after the trailing
edge of HSYNC before clamping starts. A second register
(clamp duration) sets the duration of the clamp. These are both
8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of HSYNC because, though HSYNC duration can vary widely,
the back porch (black reference) always follows HSYNC. A
good starting point for establishing clamping is to set the clamp
placement to 0x08 (providing 8 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to 0x14
(giving the clamp 20 pixel periods to re-establish the black
reference). For three-level syncs embedded on the green
channel, it is necessary to increase the clamp placement to
beyond the positive portion of the sync. For example, a good
clamp placement (Register 0x19) for a 720p input is 0x26. This
delays the start of clamp by 38 pixel clock cycles after the rising
edge of the three-level sync, allowing plenty of time for the
signal to return to a black reference.
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capa-
citor affects the performance of the clamp. If it is too small,
there is a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
then it takes excessively long for the clamp to recover from a
large change in the incoming signal offset. The recommended
value (47 nF) results in recovering from a step error of 100 mV
to within ½ LSB in 10 lines with a clamp duration of 20 pixel
periods on a 75 Hz SXGA signal.
YUV Clamping
YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be
at the midpoint of the graphics signal rather than the bottom.
For these signals it can be necessary to clamp to the midscale
range of the ADC range (128) rather than the bottom of the
ADC range (0).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0x1B [7:5]. The midscale reference
voltage is internally generated for each converter.
Auto-Offset
The auto-offset circuit works by calculating the required offset
setting to yield a given output code during clamp. When this
block is enabled, the offset setting in the I2C is seen as a desired
clamp code rather than an actual offset. The circuit compares
the output code during clamp to the desired code and adjusts
the offset up or down to compensate.
The offset on the AD9396 can be adjusted automatically to a
specified target code. This option allows the user to set the
offset to any value and be assured that all channels with the
same value programmed into the target code will match. This
eliminates any need to adjust the offset at the factory. This
function is capable of running continuously any time the clamp
is asserted.
There is an offset adjust register for each channel, namely the
offset registers at the 0x08, 0x0A, and 0x0C addresses. The
offset adjustment is a signed (twos complement) number with
±64 LSB range. The offset adjustment is added to whatever
offset the auto-offset comes up with. For example: using ground
clamp, the target code is set to 4. To get this code, the auto-
offset generates an offset of 68. If the offset adjustment is set to
+10, the offset sent to the converter is 78. Likewise, if the offset
adjust is set to −10, the offset sent to the converter is 58. Refer
to application note AN-775, Implementing the Auto-Offset
Function of the AD9880, for a detailed description of how to use
this function.
Sync-on-Green (SOG)
The SOG input operates in two steps. First, it sets a baseline
clamp level from the incoming video signal with a negative peak
detector. Second, it sets the sync trigger level to a program-
mable level (typically 150 mV) above the negative peak. The
SOG input must be ac-coupled to the green analog input
through its own capacitor. The value of the capacitor must be
1 nF ± 20%. If SOG is not used, this connection is not required.

AD9396
Rev. 0 | Page 13 of 48
Note that the SOG signal is always negative polarity. For more
detail on setting the SOG threshold and other SOG-related
functions, see the Sync Processing section.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is shown in Figure 6. Recommended settings
of the VCO range and charge pump current for VESA standard
display modes are listed in Table 9.
05690-004
G
AIN
SOG
1nF
R
AIN
47nF
B
AIN
47nF
47nF
C
P
8
nF C
Z
80nF
R
Z
1.5kΩ
FILT
PV
D
05690-006
Figure 4. Typical Clamp Configuration for RGB/YUV Applications
Figure 6. PLL Loop Filter Detail
Clock Generation
Four programmable registers are provided to optimize the
performance of the PLL. These registers are:
A PLL is employed to generate the pixel clock. In this PLL,
the HSYNC input provides a reference frequency. A voltage
controlled oscillator (VCO) generates a much higher pixel clock
frequency. This pixel clock is divided by the PLL divide value
(Register 0x01 and Register 0x02) and phase compared with the
HSYNC input. Any error is used to shift the VCO frequency
and to maintain the lock between the two signals.
•The 12-bit divisor register (R0x01, R0x02). The input
HSYNC frequency range can be any frequency which,
combined with the PLL_Div, does not exceed the VCO
range. The PLL multiplies the frequency of the HSYNC
signal, producing pixel clock frequencies in the range of
10 MHz to 100 MHz. The divisor register controls the
exact multiplication factor.
The stability of this clock is a very important element in provi-
ding the clearest and most stable image. During each pixel time,
there is a period during which the signal slews from the old
pixel amplitude and settles at its new value. This is followed by a
time when the input voltage is stable before the signal must slew
to a new value. The ratio of the slewing time to the stable time is
a function of the bandwidth of the graphics DAC and the
bandwidth of the transmission system (cable and termination).
It is also a function of the overall pixel rate. Clearly, if the
dynamic characteristics of the system remain fixed, then the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter and
the stable pixel time also becomes shorter.
•The 2-bit VCO range register (R0x03). To improve the
noise performance of the AD9396, the VCO operating
frequency range is divided into four overlapping regions.
The VCO range register sets this operating range. The
frequency ranges for the lowest and highest regions are
shown in Table 7.
Table 7.
VCORNGE Pixel Rate Range
00 12 to 30
01 30 to 60
10 60 to 120
11 120 to 150
PIXEL CLOCK INVALID SAMPLE TIMES
05690-005
•The 5-bit phase adjust register (R0x05). The phase of the
generated sampling clock can be shifted to locate an
optimum sampling point within a clock cycle. The phase
adjust register provides 32 phase-shift steps of 11.25° each.
The HSYNC signal with an identical phase shift is available
through the HSOUT pin.
The coast pin or the internal coast is used to allow the PLL to
continue to run at the same frequency, in the absence of the
incoming HSYNC signal or during disturbances in HSYNC
(such as equalization pulses). This can be used during the
vertical sync period or any other time that the HSYNC signal is
unavailable. The polarity of the coast signal can be set through
the coast polarity register. Also, the polarity of the HSYNC
signal can be set through the HSYNC polarity register. For both
HSYNC and coast, a value of 1 is active high. The internal coast
function is driven from the VSYNC signal, which is typically a
time when HSYNC signals can be disrupted with extra
equalization pulses.
Figure 5. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9396 clock generation circuit to minimize
jitter. The clock jitter of the AD9396 is less than 13% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.

AD9396
Rev. 0 | Page 14 of 48
Power Management
The AD9396 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full-power,
seek mode, auto power-down, and power-down.
Table 8 summarizes how the AD9396 determines the power
mode and the circuitry that is powered on/off in each of these
modes. The power-down command has priority and then the
automatic circuitry. The power-down pin (Pin 81—polarity set
by Register 0x26[3]) can drive the chip into four power-down
options. Bit 2 and Bit 1 of Register 0x26 control these four
options. Bit 0 controls whether the chip is powered down or the
outputs are placed in high impedance mode (with the exception
of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the
outputs, SOG, Sony Philips digital interface (SPDIF ) or I2S (IIS
or Inter-IC sound bus) outputs are in high impedance mode or
not. See the 2-Wire Serial Control Register Detail section for
more detail.
Table 8. Power-Down Mode Descriptions
Inputs
Mode Power-Down1Sync Detect2Auto PD Enable3Power-On or Comments
Full Power 1 1 X Everything
Seek Mode 1 0 0 Everything
Seek Mode 1 0 1 Serial bus, sync activity detect, SOG, band gap
reference
Power-Down 0 X Serial bus, sync activity detect, SOG, band gap
reference
1Power-down is controlled via Bit 0 in Serial Bus Register 0x26.
2Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15.
3Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard Resolution
Refresh Rate
(Hz)
Horizontal
Frequency (kHz) Pixel Rate (MHz) VCO Range1 Current1
VGA 640 × 480 60 31.5 25.175 00 101
72 37.7 31.500 01 011
75 37.5 31.500 01 100
85 43.3 36.000 01 100
SVGA 800 × 600 56 35.1 36.000 01 100
60 37.9 40.000 01 101
72 48.1 50.000 01 110
75 46.9 49.500 01 110
85 53.7 56.250 01 110
XGA 1024 × 768 60 48.4 65.000 10 011
70 56.5 75.000 10 100
75 60.0 78.750 10 100
80 64.0 85.500 10 101
85 68.3 94.500 10 110
SXGA 1280 × 1024 60 64.0 108.000 10 110
1280 × 1024 75 80.0 135.000 11 110
TV 480i 60 15.75 13.51 00 010
480p 60 31.47 27 00 101
720p 60 45 74.25 10 100
1035i 60 33.75 74.25 10 100
1080i 60 33.75 74.25 10 100
1080p 60 67.5 148.5 11 110
1These are preliminary recommendations for the analog PLL and are subject to change without notice.

AD9396
Rev. 0 | Page 15 of 48
TIMING
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
There is a pipeline in the AD9396, which must be flushed
before valid data becomes available. This means 23 data sets are
presented before valid data is available.
The timing diagram in Figure 7 shows the operation of the
AD9396.
t
PER
t
DCYCLE
t
SKEW
DATAC
K
05690-009
DATA
HSOUT
Figure 7. Output Timing
HSYNC Timing
Horizontal sync (HSYNC) is processed in the AD9396 to
eliminate ambiguity in the timing of the leading edge with
respect to the phase-delayed pixel clock and data.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to HSYNC, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use HSYNC to align memory and display write cycles,
so it is important to have a stable timing relationship between
the HSYNC output (HSOUT) and data clock (DATACK).
Three things happen to HSYNC in the AD9396. First, the
polarity of HSYNC input is determined and thus has a known
output polarity. The known output polarity can be programmed
either active high or active low (Register 0x24, Bit 7). Second,
HSOUT is aligned with DATACK and data outputs. Third, the
duration of HSOUT (in pixel clocks) is set via Register 0x23.
HSOUT is the sync signal that should be used to drive the rest
of the display system.
Coast Timing
In most computer systems, the HSYNC signal is provided con-
tinuously on a dedicated wire. In these systems, the coast input
and function are unnecessary, and should not be used. The pin
should be permanently connected to the inactive state.
In some systems, however, HSYNC is disturbed during the
vertical sync period (VSYNC). In some cases, HSYNC pulses
disappear. In other systems, such as those that employ
composite sync (Csync) signals or embedded SOG, HSYNC
includes equalization pulses or other distortions during
VSYNC. To avoid upsetting the clock generator during VSYNC,
it is important to ignore these distortions. If the pixel clock PLL
sees extraneous pulses, it attempts to lock to this new frequency,
and changes frequency by the end of the VSYNC period. It then
takes a few lines of correct HSYNC timing to recover at the
beginning of a new frame, tearing the image at the top of the
display.
The coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
Coast can be generated internally by the AD9396 (see
Register 0x12[1]), can be driven directly from a VSYNC input,
or can be provided externally by the graphics controller.

AD9396
Rev. 0 | Page 16 of 48
Sync Processing
The inputs of the sync processing section of the AD9396 are
combinations of digital HSYNCs and VSYNCs, analog sync-on-
green, or sync-on-Y signals, and an optional external coast
signal. From these signals, it generates a precise, jitter-free (9%
or less at 95 MHz) clock from its PLL; an odd/even field signal;
HSYNC and VSYNC out signals; a count of HSYNCs per
VSYNC; and a programmable SOG output. The main sync
processing blocks are the sync slicer, sync separator, HSYNC
filter, HSYNC regenerator, VSYNC filter, and coast generator.
The sync slicer extracts the sync signal from the green graphics
or luminance video signal that is connected to the SOGIN input
and outputs a digital composite sync. The sync separator’s task
is to extract VSYNC from the composite sync signal, which can
come from either the sync slicer or the HSYNC input. The
HSYNC filter is used to eliminate any extraneous pulses from
the HSYNC or SOGIN inputs, outputting a clean, low jitter
signal that is appropriate for mode detection and clock
generation. The HSYNC regenerator is used to re-create a clean,
although not low jitter, HSYNC signal that can be used for
mode detection and counting HSYNCs per VSYNC. The
VSYNC filter is used to eliminate spurious VSYNCs, maintain a
stable timing relationship between the VSYNC and HSYNC
output signals, and generate the odd/even field output. The
coast generator creates a robust coast signal that allows the PLL
to maintain its frequency in the absence of HSYNC pulses.
05690-007
AD9396
PLL CLOCK
GENERATOR
HSYNC FILTER
AND
REGENERATOR
HSYNC 0
SOG OUT
HSYNC
COAST
DATACK
SOGIN 0
COAST
CHANNEL
SELECT
VSYNC 1
O/E
FIELD
MUX
MUX
MUX
RH
3
FH
4
SP
5 MUX
1
ACTIVITY DETECT
2
POLARITY DETECT
3
REGENERATED HSYNC
4
FILTERED HSYNC
5
SET POLARITY
SP
5
AD
1
PD
2
PD
2
AD
1
PD
2
AD
1
PD
2
SYNC
SLICER
SYNC
SLICER
VSYNC 0
HSYNC 1
HSYNC OUT
VSYNC OUT
SOGIN 1
HSYNC/VSYNC
COUNTER
REG 26H, 27H
SYNC
PROCESSOR
AND
VSYNC FILTER
MUX
MUX
PLL SYNC FILTER EN
0x21:6
SP SYNC FILTER EN
0x21:7
SOGOUT SELECT
0x24:2,1
[0x11:7]
HSYNC
SELECT
[0x11:3]
COAST SELECT
0x12:1
VSYNC FILTER EN
0x21:5
FILTER COAST VSYNC
0x12:0
VSYNC VSYNC
FILTERED
VSYNC
AD
1
AD
1
AD
1
SP
5
SP
5
MUX
MUX
MUX
Figure 8. Sync Processing Block Diagram

AD9396
Rev. 0 | Page 17 of 48
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOGIN input. The sync signal is extracted in a two-step
process. First, the SOG input (typically 0.3 V below the black
level) is detected and clamped to a known dc voltage. Next, the
signal is routed to a comparator with a variable trigger level (set
by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the
clamped voltage. The sync slicer output is a digital composite
sync signal containing both HSYNC and VSYNC information
(see Figure 9).
Sync Separator
As part of sync processing, the sync separator’s task is to extract
VSYNC from the composite sync signal. It works on the idea
that the VSYNC signal stays active for a much longer time than
the HSYNC signal. By using a digital low-pass filter and a
digital comparator, it rejects pulses with small durations (such
as HSYNCs and equalization pulses) and only passes pulses
with large durations, such as VSYNC (see Figure 9).
The threshold of the digital comparator is programmable for
maximum flexibility. To program the threshold duration, write
a value (N) to Register 0x11. The resulting pulse width is
N × 200 ns. So if N = 5, the digital comparator threshold is 1 µs.
Any pulses less than 1 µs are rejected, while any pulse greater
than 1 µs passes through.
The sync separator on the AD9396 is simply an 8-bit digital
counter with a 6 MHz clock. It works independently of the
polarity of the composite sync signal. Polarities are determined
elsewhere on the chip. The basic idea is that the counter counts
up when HSYNC pulses are present. But because HSYNC
pulses are relatively short in width, the counter only reaches a
value of N before the pulse ends. It then starts counting down
until eventually reaching 0 before the next HSYNC pulse
arrives. The specific value of N varies for different video modes,
but is always less than 255. For example, with a 1 s width
HSYNC, the counter only reaches 5 (1 s/200 ns = 5). Now,
when VSYNC is present on the composite sync the counter also
counts up. However, because the VSYNC signal is much longer,
it counts to a higher number, M. For most video modes, M is at
least 255. So VSYNC can be detected on the composite sync
signal by detecting when the counter counts to higher than N.
The specific count that triggers detection, T, can be
programmed through the Serial Register 0x11.
Once VSYNC has been detected, there is a similar process to
detect when it goes inactive. At detection, the counter first
resets to 0, then starts counting up when VSYNC finishes. As in
the previous case, it detects the absence of VSYNC when the
counter reaches the threshold count, T. In this way, it rejects
noise and/or serration pulses. Once VSYNC is detected to be
absent, the counter resets to 0 and begins the cycle again.
There are two things to keep in mind when using the sync
separator. First, the resulting clean VSYNC output is delayed
from the original VSYNC by a duration equal to the digital
comparator threshold (N × 200 ns). Second, there is some
variability to the 200 ns multiplier value. The maximum varia-
bility over all operating conditions is ±20% (160 ns to 240 ns).
Because normal VSYNC and HSYNC pulse widths differ by a
factor of about 500 or more, 20% variability is not an issue.
05690-008
SOGIN
S
OGOUT OUTPUT
CONNECTED TO
HSIN
NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS
COMPOSITE
SYNC
AT HSIN
VSOUT
FROM SYNC
SEPARATOR
–300mV
+300mV
700mV MAXIMUM
0mV
Figure 9. Sync Slicer and Sync Separator Output

AD9396
Rev. 0 | Page 18 of 48
HSYNC Filter and Regenerator
The HSYNC filter is used to eliminate any extraneous pulses
from the HSYNC or SOGIN inputs, outputting a clean, low
jitter signal that is appropriate for mode detection and clock
generation. The HSYNC regenerator is used to re-create a clean,
although not low jitter, HSYNC signal that can be used for
mode detection and counting HSYNCs per VSYNC. The
HSYNC regenerator has a high degree of tolerance to
extraneous and missing pulses on the HSYNC input, but is not
appropriate for use by the PLL in creating the pixel clock
because of jitter.
The HSYNC regenerator runs automatically and requires no
setup to operate. The HSYNC filter requires setting up a filter
window. The filter window sets a periodic window of time
around the regenerated HSYNC leading edge where valid
HSYNCs are allowed to occur. The general idea is that
extraneous pulses on the sync input occur outside of this filter
window and thus are filtered out. To set the filter window
timing, program a value (x) into Register 0x20. The resulting
filter window time is ±x times 25 ns around the regenerated
HSYNC leading edge. Just as for the sync separator threshold
multiplier, allow a ±20% variance in the 25 ns multiplier to
account for all operating conditions (20 ns to 30 ns range).
A second output from the HSYNC filter is a status bit
(Register 0x16[0]) that tells whether extraneous pulses are
present on the incoming sync signal. Extraneous pulses are
often included for copy protection purposes; this status bit can
be used to detect that.
The filtered HSYNC (rather than the raw HSYNC/SOGIN
signal) for pixel clock generation by the PLL is controlled by
Register 0x21[6]. The regenerated HSYNC (rather than the
raw HSYNC/SOGIN signal) for sync processing is controlled by
Register 0x21[7]. Use of the filtered HSYNC and regenerated
HSYNC is recommended. See Figure 10 for an illustration of a
filtered HSYNC.
HSOUT
VSYNC
FILTER
W
INDOW
EXPECTED
EDGE
FILTER
WINDOW
EQUALIZATION
PULSES
HSIN
05690-010
Figure 10. Sync Processing Filter

AD9396
Rev. 0 | Page 19 of 48
VSYNC Filter and Odd/Even Fields
The VSYNC filter is used to eliminate spurious VSYNCs,
maintain a consistent timing relationship between the VSYNC
and HSYNC output signals, and generate the odd/even field
output.
The filter works by examining the placement of VSYNC with
respect to HSYNC and, if necessary, slightly shifting it in time at
the VSOUT output. The goal is to keep the VSYNC and
HSYNC leading edges from switching at the same time,
eliminating confusion as to when the first line of a frame
occurs. Enabling the VSYNC filter is done with Register
0x21[5]. Use of the VSYNC filter is recommended for all cases,
including interlaced video and is required when using the
HSYNC per VSYNC counter. Figure 12 illustrates even/odd
field determination in two situations.
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 214431
HSIN
VSIN
VSOUT
O/E FIELD
EVEN FIELD
QUADRAN
T
05690-011
Figure 11.
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 21431
HSIN
VSIN
4
VSOUT
O/E FIELD
ODD FIELD
QUADRAN
T
05690-012
Figure 12. VSYNC Filter—Odd/Even
DVI RECEIVER
The DVI receiver section of the AD9396 allows the reception of
a digital video stream compatible with DVI 1.0. Embedded in
this data stream are HSYNCs, VSYNCs and display enable (DE)
signals. DVI restricts the received format to RGB, but the
inclusion of a programmable color space converter (CSC)
allows the output to be tailored to any format necessary. With
this, the scaler following the AD9396 can specify that it always
wishes to receive a particular format—for instance, 4:2:2
YCrCb—regardless of the transmitted mode. If RGB is sent, the
CSC can easily convert that to 4:2:2 YCrCb while relieving the
scaler of this task.
DE GENERATOR
The AD9396 has an on-board generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656-compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not used. This signal alerts the following circuitry as to
which are displayable video pixels.
4:4:4 TO 4:2:2 FILTER
The AD9396 contains a filter that allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color Space to Output Color space
The AD9396 can support a wide variety of output formats, such
as the following:
•RGB 24-bit
•4:4:4 YCrCb 8-bit
•4:2:2 YCrCb 8-bit, 10-bit, and 12-bit
•Dual 4:2:2 YCrCb 8-bit
Color Space Conversion (CSC) Matrix
The color space conversion (CSC) matrix in the AD9396
consists of three identical processing channels. In each channel,
three input values are multiplied by three separate coefficients.
Also included are an offset value for each row of the matrix and
a scaling multiple for all values. Each value has a 13-bit, twos
complement resolution to ensure the signal integrity is main-
tained. The CSC is designed to run at speeds up to 150 MHz
supporting resolutions up to 1080p at 60 Hz. With any-to-any
color space support, formats such as RGB, YUV, YCbCr, and
others are supported by the CSC.
The main inputs, RIN, GIN, and BIN come from the 8-bit to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in Table 11 . The mapping of these inputs to the
CSC inputs is shown in Table 10 .
Table 10. CSC Port Mapping
Input Channel CSC Input Channel
R/CR RIN
Gr/Y GIN
B/CB BBIN
One of the three channels is represented in Figure 13. In each
processing channel the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
−0.9998 to +0.9998. The variable labeled ‘a4’ is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2CSC_Mode.

AD9396
Rev. 0 | Page 20 of 48
The functional diagram for a single channel of the CSC, as
shown in Figure 13, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings.
For a detailed functional description and more programming
examples, refer to the application note AN-795, AD9880 Color
Space Converter User's Guide.
TIMING DIAGRAMS
The following timing diagrams show the operation of the
AD9396.The output data clock signal is created so that its rising
edge always occurs between data transitions and can be used to
latch the output data externally. There is a pipeline in the
AD9396, which must be flushed before valid data becomes
available. This means six data sets are presented before valid
data is available.
05690-013
×2
2
1
0
×
×
×
a1[12:0]
a2[12:0]
a3[12:0]
R
IN
[11:0]
B
IN
[11:0]
G
IN
[11:0]
+
×4
CSC_Mode[1:0]
a4[12:0]
R
OUT
[11:0]
+
1
4096
×
1
4096
×
1
4096
×
+
Figure 13. Single CSC Channel
DATAIN P0 P1 P2 P5P3 P4 P9P6 P8 P10 P11P7
HSIN
DATACK
8 CLOCK CYCLE DELAYS
DATAOUT P0 P1 P2 P3
2 CLOCK CYCLE DELAYS
HSOUT
05690-014
Figure 14. RGB ADC Timing
DATAIN P0 P1 P2 P5P3 P4 P9P6 P8 P10 P11P7
HSIN
DATACK
8 CLOCK CYCLE DELAYS
CB/CROUT B0 R0 B2 R2
YOUT Y0 Y1 Y2 Y3
2 CLOCK CYCLE DELAYS
NOTES:
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.
HSOUT
05690-015
Figure 15. YCrCb ADC Timing
Table 11.
Port Red Green Blue
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
4:4:4 Red/Cr [7:0] Green/Y [7:0] Blue/Cb [7:0]
4:2:2 CbCr [7:0] Y [7:0] DDR 4:2:2 ↑CbCr ↓Y, Y
DDR ↑1G [3:0] DDR ↑B [7:4] DDR ↑B [3:0] DDR 4:2:2 ↑CbCr [11:0]
4:4:4 DDR
DDR ↓R [7:0] DDR ↓G [7:4] DDR 4:2:2 ↓Y,Y [11:0]
4:2:2 to 12 CbCr [11:0] Y [11:0]
1Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.