Analog Devices Super Sequencer ADM1168 User manual

Super Sequencer and Monitor with
Nonvolatile Fault Recording
ADM1168
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
16 event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
NFET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
FUNCTIONAL BLOCK DIAGRAM
PDO7
PDO8
PDOGND
VDD
ARBITRATOR
GND
VCCP
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
V
DDCAP
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
SD
A
SCL
A
1
A
0
SMBus
INTERFACE
REFOUT REFGND
VREF
ADM1168
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF NFET)
EEPROMFAULT RECORDING
09474-001
Figure 1.
GENERAL DESCRIPTION
The ADM1168 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.
The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-window
faults on up to eight supplies. In addition, eight programmable
outputs can be used as logic enables. Six of these programmable
outputs can also provide up to a 12 V output for driving the gate
of an NFET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs based
on the condition of the inputs.
A block of nonvolatile EEPROM is available that can be used to
store user-defined information and may also be used to hold a
number of fault records that are written by the sequencing engine
defined by the user when a particular fault or sequence occurs.
The ADM1168 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1168 register map, refer
to the AN-721 Application Note.

ADM1168
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Detailed Block Diagram .................................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Powering the ADM1168................................................................ 10
Inputs................................................................................................ 11
Supply Supervision..................................................................... 11
Programming the Supply Fault Detectors............................... 11
Input Comparator Hysteresis.................................................... 12
Input Glitch Filtering ................................................................. 12
Supply Supervision with VXx Inputs....................................... 13
VXx Pins as Digital Inputs ........................................................ 13
Outputs ............................................................................................ 14
Supply Sequencing Through Configurable Output Drivers. 14
Default Output Configuration.................................................. 14
Sequencing Engine ......................................................................... 15
Overview ..................................................................................... 15
Warnings...................................................................................... 15
SMBus Jump (Unconditional Jump)........................................ 15
Sequencing Engine Application Example............................... 16
Fault and Status Reporting........................................................ 17
Nonvolatile Black Box Fault Recording................................... 17
Black Box Writes with No External Supply ............................ 18
Applications Diagram .................................................................... 19
Communicating with the ADM1168........................................... 20
Configuration Download at Power-Up................................... 20
Updating the Configuration ..................................................... 20
Updating the Sequencing Engine............................................. 21
Internal Registers........................................................................ 21
EEPROM ..................................................................................... 21
Serial Bus Interface..................................................................... 22
SMBus Protocols for RAM and EEPROM.............................. 24
Write Operations........................................................................ 24
Read Operations......................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/11—Revision 0: Initial Version

ADM1168
Rev. 0 | Page 3 of 28
DETAILED BLOCK DIAGRAM
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
DEVICE
CONTROLLER
OSC
EEPROM
SDA SCL A1 A0
SMBus
INTERFACE
ADM1168
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDOGND
PDO3
GND
PDO4
PDO5
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO6
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO8
SEQUENCING
ENGINE
VX2
VX3
VP2
VP3
VH
VP1
VX1
AGND
VX4
VDD
ARBITRATOR
VCCP
REG 5.25V
CHARGE PUMP
REFOUT REFGND
VREF
VDDCAP
09474-002
FAULT
RECORDING
Figure 2. Detailed Block Diagram

ADM1168
Rev. 0 | Page 4 of 28
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx 3.0 V Minimum supply required on one of the VH, VPx pins
VPx 6.0 V Maximum VDDCAP = 5.1 V typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
CVDDCAP 10 μF Minimum recommended decoupling capacitance
POWER SUPPLY
Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO8 off
Additional Currents
All PDOx FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO8 off
Current Available from VDDCAP 2 mA Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPx Pins
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VXx Pins
Input Impedance 1 MΩ
Detection Ranges
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 % Internal reference VREF error + DAC nonlinearity +
comparator offset error
Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current
0.25 mV Sinking current
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC

ADM1168
Rev. 0 | Page 5 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 μA
10.5 12 13.5 V IOH = 1 μA
IOUTAVG 20 μA 2 V < VOH < 7 V
Standard (Digital Output) Mode
(PDO1 to PDO8)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V
PU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
VOL 0 0.50 V IOL = 20 mA
IOL220 mA Maximum sink current per PDO pin
ISINK260 mA Maximum total sink for all PDO pins
RPULL-UP 16 20 29 kΩ Internal pull-up
ISOURCE (VPx)22 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
Three-State Output Leakage Current 10 μA VPDO = 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current,
IPULL-DOWN
20 μA VDDCAP = 4.75 V, TA= 25°C, if known logic state is required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL20.4 V IOUT = −3.0 mA
SERIAL BUS TIMING See Figure 27
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 1.3 μs
Start Setup Time, tSU;STA 0.6 μs
Stop Setup Time, tSU;STO 0.6 μs
Start Hold Time, tHD;STA 0.6 μs
SCL Low Time, tLOW 1.3 μs
SCL High Time, tHIGH 0.6 μs
SCL, SDA Rise Time, tr300 ns
SCL, SDA Fall Time, tf300 ns
Data Setup Time, tSU;DAT 100 ns
Data Hold Time, tHD;DAT 250 ns
Input Low Current, IIL 1 μA VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2Specification is not production tested but is supported by characterization data at initial product release.

ADM1168
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFOUT Pin 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND,
REFGND Pins
−0.3 V to +0.3 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
LeadTemperature, Soldering Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
32-Lead LQFP 54 °C/W
ESD CAUTION

ADM1168
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
12
25
32
8
9
17
16
4
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
GND VDDCAP SDA SCL A1 A0 VCCP PDOGN
D
AGND
REFGND
NC
REFOUT
NC NC NC NC
PIN 1
INDICATOR
ADM1168
TOP VIEW
(Not to Scale)
09474-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 VX1 to VX4 High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
5 to 7 VP1 to VP3 Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to these pins, the output of which connects to a supply fault detector.
These pins allow thresholds from 2.5 V to 6 V, from 1.25 V to 3 V, and from 0.573 V to 1.375 V.
8 VH High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to this pin, the output of which connects to a supply fault detector.
This pin allows thresholds from 6 V to 14.4 V and from 2.5 V to 6 V.
9 AGND1Ground Return for Input Attenuators.
10 REFGND1Ground Return for On-Chip Reference Circuits.
11, 13 to 16 NC No Connect.
12 REFOUT
Reference Output, 2.048 V. Note that a capacitor must always be connected between this pin and REFGND.
A 10 μF capacitor is recommended for this purpose.
17 to 24 PDO8 to PDO1 Programmable Output Drivers.
25 PDOGND1Ground Return for Output Drivers.
26 VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and
GND. A 10 μF capacitor is recommended for this purpose.
27 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
28 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
29 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
30 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
31 VDDCAP
Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a typical of 4.75 V.
A capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for
this purpose.
32 GND1Supply Ground.
1In a typical application, all ground pins are connected together.

ADM1168
Rev. 0 | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
6
0
1
2
3
4
5
0654321
V
VP1
(V)
V
VDDCAP
(V)
09474-050
Figure 4. VVDDCAP vs. VVP1
6
0
1
2
3
4
5
011412108642
V
VH
(V)
V
VDDCAP
(V)
6
09474-051
Figure 5. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0123456
V
VP1
(V)
I
VP1
(mA)
09474-052
Figure 6. IVP1 vs. VVP1 (VP1 as Supply)
180
160
140
120
100
80
60
40
20
0
0123456
V
VP1
(V)
I
VP1
(µA)
09474-053
Figure 7. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
011412108642
V
VH
(V)
I
VH
(mA)
6
09474-054
Figure 8. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
0
0654321
V
VH
(V)
I
VH
(µA)
09474-055
Figure 9. IVH vs. VVH (VH Not as Supply)

ADM1168
Rev. 0 | Page 9 of 28
14
12
10
8
6
4
2
0
0 15.012.510.07.55.02.5
I
LOAD
(µA)
CHARGE-PUMPED V
PDO1
(V)
09474-056
Figure 10. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0654321
I
LOAD
(mA)
V
PDO1
(V)
VP1 = 5V
VP1 = 3V
09474-057
Figure 11. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
065040302010
I
LOAD
(µA)
V
PDO1
(V)
0
VP1 = 5V
VP1 = 3V
09474-058
Figure 12. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD
2.058
2.038
2.043
2.048
2.053
–40 –20 0 20 40 60 10080
TEMPERATURE (°C)
REFOUT (V)
VP1 = 3.0V
VP1 = 4.75V
09474-061
Figure 13. REFOUT vs. Temperature

ADM1168
Rev. 0 | Page 10 of 28
POWERING THE ADM1168
The ADM1168 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep
it operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of four low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss
with this architecture (~0.2 V), resulting in the ability to power
the ADM1168 from a supply as low as 3.0 V. Note that the supply
on the VXx pins cannot be used to power the device.
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 14. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns off
so that it does not pull VDD down. The VDD capacitor can then
act as a reservoir to keep the device active until the next highest
supply takes over the powering of the device. A 10 μF capacitor is
recommended for this reservoir/decoupling function.
The value of the VDDCAP capacitor may be increased if it is
necessary to guarantee a complete fault record is written into
EEPROM should all supplies fail. The value of the capacitor to
use is discussed in the Black Box Writes with No External
Supply section.
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1168 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1168 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller or RC filter
network, should be taken to protect the device from transients
that may cause damage during hot swap events.
When two or more supplies are within 100 mV of each other, the
supply that first takes control of VDD keeps control. For example, if
VP1 is connected to a 3.3 V supply, VDD powers up to approximately
3.1 V through VP1. If VP2 is then connected to another 3.3 V
supply, VP1 still powers the device, unless VP2 goes 100 mV
higher than VP1.
SUPPLY
COMPARATOR
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
VH
VP3
VP2
VP1
V
DDCAP
INTERNAL
DEVICE
SUPPLY
09474-022
Figure 14. VDD Arbitrator Operation

ADM1168
Rev. 0 | Page 11 of 28
INPUTS
SUPPLY SUPERVISION
The ADM1168 has eight programmable inputs. Four of these
are dedicated supply fault detectors (SFDs). These dedicated
inputs are called VH and VPx (VP1 to VP3) by default. The
other four inputs are labeled VXx (VX1 to VX4) and have dual
functionality. They can be used either as SFDs, with functionality
similar to the VH and VPx, or as CMOS-/TTL-compatible logic
inputs to the device. Therefore, the ADM1168 can have up to
eight analog inputs, a minimum of four analog inputs and four
digital inputs, or a combination thereof. If an input is used as
an analog input, it cannot be used as a digital input. Therefore, a
configuration requiring eight analog inputs has no available
digital inputs. Table 6 shows the details of each input.
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1168 can have up to eight SFDs on its eight input
channels. These highly programmable reset generators enable
the supervision of up to eight supply voltages. The supplies can
be as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
drops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value), or an out-of-
window fault (the input voltage is outside a preprogrammed
range). The thresholds can be programmed to an 8-bit resolution
in registers provided in the ADM1168. This translates to a
voltage resolution that is dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 5. Voltage Range Limits
Voltage Range (V) VB(V) VR(V)
0.573 to 1.375 0.573 0.802
1.25 to 3.00 1.25 1.75
2.5 to 6.0 2.5 3.5
6.0 to 14.4 6.0 8.4
The threshold value required is given by
VT= (VR× N)/255 + VB
where:
VTis the desired threshold voltage (undervoltage or overvoltage).
VRis the voltage range.
Nis the decimal value of the 8-bit code.
VBis the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N= 255 × (VT− VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as described in the AN-721 Application Note) is given by
N= 255 × (5 − 2.5)/3.5
Therefore, N= 182 (1011 0110 or 0xB6).

ADM1168
Rev. 0 | Page 12 of 28
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 16 are always
monitoring VPx. To avoid chatter (multiple transitions when the
input is very close to the set threshold level), these comparators
have digitally programmable hysteresis. The hysteresis can be
programmed up to the values shown in Tabl e 6.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
The hysteresis value is given by
VHYST = VR× NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6 .
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
which allows the user to remove any spurious transitions such
as supply bounce at turn-on. The glitch filter function is in addition
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulse
appearing on the input of the glitch filter block that is less than
100 μs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 μs
appears on the output of the glitch filter block. The output is
delayed with respect to the input by 100 μs. The filtering process is
shown in Figure 15.
t
0
t
GF
t
0
t
GF
t
0
t
GF
t
0
t
GF
INPUT
INPUT PULSE SHORTE
R
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGE
R
THAN GLITCH FILTER TIMEOUT
OUTPUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
OUTPUT
09474-024
Figure 15. Input Glitch Filter Function
+
–
+
–
UV
COMPARATOR
VREF
FAULT TYPE
SELECT
OV
COMPARATOR
FAULT
OUTPUT
GLITCH
FILTER
VPx
MID
LOW
RANGE
SELECT
ULTRA
LOW
09474-023
Figure 16. Supply Fault Detector Block
Table 6. Input Functions, Thresholds, and Ranges
Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (μs)
VH High voltage analog input 2.5 to 6.0 425 mV 13.7 0 to 100
6.0 to 14.4 1.02 V 32.9 0 to 100
VPx Positive analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXx High-Z analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital input 0 to 5.0 Not applicable Not applicable 0 to 100

ADM1168
Rev. 0 | Page 13 of 28
SUPPLY SUPERVISION WITH VXx INPUTS
The VXx inputs have two functions. They can be used as either
supply fault detectors or as digital logic inputs. When selected as
analog (SFD) inputs, the VXx pins have functionality that is very
similar to the VH and VPx pins. The primary difference is that the
VXx pins have only one input range: 0.573 V to 1.375 V. Therefore,
these inputs can directly supervise only the very low supplies.
However, the input impedance of the VXx pins is high, allowing
an external resistor divide network to be connected to the pin.
Thus, potentially any supply can be divided down into the input
range of the VXx pin and supervised. This enables the ADM1168
to monitor other supplies, such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXx pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedicated
analog inputs, VPx and VH. The analog function of VX1 is mapped
to VP1, VX2 is mapped to VP2, and so on. VX4 is mapped to
VH. In this case, these SFDs can be viewed as secondary or
warning SFDs.
The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be generated
on a single supply using only one pin. For example, if VP1 is set
to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can be
set to output a warning at 3.1 V. Warning outputs are available
for readback from the status registers. They are also OR’ed together
and fed into the SE, allowing warnings to generate interrupts on
the PDOs. Therefore, in this example, if the supply drops to 3.1 V, a
warning is generated, and remedial action can be taken before
the supply drops out of tolerance.
VXx PINS AS DIGITAL INPUTS
As described in the Supply Supervision with VXX Inputs section,
the VXx input pins on the ADM1168 have dual functionality.
The second function is as a digital logic input to the device.
Therefore, the ADM1168 can be configured for up to four digital
inputs. These inputs are TTL-/CMOS-compatible inputs. Standard
logic signals can be applied to the pins: RESET from reset generators,
PWRGD signals, fault flags, manual resets, and more. These
signals are available as inputs to the SE and, therefore, can be used
to control the status of the PDOs. The inputs can be configured
to detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block, when the logic transition is detected. The
width is programmable from 0 μs to 100 μs.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This function enables the user to ignore
spurious transitions on the inputs. For example, the filter can be
used to debounce a manual reset switch.
When configured as digital inputs, each VXx pin has a weak
(10 μA) pull-down current source available for placing the input
into a known condition, even if left floating. The current source,
if selected, weakly pulls the input to GND.
DETECTOR
VXx
(DIGITAL INPUT)
GLITCH
FILTER
DIGITIAL THRESHOLD = 1.4V
TO
SEQUENCING
ENGINE
+
–
09474-027
Figure 17. VXx Digital Input Function

ADM1168
Rev. 0 | Page 14 of 28
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1168 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is taken with the
PDOs, based on the condition of the ADM1168 inputs. Therefore,
the PDOs can be set up to assert when the SFDs are in tolerance,
the correct input signals are received on the VXx digital pins,
and no warnings are received from any of the inputs of the device.
The PDOs can be used for a variety of functions. The primary
function is to provide enable signals for LDOs or dc-to-dc
converters that generate supplies locally on a board. The PDOs
can also be used to provide a PWRGD signal when all the SFDs
are in tolerance or a RESET output if one of the SFDs goes out
of specification (this can be used as a status signal for a DSP, FPGA,
or other microcontroller).
The PDOs can be programmed to pull up to a number of different
options. The outputs can be programmed as follows:
•Open drain (allowing the user to connect an external pull-up
resistor)
•Open drain with weak pull-up to VDD
•Open drain with strong pull-up to VDD
•Open drain with weak pull-up to VPx
•Open drain with strong pull-up to VPx
•Strong pull-down to GND
•Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only)
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external NFET, which is used to isolate, for example, a card-side
voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOxCFG configuration
register (see the AN-721 Application Note for details).
The data sources are as follows:
•Output from the SE.
•Directly from the SMBus. A PDO can be configured so the
SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
•On-chip clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It
can be used, for example, to clock an external device such
as an LED.
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1168
device from the factory are set to 0. Because of this, the PDOx pins
are pulled to GND by a weak (20 kΩ), on-chip, pull-down resistor.
As the input supply to the ADM1168 ramps up on VPx or VH,
all PDOx pins behave as follows:
•Input supply = 0 V to 1.2 V. PDOs high impedance.
•Input supply = 1.2 V to 2.7 V. PDOs pulled to GND by a
weak (20 kΩ), on-chip, pull-down resistor.
•Supply > 2.7 V. Factory programmed devices continue to pull
all PDOs to GND by a weak (20 kΩ), on-chip, pull-down
resistor. Programmed devices download current EEPROM
configuration data, and the programmed setup is latched. The
PDO then goes to the state demanded by the configuration,
providing a known condition for the PDOs during power-up.
The internal pull-down can be overdriven with an external pull-up
of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor
value is given by
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
PDO
SE DATA
CFG4 CFG5 CFG6
SMBus DATA
CLK DATA
10Ω
20kΩ
10Ω
20kΩ
VP1
SEL
VP4
10Ω
20kΩ
V
DD
V
FET (PDO1 TO PDO6 ONLY)
20kΩ
09474-028
Figure 18. Programmable Driver Output

ADM1168
Rev. 0 | Page 15 of 28
SEQUENCING ENGINE
OVERVIEW
The ADM1168 SE provides the user with powerful and flexible
control of sequencing. The SE implements a state machine control
of the PDO outputs with state changes conditional on input
events. SE programs can enable complex control of boards such
as power-up and power-down sequence control, fault event
handling, and interrupt generation on warnings. A watchdog
function that verifies the continued operation of a processor
clock can be integrated into the SE program. The SE can also be
controlled via the SMBus, giving software or firmware control
of the board sequencing.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
•It monitors signals indicating the status of the eight input
pins, VP1 to VP3, VH, and VX1 to VX4.
•It can be entered from any other state.
•Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
•Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
•The output condition of the eight PDO pins is defined and
fixed within a state.
•It can transition from one state to the next in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
•It can trigger a write of the black box fault and status
registers into the black box section of EEPROM.
SEQUENCE
TIMEOUT
MONITOR
FAULT STATE
09474-029
Figure 19. State Cell
The ADM1168 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or
when the secondary voltage monitors on VPx and VH are
triggered. The warnings are OR’ed together and are available
as a single warning input to each of the three blocks that enable
exiting a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state unconditionally.
This enables the user to force the SE to advance. Examples of the
use of this feature include moving to a margining state or debugging
a sequence. The SMBus jump or go-to command can be seen as
another input to sequence and timeout blocks to provide an exit
from each state.
Table 7. Sample Sequence State Entries
State Sequence Timeout Monitor
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP1 is not okay, go to State IDLE1.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms,
go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
DIS2V5 If VX1 is high, go to State IDLE1.
FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.
FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1.
PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.

ADM1168
Rev. 0 | Page 16 of 28
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 21 shows how the simple building block of a single
SE state can be used to build a power-up sequence for a three-
supply system. Table 8 lists the PDO outputs for each state in
the same SE implementation. In this system, a good 5 V supply
on the VP1 pin and the VX1 pin held low are the triggers required
to start a power-up sequence. The sequence next turns on the 3.3 V
supply, then the 2.5 V supply (assuming successful turn on of the
3.3 V supply). When all three supplies have turned on correctly,
the PWRGD state is entered, where the SE remains until a fault
occurs on one of the three supplies or until it is instructed to go
through a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 21 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 20 is a block diagram
of the sequence detector.
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX4
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
09474-032
Figure 20. Sequence Detector Block Diagram
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 21, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES
TIMEOUT
STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
(VP1 +
VP2) = 0
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
09474-030
Figure 21. Sample Application Flow Diagram
Table 8. PDO Outputs for Each State
PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1

ADM1168
Rev. 0 | Page 17 of 28
Monitoring Fault Detector
The monitoring fault detector block is used to detect a failure on an
input. The logical function implementing this is a wide OR gate
that can detect when an input deviates from its expected condition.
The clearest demonstration of the use of this block is in the
PWRGD state, where the monitor block indicates that a failure
on one or more of the VPx, VXx, or VH inputs has occurred.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device needs to react as
quickly as possible. Some latency occurs when moving out of this
state, however, because it takes a finite amount of time (~20 μs) for
the state configuration to download from the EEPROM into the
SE. Figure 22 is a block diagram of the monitoring fault detector.
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
V
P1
V
X4
MONITORING FAULT
DETECTOR
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
1-BIT FAULT
DETECTOR
FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
09474-033
Figure 22. Monitoring Fault Detector Block Diagram
Timeout Detector
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 21, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply.
This supply rail is connected to the VP2 pin, and the sequence
detector looks for the VP2 pin to go above its undervoltage
threshold, which is set in the supply fault detector (SFD) attached
to that pin.
The power-up sequence progresses when this change is detected. If,
however, the supply fails (perhaps due to a short circuit overloading
this supply), the timeout block traps the problem. In this example,
if the 3.3 V supply fails within 10 ms, the SE moves to the DIS3V3
state and turns off this supply by bringing PDO1 low. It also
indicates that a fault has occurred by taking PDO3 high. Timeout
delays of 100 μs to 400 ms can be programmed.
FAULT AND STATUS REPORTING
The ADM1168 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
The fault register can be enabled or disabled in each state. To
latch data from one state, ensure that the fault latch is disabled
in the following state. This ensures that only real faults are
captured and not, for example, undervoltage conditions that
may be present during a power-up or power-down sequence.
The ADM1168 also has a number of status registers. These include
more detailed information, such as whether an undervoltage or
overvoltage fault is present on a particular input. The status
registers also include information on ADC limit faults.
There are two sets of these registers with different behaviors.
The first set of status registers is not latched in any way and,
therefore, can change at any time in response to changes on the
inputs. These registers provide information such as the UV and
OV state of the inputs, the digital state of the GPI VXx inputs,
and the ADC warning limit status.
The second set of registers update each time the sequence engine
changes state and are latched until the next state change. The
second set of registers provides the same information as the first
set, but in a more compact form. The reason for this is that these
registers are used by the black box feature when writing status
information for the previous state into EEPROM.
See the AN-721 Application Note for full details about the
ADM1168 registers.
NONVOLATILE BLACK BOX FAULT RECORDING
A section of EEPROM, from Address 0xF900 to Address 0xF9FF, is
provided that by default can be used to store user-defined settings
and information. Part of this section of EEPROM, Address 0xF980
to Address 0xF9FF, can instead be used to store up to 16 fault records.
Any sequencing engine state can be designated as a black box write
state. Each time the sequence engine enters that state, a fault record
is written into EEPROM. The fault record provides a snapshot of
the entire ADM1168 state at the point in time when the last state
was exited, just prior to entering the designated black box write
state. A fault record contains the following information:
•A flag bit set to 0 after the fault record has been written.
•The state number of the previous state prior to the fault
record write state.
•Did a sequence, timeout, or monitor condition cause the
previous state to exit?
•UVSTATx and OVSTATx input comparator status.
•VXx GPISTAT status.
•LIMSTATx status.
•A checksum byte.

ADM1168
Rev. 0 | Page 18 of 28
Each fault record contains eight bytes, with each byte taking
typically about 250 μs to write to EEPROM, for a total write
time of about 2 ms. After the black box begins to write a fault
record into EEPROM, the ADM1168 ensures that it is complete
before attempting to write any additional fault records. This means
that if consecutive sequencing engine states are designated as
black box write states, then a time delay must be used in the first
state to ensure that the fault record is written before moving to
the next state.
When the ADM1168 powers on initially, it performs a search
to find the first fault record that has not been written to. It does
this by checking the flag bit in each fault record until it finds
one where the flag bit is 1. The first fault record is stored at
Address 0xF980, and at multiples of eight bytes after that, with
the last record stored at Address 0xF9F8.
The fault recorder is only able to write in the EEPROM. It is not able
to erase the EEPROM prior to writing the fault record. Therefore,
to ensure correct operation, it is important that the fault record
EEPROM is erased prior to use. When all the EEPROM locations
for the fault records are used, no more fault records are written.
This ensures that the first fault in any cascading fault is stored and
not overwritten and lost.
To avoid the fault recorder filling up and fault records being lost, an
application can periodically poll the ADM1168 to determine if there
are fault records to be read. Alternatively, one of the PDOx outputs
can be used to generate an interrupt for a processor in the fault
record write state to signal the need to come and read one or more
fault records.
After reading fault records during normal operation, two things
must be done before the fault recorder will be able to reuse the
EEPROM locations. First, the EEPROM section must be erased.
The fault recorder must then be reset so that it performs its search
again for the first unused location of EEPROM that is available to
store a fault record.
BLACK BOX WRITES WITH NO EXTERNAL SUPPLY
In cases where all the input supplies fail, for example, if the card
has been removed from a powered backplane, the state machine
can be programmed to trigger a write into the black box EEPROM.
The decoupling capacitors on the rail that power the ADM1168
and other loads on the board form an energy reservoir. Depending
on the other loads on the board and their behavior as the supply
rails drop, there may be sufficient energy in the decoupling
capacitors to allow the ADM1168 to write a complete fault record
(eight bytes of data).
Typically, it takes 2 ms to write to the eight bytes of a fault record. If
the ADM1168 is powered using a 12 V supply on the VH pin, then
a UV threshold at 6 V can be set and used as the state machine
trigger to start writing a fault record to EEPROM. The higher the
threshold is, the earlier the black box write begins, and the more
energy available in the decoupling capacitors to ensure it completes
successfully.
Provided the VH supply, or another supply connected to a VPx pin,
remains above 3.0 V during the time to write, the entire fault record
is always written to the EEPROM. In many cases, there should be
sufficient decoupling capacitors on a board to power the
ADM1168 as it writes into the EEPROM.
In cases where the decoupling capacitors are not able to supply
sufficient energy after the board is removed to ensure a complete
fault record is written, the value of the capacitor on VDDCAP
may be increased. In the worst case, assuming that no energy is
supplied to the ADM1168 by the external decoupling capacitors,
but that VDDCAP has 4.75 V on it, then a 47 μF is sufficient to
guarantee that a single complete black box record can be written
to the EEPROM.

ADM1168
Rev. 0 | Page 19 of 28
APPLICATIONS DIAGRAM
3.3V OUT
VH
PDO8
PDO7
SIGNAL VALID
PDO6
PDO2
PDO1
PDO5
PDO4
PDO3
EN OUT
DC-TO-DC1
IN
3.3V OUT
3V OUT
5V OUT
12V OUT
EN OUT
DC-TO-DC2
IN
1.25V OUT
EN OUT
DC-TO-DC3
IN
EN OUT
LDO
IN
1.25V OUT
0.9V OUT
12V IN
5V IN
3V IN
5V OUT VP1
3V OUT VP2
3.3V OUT VP3
1.25V OUT VX1
1.2V OUT VX2
0.9V OUT VX3
VX4
10µF
VCCP
10µF
REFOUT
10µF
VDDCAP GND
ADM1168
PWRGD
RESET
09474-068
Figure 23. Applications Diagram

ADM1168
Rev. 0 | Page 20 of 28
COMMUNICATING WITH THE ADM1168
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1168 (undervoltage/overvoltage
thresholds, glitch filter timeouts, and PDO configurations) is
dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the
device. The latches are double-buffered and have two identical
latches, Latch A and Latch B. Therefore, when an update to a
function occurs, the contents of Latch A are updated first, and
then the contents of Latch B are updated with identical data.
The advantages of this architecture are explained in detail in
the Updating the Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs in
steps, as follows:
1. With no power applied to the device, the PDOs are all high
impedance.
2. When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly
pulled to GND with a 20 kΩ resistor.
3. When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads its contents to all Latch As.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6. At 0.5 ms after the configuration download completes,
the first state definition is downloaded from EEPROM
into the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1168 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1168, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one
of the PDOs.
The ADM1168 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to
the RAM across the SMBus, and the configuration is updated
immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1168 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM contents
to the RAM registers. With this method, the configuration of the
ADM1168 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in the Option 3
section is also a useful way to restore the original EEPROM
contents if revisions to the configuration are unsatisfactory. For
example, if the user needs to alter an overvoltage threshold, the
RAM register can be updated, as described in the Option 1
section. However, if the user is not satisfied with the change and
wants to revert to the original programmed value, the device
controller can issue a command to download the EEPROM
contents to the RAM again, as described in the Option 3
section, restoring the ADM1168 to its original configuration.
The topology of the ADM1168 makes this type of operation
possible. The local, volatile registers (RAM) are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to leaves the
double buffered latches open at all times, allowing the registers
to be updated continuously as they are written to. If Bit 0 is set
to 0 when a RAM write occurs across the SMBus, only the first
side of the double-buffered latch is written to. The user must
then write a 1 to Bit 1 of the UPDCFG register. This generates a
pulse to update all the second latches at once. EEPROM writes
occur in a similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page
can all be set to 1. If this bit is set low, the contents of a page
cannot be erased, even if the command code for page erasure is
programmed across the SMBus. The bit map for the UPDCFG
register is shown in the AN-721 Application Note. A flow diagram
for download at power-up and subsequent configuration updates is
shown in Figure 24.