APPOTECH CW6632B User manual
CW6632B
Bluetooth 3.0 Audio Player SOC
User Manual
[CW6632B-UM-EN]
Versions: 1.0.0
Release Date: 2015-8-25
II Table of content
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved
Table of content
Table of content ........................................................................................................................................ II
1Product Overview.............................................................................................................................. 1
1.1 Outline........................................................................................................................................ 1
1.2 Features...................................................................................................................................... 1
1.3 Applications:............................................................................................................................... 2
1.4 System Architecture................................................................................................................... 2
2Pin Definitions ................................................................................................................................... 3
2.1 CW6632B.................................................................................................................................... 3
2.1.1 Package............................................................................................................................... 3
2.1.2 Pin Assignment ................................................................................................................... 3
2.1.3 Pin Description.................................................................................................................... 3
3CPU Core Information ....................................................................................................................... 6
3.1 Architecture ............................................................................................................................... 6
3.2 Instruction Set ............................................................................................................................ 6
3.3 Memory Mapping ...................................................................................................................... 9
3.3.1 Program Memory Mapping ................................................................................................ 9
3.3.2 External Data Memory Mapping ...................................................................................... 10
3.3.3 Internal Data Memory Mapping....................................................................................... 10
3.4 Interrupt Processing................................................................................................................. 11
3.4.1 Interrupt sources .............................................................................................................. 11
3.4.2 Interrupt Priority............................................................................................................... 13
3.5 Special Function Register Mapping (SFR)................................................................................. 13
3.6 Extend Special Function Registers Mapping (XSFR) ................................................................. 14
3.7 CPU and Memory related SFR Description .............................................................................. 15
4Reset Generation............................................................................................................................. 25
4.1 Power-on Reset (POR).............................................................................................................. 25
4.2 System Reset ............................................................................................................................ 25
4.2.1 LVD.................................................................................................................................... 26
Table of content
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
4.2.2 RTCC Reset........................................................................................................................ 27
4.2.3 Watchdog Reset ............................................................................................................... 27
4.2.4 Port Wakeup Reset........................................................................................................... 28
4.3 Clock System ............................................................................................................................ 28
4.3.1 Clock Control .................................................................................................................... 28
4.3.2 Clock Gating...................................................................................................................... 34
4.3.3 Phase Lock Loop (PLL)....................................................................................................... 34
5Low Power Management ................................................................................................................ 39
5.1 Power Saving Mode ................................................................................................................. 39
5.1.1 BSleep Mode....................................................................................................................... 39
5.1.2 Hold Mode........................................................................................................................ 39
5.1.3 Idle Mode.......................................................................................................................... 39
5.1.4 Power Down Mode........................................................................................................... 40
5.2 Power Supply............................................................................................................................ 40
6General Purpose Input/Output (GPIO)............................................................................................ 44
6.1 Overview .................................................................................................................................. 44
6.2 Features.................................................................................................................................... 44
6.3 Function multiplexing............................................................................................................... 44
6.4 Port interrupt and wakeup....................................................................................................... 46
6.5 GPIO Special Function Registers .............................................................................................. 46
6.5.1 149Bwakeup registers .............................................................................................................. 60
6.6 Operation Guide....................................................................................................................... 61
7Timers.............................................................................................................................................. 62
7.1 Timer0 ...................................................................................................................................... 62
7.1.1 Timer0 Features................................................................................................................ 62
7.1.2 Timer0 Special Function Registers.................................................................................... 62
7.2 Timer1 ...................................................................................................................................... 63
7.2.1 Timer1 Features................................................................................................................ 63
7.2.2 Timer1 Special Function Registers.................................................................................... 64
IV Table of content
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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7.3 Timer2 ...................................................................................................................................... 65
7.3.1 Timer2 Features................................................................................................................ 66
7.3.2 Timer2 Special Function Registers.................................................................................... 66
7.4 Timer3 ...................................................................................................................................... 68
7.4.1 Timer3 Features................................................................................................................ 68
7.4.2 Timer3 Special Function Registers.................................................................................... 68
7.5 Watchdog Timer (WDT) ........................................................................................................... 69
7.5.1 Watchdog Wake up .......................................................................................................... 69
7.5.2 Watchdog SFR................................................................................................................... 70
8Universal Asynchronous Receiver/Transmitter (UART) .................................................................. 71
8.1 UART0....................................................................................................................................... 71
8.1.1 Overview........................................................................................................................... 71
8.1.2 UART0 Special Function Registers .................................................................................... 71
8.2 UART1....................................................................................................................................... 73
8.2.1 Overview........................................................................................................................... 73
8.2.2 UART1 Special Function Registers .................................................................................... 73
8.3 Operation Guide....................................................................................................................... 77
8.4 BT Control Register .................................................................................................................. 79
9IR receiver........................................................................................................................................ 80
9.1 IR frame format........................................................................................................................ 80
9.2 IR Receiver Control Registers ................................................................................................... 81
9.3 IR Receiver Operation Guide.................................................................................................... 83
10 SPI .................................................................................................................................................... 84
10.1 SPI0........................................................................................................................................... 84
10.1.1 SPI0 Special Function Registers ........................................................................................ 85
10.1.2 SPI0 Operation Guide ....................................................................................................... 86
10.2 SPI1........................................................................................................................................... 87
10.2.1 SPI1 Special Function Registers ........................................................................................ 88
10.2.2 SPI1 Operation Guide ....................................................................................................... 90
Table of content
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved.
11 External Memory Interface (EMI).................................................................................................... 91
11.1 EMI Control Registers............................................................................................................... 91
12 SD Card Host Controller (SDC)......................................................................................................... 94
12.1 Features.................................................................................................................................... 94
12.2 IO Mapping............................................................................................................................... 94
12.3 SDC Special Function Registers ................................................................................................ 94
12.4 SDC Operation Guide ............................................................................................................... 97
12.4.1 206Bcommand Operation ........................................................................................................ 97
12.4.2 207Bdata Operation ................................................................................................................. 98
13 Audio Terminal (DAC)...................................................................................................................... 99
13.1 Features.................................................................................................................................... 99
13.2 DAC Special Function Registers................................................................................................ 99
13.2.1 DAC Register Mapping...................................................................................................... 99
13.2.2 Function of DAC Control Registers ................................................................................. 100
13.3 Operation Guide..................................................................................................................... 104
13.3.1 BDAC Operation Guide ................................................................................................... 104
14 SARADC.......................................................................................................................................... 105
14.1 Features.................................................................................................................................. 105
14.2 ADC Pin Mapping.................................................................................................................... 105
14.3 SARADC Special Function Registers........................................................................................ 105
15 CRC16 /LFSR16/LFSR32 ................................................................................................................. 108
15.1 CRC16 ..................................................................................................................................... 108
15.1.1 Features.......................................................................................................................... 108
15.1.2 CRC16 Special Function Registers................................................................................... 108
15.2 LFSR16 .................................................................................................................................... 109
15.2.1 Features.......................................................................................................................... 109
15.2.2 LFSR16 Special Function Register ................................................................................... 109
15.3 LFSR32 .................................................................................................................................... 110
15.3.1 Features.......................................................................................................................... 110
VI Table of content
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright © 2015, www.appotech.com. All Rights Reserved
15.3.2 LFSR32 Special Function Registers.................................................................................. 110
16 Integrated Interchip Sound (IIS) .................................................................................................... 111
16.1 Features.................................................................................................................................. 111
16.2 IIS Special Function Register .................................................................................................. 111
16.3 Operation Guide..................................................................................................................... 118
16.3.1 CPU RD/WR..................................................................................................................... 118
16.3.2 loop................................................................................................................................. 118
16.3.3 DMA mode...................................................................................................................... 119
17 PolyFuse control ............................................................................................................................ 120
17.1 PF Special Function Register .................................................................................................. 120
17.2 PF user guideline .................................................................................................................... 121
18 Characteristics ............................................................................................................................... 122
18.1 PMU Parameters .................................................................................................................... 122
18.2 CORE PLL Parameters............................................................................................................. 122
18.3 General purpose I/O Parameters ........................................................................................... 122
18.4 Audio ADDA Parameters ........................................................................................................ 123
18.5 USB PHY Parameters .............................................................................................................. 123
18.6 RF Analog Blocks .................................................................................................................... 123
19 Package Outline Dimensions ......................................................................................................... 125
19.1 SSOP28 ................................................................................................................................... 125
Revision History.......................................................................................................................................... i
1 Product Overview 1
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
1Product Overview
1.1 Outline
CW6632B is a highly integrated system on chip for Bluetooth v3.0 with Enhanced Data Rate (EDR). This SOC is
backward-compatible with Bluetooth 2.1, 2.0 and 1.2 systems. The Bluetooth chip supports a data rate of
1M/2M/3Mbps. It has SSOP28 packaging, stereo audio output with AUX input, and external flash. It integrates an
abundant amount of peripherals (full-duplex UART, SPI, SD, IIC (FM function)), and audio interface. In addition, this
SOC supports audio playback from SD, USB.
1.2 Features
Supports Bluetooth 3.0 + EDR; backward-compatible with BT 2.1+EDR and below;
Supports HFP 1.6, HSP 1.2, A2DP 1.3, AVCTP 1.4, AVDTP 1.3 and AVRCP 1.5;
Class 2 power level, RF Performance: Tx:0dBm, Rx: -80dBm;
Supports simple pairing and auto reconnection function;
High Performance 8051 at 48MHz;
Supports MP3/SBC decoder;
Supports two pairs of AUX;
Six Channels 10-bit SARADC;
Supports 16bit Stereo DAC with >90dB SNR, embedded with two class A/B headphone amplifier;
16bit Mono ADC with >90dB DR;
Supports Audio record function from MIC;
Supports Audio playback from SD/USB;
Keypad tone mixer;
Watchdog Timer with on-chip RC oscillator;
Supports full-duplex IIS, UART, SPI, SD interface;
Supports IIC interface for FM function;
2 channels 16 levels Low Voltage Detector;
Power on Reset;
Full speed USB 2.0 HOST/DEVICE controller/PHY;
Internal crystal oscillator support 26M crystal;
Internal LDO regulator:1.35V to 1.2V;4.2V to 3.3V;
Built-in buck converter,DC-DC:4.2V to 1.35V;
Supports Software Power On/Off, Deep Sleep mode, and Sniff mode;
2 1.3 Applications:
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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1.3 Applications:
Bluetooth MP3 Boombox
Bluetooth stereo headset
Bluetooth stereo speaker
Bluetooth audio communication equipment
1.4 System Architecture
Bluetooth Radio
Transceiver
RF Synthesizer
RF Rx Tx DAC
Rx ADCRF Tx
Bluetooth
Baseband Core
Peripherals & IOs
Watchdog
SARADC
Timer0-3 IIS
EMI
SDC
SPI0,1
USB Host
UART0,1 Port0-3
Clock
Management
Audio Acceleration Engine
Power
Management
Core
CPU RAM ROM
Audio Interface
PLL
Internal RC
Real Time
Clock
SMPC/LDO
POR/LVD
Battery
Charger
Headphone
&MIC
Amplifier
Audio ADC
Audio DAC
Huffman FFT/iFFT DSP
Frequency
Hopping
Generator
Slot Timing
Controller
Timing
Recovery
Encryption
/Decryptio
n Engine
Figure 1-1 CW6632B system architecture
2 Pin Definitions 3
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
2Pin Definitions
2.1 CW6632B
2.1.1 Package
SSOP28
2.1.2 Pin Assignment
Figure 2-1 shows the pin assignment of CW6632B.
CW6632B
SSOP28
V10
1
2
3
4
5
6
7
8
9
P21
10
11
12
13
14
MICN
MICP/VCM
AVSS
VDDHP
DACL
DACR
VCM_BUF/P01
P00
P13
P32
P31
P30
P14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
P07
PAD_VCC_IF/
VCC_RF/VCC_PA
RXTX
GND_ANT1
VCC_VCO/
PAD_VDDQ/VCC_XO
XO_P
XO_N
VBAT
VOUT1V5
VDDLDO
VDDIO/AVDD
USBDM
USBDP
P20
Figure 2-1 Pin Assignment of CW6632B
2.1.3 Pin Description
Table 2-1 shows the pin description of CW6632B.
Table 2-1 Pin Description of CW6632B
Pin No.SSOP28
Name
Type
Function
1
P21
I/O
GPIO
AUXR2
4 2.1 CW6632B
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Pin No.SSOP28
Name
Type
Function
ADC1
SDCLK
EMIDAT1
LCD_D1
2
MICN
A
MIC Negative input
3
MICP/VCM
A
MIC Positive input
DAC VCM output
4
AVSS
GND
Analog GND
5
VDDHP
PWR
Headphone power
6
DACL
A
DAC left output
GPIO input
7
DACR
A
DAC right output
GPIO input
8
P01/VCM_BUF
I/O
GPIO
AUXR0
UARTTX1
PORT INT/WKUP0
SDDAT2
DAC VCM buffer
9
P00
I/O
GPIO
AUXL0
UARTRX1
SDDAT1
SPI0DIN2
10
P13
I/O
GPIO
ADC5
IISBCLK0
11
P32
I/O
GPIO
SDDAT0
SPI0DOUT3/DIN3
12
P31
I/O
GPIO
SDCMD
SPI0DIN3
13
P30
I/O
GPIO
ADC4
SDCLK
SPI0CLK3
14
P14
I/O
GPIO
ADC2
SDDAT3
SPI0DOUT2
TMR3CAP/TMR3PWM
2 Pin Definitions 5
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Pin No.SSOP28
Name
Type
Function
IISDO0
15
P07
I/O
GPIO
PORTINT/WKUP3
Ir_input
TRM1CAP
16
PAD_VCC_IF/VCC_RF/VCC_PA
PWR
Power VCC
17
RXTX
A
RF Rx and Tx pin
18
GND_ANT1
GND
RF GND
19
VCC_VCO/VCC_XO/PAD_VDDQ
PWR
Power VCC/VDDQ
20
XO_P
A
BT 26MHz XOSC Positive Pin
21
XO_N
A
BT 26MHz XOSC Negative Pin
22
BVIN
PWR
PMU Power input Pin 4.2V(typ)
23
VOUT1V5
PWR
VOUT 1.5V
24
VDDLDO
PWR
LDO power input 4.2V(typ)
25
VDDIO/AVDD
PWR
Power output VDDIO 3.3V
26
USBDM
I/O
USB Negative Input/output
27
USBDP
I/O
USB Positive Input/output
28
P20
I/O
GPIO
AUXL2
SDCMD
EMIDAT0
LCD_D0
6 3.1 Architecture
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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3CPU Core Information
3.1 Architecture
The AXC51-CORE of CW6632B is fully compatible with the MCS-51TM instruction set.
The AXC51-CORE employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock
cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the AXC51-CORE executes
most of its instructions in 1 system clock cycle. With system clock running at 48 MHz, it has a peak throughput of 48
MIPS running in on-chip SRAM area.
3.2 Instruction Set
The instruction set of the AXC51-CORE is fully compatible with the standard MCS-51TM instruction set; standard
8051 development tools can be used to develop software for the AXC51-CORE. All instructions of AXC51-CORE
are the binary and functional equivalent of their MCS-51TM counterparts, including op-codes, addressing modes and
effect on PSW flags. However, instruction timing is different than that of the standard 8051. Table 3-1 shows
AXC51-CORE Instruction Set Summary
Table 3-1 AXC51-CORE Instruction Set Summary
Number of Bytes
Mnemonic
Operands
Clock Cycles (running in IRAM)
1
NOP
1
2
AJMP
code addr
3
3
LJMP
code addr
3
1
RR
A
1
1
INC
A
1
1
INC
data addr
1
1
INC
@Ri
1
1
INC
Rn
1
3
JBC
bit addr, code addr
1 or 3
2
ACALL
code addr
3
3
LCALL
code addr
3
1
RRC
A
1
1
DEC
A
1
2
DEC
data addr
1
1
DEC
@Ri
1
1
DEC
Rn
1
3
JB
bit addr, code addr
1 or 3
1
RET
4
1
RL
A
1
2
ADD
A, #data
1
3 CPU Core Information 7
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Number of Bytes
Mnemonic
Operands
Clock Cycles (running in IRAM)
2
ADD
A, data addr
1
1
ADD
A, @Ri
1
1
ADD
A, Rn
1
3
JNB
bit addr, code addr
1 or 3
1
RETI
4
1
RLC
A
1
2
ADDC
A, #data
1
2
ADDC
A, data addr
1
1
ADDC
A, @Ri
1
1
ADDC
A, Rn
1
2
JC
code addr
1 or 3
2
ORL
data addr, A
1
3
ORL
data addr, #data
1
2
ORL
A, #data
1
2
ORL
A, data addr
1
1
ORL
A, @Ri
1
1
ORL
A, Rn
1
2
JNC
code addr
1 or 3
2
ANL
data addr, A
1
2
ANL
data addr, #data
1
1
ANL
A, @Ri
1
1
ANL
A, Rn
1
2
JZ
code addr
1 or 3
2
XRL
data addr, A
1
3
XRL
data addr, #data
1
2
XRL
A, #data
1
2
XRL
A, data addr
1
1
XRL
A, @Ri
1
1
XRL
A, Rn
1
2
JNZ
code addr
1 or 3
2
ORL
C, bit addr
1
1
JMP
@A+DPTR
3
2
MOV
A, #data
1
3
MOV
data addr, #data
1
2
MOV
@Ri, #data
1
2
MOV
Rn, #data
1
2
SJMP
code addr
3
2
ANL
C, bit addr
1
1
MOVC*
A, @A+PC
1
1
DIV
AB
1
3
MOV
data addr, data addr
1
8 3.2 Instruction Set
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Number of Bytes
Mnemonic
Operands
Clock Cycles (running in IRAM)
2
MOV
data addr, @Ri
1
2
MOV
data addr, Rn
1
3
MOV
DPTR, #data
1
2
MOV
bit addr, C
1
1
MOVC*
A, @A+DPTR
2
2
SUBB
A, #data
1
2
SUBB
A, data addr
1
1
SUBB
A, @Ri
1
1
SUBB
A, Rn
1
2
ORL
C, bit addr
1
2
MOV
C, bit addr
1
1
INC
DPTR
1
1
MUL
AB
1
2
MOV
@Ri, data addr
1
2
MOV
Rn, data addr
1
2
ANL
C, bit addr
1
2
CPL
bit addr
1
2
CPL
C
1
3
CJNE
A, #data, code addr
1 or 3
3
CJNE
A, data addr, code addr
1 or 3
3
CJNE
@Ri, #data, code addr
1 or 3
3
CJNE
Rn, #data, code addr
1 or 3
2
PUSH
data addr
1
2
CLR
bit addr
1
1
CLR
C
1
1
SWAP
A
1
2
XCH
A, data addr
1
1
XCH
A, @Ri
1
1
XCH
A, Rn
1
2
POP
data addr
1
2
SETB
bit addr
1
1
SETB
C
1
1
DA
A
1
3
DJNZ
data addr, code addr
1 or 3
1
XCHD
A, @Ri
1
2
DJNZ
Rn, code addr
1 or 3
1
MOVX
A, @DPTR
2
1
MOVX
A, @Ri
2
1
CLR
A
1
2
MOV
A, data addr
1
1
MOV
A, @Ri
1
3 CPU Core Information 9
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Number of Bytes
Mnemonic
Operands
Clock Cycles (running in IRAM)
1
MOV
A, Rn
1
1
MOVX
@DPTR, A
1
1
MOVX
@Ri, A
1
1
CPL
A
1
2
MOV
data addr, A
1
1
MOV
@Ri, A
1
1
MOV
Rn, A
1
3.3 Memory Mapping
3.3.1 Program Memory Mapping
As illustrated in CW6632B program space is divided into 3 regions: SRAM1, SRAM2, and IROM.
0x0000
0xFFFF
CODE Space
SRAM2
SRAM1
IROM
0x6400
0x63FF
Figure 3-1 Program Memory Organization
10 3.3 Memory Mapping
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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3.3.2 External Data Memory Mapping
XFigure 3-2illustrated External Data Memory Mapping.
XDATA Space
0x0000
SRAM2
0x63FF
0x7FFF
0xFFFF
0x8000
0x9FFF
0xA000
SRAM1
Reserved
0x6400
256B Data RAM
SRAM0
Reserved
0x1FFF
0x1F00
Figure 3-2 External Data Memory Mapping
3.3.3 Internal Data Memory Mapping
Internal data memory locates in SRAM0 at the address from 0x9F00 to 0x9FFF as showed in XFigure 3-2Internal
data memory is mapped in XFigure 3-3. The memory space is shown divided into three blocks, which are generally
referred to as the Lower 128, the Upper 128, and SFR space.
3 CPU Core Information 11
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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Indirect addressing
only
Direct and Indirect
addressing
Direct addressing
00H
7FH
80H
FFH
Upper128
Lower128
SFR
FFH
80H
Figure 3-3 Internal data memory mapping
As shown in Figure 3-4 the Lowest 32 bytes in Lower 128 are grouped into 4 banks of 8 registers. Program
instructions call out these registers as R0 through R7. Two bits in the PSW select which register bank are in use.
00H 07H
08H 0FH
10H 1FH
18H 1FH
20H
2FH
7FH
00
01
10
11
BANK SELECT
BITS IN PSW
Reset value of SP
Bit addressable space
Figure 3-4 Lowest 32 bytes in Internal data memory Lower 128
3.4 Interrupt Processing
3.4.1 Interrupt sources
The CW6632B provides 15 interrupt sources. All interrupts are controlled by a series combination of individual
enable bits and a global enable (EA) in the interrupt-enable register (IE0.7). Setting EA to logic 1 allows individual
interrupts to be enabled. Setting EA to logic 0 disables all interrupts regardless of the individual interrupt-enable
settings. The interrupt enables and priorities are functionally identical to those of the 80C52.
The CW6632B provides 3 sets of vectors entry addresses, starting from 0x0003, 0x4003 and 0x8003. The vector
base address is set by DPCON [7:6]. Table 3-2lists the interrupt summary.
Table 3-2 Interrupt Summary
12 3.4 Interrupt Processing
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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Interrupt
Sources
Interrupt
Vector
Interrupt
Number
Natural
Order
Interrupt Flag
Interrupt
Enable Bit
Priority
Control Bit
SINT0
0x0003
0x4003
0x8003
0
1
SPMODE.7
IE0.0
IPH0.0
IP0.0
SINT1
AGC
0x000B
0x400B
0x800B
1
2
SPMODE.6
AGCDMACON.0
IE0.1
IPH0.1
IP0.1
Timer 1
0x0013
0x4013
0x8013
2
3
TMR1CON.7
TMR1CON.6
IE0.2
IPH0.2
IP0.2
Timer 2
0x001B
0x401B
0x801B
3
4
TMR2CON.7
TMR2CON.6
IE0.3
IPH0.3
IP0.3
MP3/FFT1
0x0023
0x4023
0x8023
4
5
AUCON7.6
AUCON7.5
AUCON7.4
AUCON7.3
AUCON7.2
AUCON7.1
AUCON7.0
AUCON11.6
FFT1CON1.1
IE0.4
IPH0.4
IP0.4
Huffman/
UART1
（overflow）
0x002B
0x402B
0x802B
5
6
HFMCON.7
HFMCON.6
UART1STA.1
IE0.5
IPH0.5
IP0.5
USBSOF
UART1
0x0033
0x4033
0x8033
6
7
USBCON2.1
UART1STA.3&UART1STA2
IE0.6
IPH0.6
IP0.6
USBCTL
0x003B
0x403B
0x803B
7
8
IE1.0
IPH1.0
IP1.0
SDC
0x0043
0x4043
0x8043
8
9
SDCON1.5
SDCON1.4
IE1.1
IPH1.1
IP1.1
PORT
0x004B
0x404B
0x808B
9
10
WKPND
IE1.2
IPH1.2
IP1.2
SPI0
0x0053
0x4053
0x8053
10
11
SPI0CON.7
IE1.3
IPH1.3
IP1.3
Timer 3
0x005B
0x405B
11
12
TMR3CON.7
IE1.4
IPH1.4
IP1.4
3 CPU Core Information 13
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
Interrupt
Sources
Interrupt
Vector
Interrupt
Number
Natural
Order
Interrupt Flag
Interrupt
Enable Bit
Priority
Control Bit
0x805B
Timer 0
0x0063
0x4063
0x8063
12
13
TMR0CON.7
IIS_CON2.3&IIS_CON2.1
IE1.5
IPH1.5
IP1.5
RTCC
UART0
WDT
LVD
IIS
0x006B
0x406B
0x806B
13
14
RTCON.7
UARTSTA.5&UARTSTA.4
IP0.7
LVDCON.7
IIS_CON2.3&IIS_CON2.2&
IIS_CON2.1&IIS_CON2.0
IE1.6
IPH1.6
IP1.6
SPI1
0x0073
0x4073
0x8073
14
15
SPI1CON.7
IE1.7
IPH1.7
IP1.7
3.4.2 Interrupt Priority
There are 4 levels of interrupt priority: Level 3 to 0. All interrupts have individual priority bits in the interrupt priority
registers to allow each interrupt to be assigned a priority level from 3 to 0. All interrupts also have a natural hierarchy.
In this manner, when a set of interrupts has been assigned the same priority, a second hierarchy determines which
interrupt is allowed to take precedence. The natural hierarchy is determined by analyzing potential interrupts in a
sequential manner with the order listed in Table 3-2.
The processor indicates that an interrupt condition occurred by setting the respective flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled.
3.5 Special Function Register Mapping (SFR)
Table 3-3 Special function registers naming and address
0
1
2
3
4
5
6
7
0x80
P0
SP
DPL0
DPH0
DPL1
DPH1
DPCON
PCON0
0x88
SDCON0
SDCON1
SDCON2
MEMCON
ATDAT
ERABYT0
/
ERABYT1
0x90
P1
BFBYTEPTRL
BFBYTEPTRH
BFDATAL
BFDATAH
BFBITPTR
BFCON
PCON3
0x98
PWKEN
PWKEDGE
PIE0
SPH
PCON1
ISDCHSUM
IRTCDAT
IRTCON
0XA0
P2
IIS_CON2
SPI1CON
SPI1BUF
ATADR
SPI1DMACNT
SPI1DMASP
IRCON0
0XA8
IE0
IE1
SPI1DMACNTL
IUBPCON
HFMCON1
IRCON1
AGCCON2
SPMODE
0XB0
P3
SQRT_DATA0
SQRT_DATA1
SQRT_DATA2
ERABYT2
ERABYT3
EMIBUF
PLLCON
0XB8
IP0
IP1
P0DIR
P1DIR
P2DIR
P3DIR
ERABYT4
LVDCON
0XC0
IIS_CON0
TMR2CON0
TMR2CON1
IIS_CON1
RTCON1
SECCNT
OTP_ADR
IRAM_ADR
0XC8
HFMCON
USBCON0
USBCON1
USBCON2
USBDATA
USBADR
OIRAMCNT
OIRAMCON
0XD0
PSW
HFMCNT
ADCCON
PCON2
ADCDATAL
ADCDATAH
COS_VALH
COS_VALL
14 3.6 Extend Special Function Registers Mapping (XSFR)
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
0XD8
SPI0BUF
SPI0CON
ADCMODE
CLKCON
CLKCON1
USBDPDM
SQRT_DATA3
PBANK0
0XE0
ACC
IPH0
IPH1
AUCON0
AUCON1
AUCON2
AUCON3
AUCON4
0XE8
AUCON5
AUCON6
AUCON7
AUCON8
AUCON9
AUCON10
SQRT_CFG
COS_IDX
0XF0
B
ER0H
ER0L
ER1H
ER1L
CRCREG
CRCFIFO
WDTCON
0XF8
TMR0CON
TMR0CNT
TMR0PR
TMR0PWM
UARTSTA
UARTCON
IIS_CON3
UARTDATA
3.6 Extend Special Function Registers Mapping (XSFR)
Table 3-4 XSFR space mapping
7
6
5
4
3
2
1
0
78D8H
AGCSETCNT
AGCSETDATA
BS_END_ADR
BS_BEGIN_ADR
78D0H
AGCDATL
AGCDATH
AGCDMAADR
AGCDMACON
AGCCON3
AGCANLCON
AGCCON1
AGCCON0
78C8H
-
-
FFT1_SQRTL_A
DDR
FFT1_SQRTH_A
DDR
FFT1SCALE
FFT1_BUFL_A
DDR
FFT1_BUFH_A
DDR
FFT1_DATAL_A
DDR
78C0H
FFT1_DATAH
_ADDR
-
IUBP3
IUBP2
IUBP1
IUBP0
78B8H
P3PDS1
P2PDS1
P1PDS1
-
P3PDS0
P2PDS0
P1PDS0
-
78B0H
P3PUS1
P2PUS1
P1PUS1
-
P3PUS0
P2PUS0
P1PUS0
-
78A8H
AGCRDATL
AGCRDATH
AGCSAMPLEH
AGCSAMPLEL
AGCCON4
UART1CNTH
UART1CNTL
UART1POINTH
78A0H
UART1POIN
TL
UART1MINUS
UART1LOOPCN
T
CLKCON2
ATCON10
ATCON9
FFT1CON1
FFT1CON
7898H
ATCON8
ATCON7
DCT_CFG
FIFO_BASE
FIFO_SPEED
AUCON11
KVADR
KVCON2
7890H
KVCON1
ATCON6
ATCON5
ATCON4
ATCON3
ATCON2
ATCON1
ATCON0
7888H
SPI1BAUD
UARTDIV
LFSR32_DAT3
LFSR32_DAT2
LFSR32_DAT1
LFSR32_DAT0
UARTBAUDH
UARTBAUD
7880H
IUBP
IUADR
IUDAT1
ID1
ID0
ECN
RANDOM_CNT
ADCBAUD
7878H
IISMDA_RD_
PCNT1
IISMDA_RD_P
CNT0
USBEP3TXADR
H
USBEP3TXADR
L
USBEP3RXAD
RH
USBEP3RXAD
RL
USBEP2TXADR
H
USBEP2TXADR
L
7870H
USBEP2RXA
DRH
USBEP2RXAD
RL
USBEP1TXADR
H
USBEP1TXADR
L
USBEP1RXAD
RH
USBEP1RXAD
RL
USBEP0ADRH
USBEP0ADRL
7868H
LFSR16_DAT
1
LFSR16_DAT0
-
EMICON1
EMICON0
FIFO_SET
FIFO_TRT
7860H
SFB_GEN
AUCON12
TMR2PWMH
TMR2PWML
TMR2PRH
TMR2PRL
TMR2CNTH
TMR2CNTL
7858H
PLL1FRAL
PLL1FRACH
PLL1INTL
PLL1INTH
TMR1CON1
TMR1CON0
TMR3PWM
TMR3PR
7850H
TMR3CNT
TMR3CON
TMR1PWMH
TMR1PWML
TMR1PRH
TMR1PRL
TMR1CNTH
TMR1CNTL
7848H
PLL2FRAL
PLL2FRACH
PLL2INTL
PLL2INTH
PLL2CON
P3PD0
P2PD0
P1PD0
7840H
P0PD0
-
P2PU1
PUP3
PUP2
PUP1
PUP0
7838H
PMUXCON0
PLL1DIV
SDADCDON
IIS_WSCNT1
PMUXCON1
IIS_ADR0
IIS_REFCLK_C
FG
7830H
IIS_DAT7
IIS_DAT6
IIS_DAT5
IIS_DAT4
IIS_DAT3
IIS_DAT2
IIS_DAT1
IIS_DAT0
7828H
IIS_BAUD
SPI1CON1
IIS_ALLBIT
IIS_DMA_RD_C
NT1
IIS_DMA_RD_
CNT0
IIS_DMA_WR_
CNT1
IIS_DMA_WR_
CNT0
P3DRV0
Table of contents
