Application Note 174
6Copyright © 2007. All rights reserved. DAI0174A
2.4 Asynchronous Mode
The ARM1136 bus interface ports can operate either synchronously or asynchronously to the
core clock, enabling the choice of core and bus clock frequencies. To keep things simple we will
not discuss how to use asynchronous mode here. You might want to use it on your ASIC design
if:
• the different ARM1136 ports are connected to AHB buses with asynchronous frequencies
• it is difficult to synchronise the core clock with the AHB clock across the whole chip
• the AHB clock is fixed at say 133MHz for the SDRAM and you are trying to run the core
as fast as possible, say 633MHz
• the AHB clock is fixed and you have multiple masters each with a different core frequency
• the AHB clock is fixed and you want to reduce the core clock to say 10MHz for power
saving.
The additional 1-cycle latency of using an asynchronous bridge is small compared to the 5 or
6-cycle latency of a normal access. For more details, see figure 8-2 in the ARM1136 Technical
Reference Manual, which compares the performance lost through synchronization penalty with
the performance lost through reducing the core frequency to be an integer multiple of the bus
frequency.
2.5 Constraints
Here is a list of constraints for the clock control registers. The registers are summarized in a table
at the end of this document.
• CM_OSC, CM_AUXOSC and CM_INIT are locked from accidental changes by the
CM_LOCK register. Write 0x0000A05F to CM_LOCK to unlock them, and any other
value to lock them.
• Changes to the clock dividers for CLK, HCLKI or HCLKE take place immediately. If you
are using the ARM1136JF-S in asynchronous mode (CPU asynchronous to bus ports),
you must make sure changes to these dividers propagate before selecting the
asynchronous ratio.
• HCLKI must be an integer multiple of HCLKE. In ARM1136JF-S synchronous mode (the
default), CLK must be an integer multiple of HCLKI greater than 1.
• Changes to PLLREFDIV, PLLFBDIV and PLLOUTDIV take place after a soft reset. That
is, when you press the CM1136 reset button S1, or when you set the RESET bit (bit 3) in
the CM_CTRL register. Reads from the CM_AUXOSC register (PLLOUTDIV and
PLLREFDIV control bits) will not show the updated values until a soft reset has occurred.
• When the Core Module is mounted on an AP baseboard or standalone, writes to CM_OSC
take effect immediately. When the Core Module is mounted on an Integrator/CP
baseboard (which uses a different FPGA image) you must perform a soft reset for changes
in CM_OSC to take effect.
• When mounted on a CP baseboard there is an undocumented feature to change clocks
without a soft reset. Setting bit 26 of the CM_OSC register forces the CM_INIT,
CM_OSC and CM_AUX registers to immediately update the hardware. To prevent the
test chip PLL and FPGA DLL losing lock you must keep the frequency changes small.
The DLL is more sensitive, its input can accept a change of up to 1ns period (where period
= 1 / frequency) without losing lock, for example changing HCLKE from 30 to 30.9MHz.
