ARTERY AT32F403A Series User manual

AT32F403A/407 CRM Quick Start Guide
2022.06.10 1 Ver 2.0.4
AN0082
Application Note
AT32F403A/407 CRM Quick Start Guide
Introduction
This application note mainly introduces:
1. How to configure and modify the clock source code based on the BSP_V2.x.x provided by Artery.
2. How to use the accessary clock configuration tools to set clock path and parameters to generate
and use the corresponding clock code.
Applicable products:
Part number
AT32F403Axx
AT32F407xx

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Contents
1Overview .........................................................................................................6
2Clock tree........................................................................................................7
3Code configuration .........................................................................................9
3.1 Functions ...........................................................................................................................9
3.2 Clock configuration..........................................................................................................10
3.2.1 CRM reset .............................................................................................................10
3.2.2 Clock source configuration.....................................................................................10
3.2.3 PLL configuration...................................................................................................11
3.2.4 Set bus frequency division.....................................................................................12
3.2.5 Switch system clock...............................................................................................12
3.2.6 Update core frequency...........................................................................................13
3.3 Example of clock configuration ......................................................................................13
4Clock configuration tools..............................................................................15
4.1 Environment requirement ...............................................................................................15
4.2 Installation........................................................................................................................15
4.3 Function overview ...........................................................................................................15
4.4 Menu bar..........................................................................................................................16
4.5 Create configuration project...........................................................................................16
4.6 Clock configuration interface..........................................................................................17
4.7 Generate code.................................................................................................................19
5Notes.............................................................................................................20
5.1 Modification of HEXT......................................................................................................20
5.2 Usage of tools..................................................................................................................20
6Application case 1: Switch system clock......................................................21
6.1 Introduction......................................................................................................................21
6.2 Resources........................................................................................................................21

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6.3 Software design...............................................................................................................21
6.4 Test result.........................................................................................................................23
7Application case 2: Clock fail detector .........................................................24
7.1 Introduction......................................................................................................................24
7.2 Resources........................................................................................................................24
7.3 Software design...............................................................................................................24
7.4 Test result.........................................................................................................................26
8Revision history............................................................................................27

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List of tables
Table 1. Document revision history............................................................................................... 27

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List of figures
Figure 1. AT32F403A/407 clock tree............................................................................................... 7
Figure 2. Clock configuration process........................................................................................... 10
Figure 3. Startup interface ............................................................................................................ 15
Figure 4. Configuration interface................................................................................................... 16
Figure 5. Menu bar ....................................................................................................................... 16
Figure 6. Select MCU ................................................................................................................... 17
Figure 7. Clock configuration interface.......................................................................................... 17
Figure 8. Clock configuration block............................................................................................... 18

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1 Overview
As the necessary condition for the correct and efficient running of chips, proper clock configuration
is of great importance. The clock configuration of each AT32 series MCU may be slight different.
This application note mainly introduces how to use BSP_V2.x.x provided by Artery to performclock
configuration of the corresponding AT32 MCU series.
The clock is configured with the following methods:
1. Manually write code to call the driver functions in BSP to implement clock configuration;
2. Use clock configuration tools to set and generate the corresponding source code file.

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2 Clock tree
Before configuring the clock, it is necessary to have a comprehensive understanding of the clock
tree, with focuses on the clock source, frequency multiplication and system clock.
Figure 1. AT32F403A/407 clock tree
USB
Divider
/1,1.5,
2,2.5,
3,3.5,
4HICK_TO_USB
USB48MUSBCLK To
USB interface
/128
LEXT RTCCLK RTC
LICK RC
40 kHz
RTCSEL[1:0]
LICK To WDT
WDTCLK
CLKOUT
Divider
/1,2..512
Clock
Output /2
/4
CLKOUT PLLCLK
PLLCLK
HICK
HEXT
SCLK
USB48M
ADCCLK
LICK
LEXT
CLKOUT_SEL
Peripheral
Clock
enable
PCLK1/2
Max.120 MHz
Max.240 MHz
ADC Divider
/2,4,6,8,12,16 To ADC1,2,3 ADCCLK Max.28 MHz
Peripheral
clock
enable
To SDIO/EMAC/
XMC/DMA/
memory
MACTXCLK
MII_RMII_SEL
EMAC_MII_TX_CLK
EMAC_MII_RX_CLK
0
1
0
1
/2,20
MII_RMII_SEL
To EMAC
To EMAC
EMACRMIICLK
MACRXCLK
ACC
HICK RC
48 MHz
/6
HICK48M
/2
HICK8M
HICK4M
HICKDIV
HICK
HEXT_OUT
HEXT_IN
HEXT OSC
4-25 MHz HEXT
HEXT
PLLRCS
64,…,*16,
*2,*3,*4
PLL
PLLMULT
HEXT
Divider
/2,3,4,5
PLLHEXTDIV
HICK4M
HEXT PLLCLK
PLLCLK
LEXT OSC
32.768 kHz
LEXT_IN
LEXT_OUT
LEXT
LICK
HICK_TO_SCLK
PLLCLK
SCLKSEL
CFD
HEXT
HICK8M
HEXT
HICK
HICK SCLK
Max.
240 MHz 12S1/2/3/4 CLK
Peripheral
clock
enable
AHB
Divider
/1,2...512
HCLK
Max.
240MHz
CPU FCLK
/8 CPU SysTick
APB1/2
Divider
/1,2,4,8,16
HCLK
Max.240MHz
to TMRxCLK
Peripheral
clock enable
To APB1/2
peripheral
PCLK2
Max.120 MHz
MII_RMII_SEL
To EMAC
SCLK
Max.
240 MHz
PCLK1/2
Max.120 MHz
APB1/2 divider ==1
x 2
PCLK1/2
Max.120 MHz

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Figure 1 contains the following key elements:
1) SCLKSEL: The system clock can be selected from HEXT, PLLCLK and HICK.
2) HEXT: It is a high-speed external oscillator that is connected externally to a 4~25 MHz crystal
or clock source.
3) HICK: It is a high-speed internal oscillator that is clocked by a high-speed RC, and the internal
frequency of the HICK clock is 48 MHz. The HICKDIV bit is used to select HICK (48 MHz) or
HICK/6 (if the HICK/6 is selected, the clock frequency is 8 MHz).
4) PLLCLK: PLL clock = PLL entry clock * PLL multiplication factor.
5) PLL entry clock: It is determined by PLLRCS and PLLHEXTDIV bits, and it can be selected
from HICK 4 MHz, HEXT and HEXTDIV (derived from HEXT division, HEXT/2 by default).

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3 Code configuration
This section introduces how to use library functions to configure the clock.
3.1 Functions
The interface functionsfor hardware clock configuration in BSP of the corresponding MCU series
are encapsulated and can be called. Functions commonly used for clock configuration are listed
below. Refer to at32f403a_407_crm.c/.h for detailsabout parameters and return value of each
function.
/* CRM resetfunction, whichresets clockconfigurationtodefault*/
void crm_reset(void);
/* HEXT bypass enablefunction */
void crm_hext_bypass(confirm_statenew_state);
/* Status flag get function, such as the stable status flag of PLL/HEXT/HICK */
flag_status crm_flag_get(uint32_tflag);
/* Wait for HEXT clock to stabilize*/
error_status crm_hext_stable_wait(void);
/* Clock source enablefunction,suchas enablePLL/HEXT/HICK*/
void crm_clock_source_enable(crm_clock_source_type source,confirm_statenew_state);
/* Clock frequencydivisionfunctionwhenHEXT is selectedas thePLL clocksource */
void crm_hext_clock_div_set(crm_hext_div_typevalue);
/* PLL configurationfunction,including PLLclocksource,PLL multiplicationfactor,frequencyafter multiplication*/
void crm_pll_config(crm_pll_clock_source_typeclock_source,crm_pll_mult_type mult_value,
crm_pll_output_range_typepll_range);
/* System clockswitchfunction */
void crm_sysclk_switch(crm_sclk_typevalue);
/* Current system clockswitchstatus getfunction */
crm_sclk_typecrm_sysclk_switch_status_get(void);
/* Auto step-by-stepsystem clockswitch enablefunction;when PLLfrequency> 108MHz, enableauto step-by-
stepswitchbefore switchingthe system clockto PLL */
void crm_auto_step_mode_enable(confirm_statenew_state);
/* HICK/6 configurationfunction,which is mainlyusedto implementHICK48MHz as system clockand USB
clock */
void crm_hick_divider_select(crm_hick_div_6_type value);
/* Frequencyselectfunctionwhen HICK is selectedas system clock; thefrequencycan beset to a fixed value (8
MHz) or HICK/6 (depending ontheHICK divider selectfunction) */
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_typevalue);
/* System clockto AHB clockdivider configurationfunction */
void crm_ahb_div_set(crm_ahb_div_typevalue);
/* AHB clock to APB1 clock divider configurationfunction */

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void crm_apb1_div_set(crm_apb1_div_typevalue);
/* AHB clock to APB2 clock divider configurationfunction */
void crm_apb2_div_set(crm_apb2_div_typevalue);
3.2 Clock configuration
Figure 2 shows the clock configuration process.
Figure 2. Clock configuration process
CRM Reset
Clock Source Enable
PLL Configuration
UpdateCore Frequency
Switch System Clock
Set Bus Frequency Division
3.2.1 CRM reset
According to the configuration process, performCRM reset firstly, which switches system clock to
HICK, and write the default value to other system clock configuration registers. The code to reset
CRM is as follows:
crm_reset(); /* CRM reset*/
3.2.2 Clock source configuration
The HEXT or HICK can be selected as the system clock source, which can also be used as a
reference clock source of PLL. Before enabling PLL, enable the PLL reference clock source and
wait untilit becomes stable.
HEXT
If HEXT is connected externallyto an active clock, the HEXT bypass mode should be enabled. If
the crystal oscillator is used, the HEXT bypass mode should be disabled. The bypass mode is set
before enabling the HEXT clock source (disabled by default). The code to enable HEXT bypass
mode is as follows:
crm_hext_bypass(TRUE); /* HEXT bypass modeenable */
Enable HEXT clock source and wait untilHEXT clock becomes stable. The code is as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT,TRUE); /* Enable HEXT clocksource */
while(crm_hext_stable_wait()==ERROR) /* Wait until HEXT clock becomes stable */
{
}