ARTERY AT32F403A Series User manual

AT32F403A/407 CRM Quick Start Guide
2022.06.10 1 Ver 2.0.4
AN0082
Application Note
AT32F403A/407 CRM Quick Start Guide
Introduction
This application note mainly introduces:
1. How to configure and modify the clock source code based on the BSP_V2.x.x provided by Artery.
2. How to use the accessary clock configuration tools to set clock path and parameters to generate
and use the corresponding clock code.
Applicable products:
Part number
AT32F403Axx
AT32F407xx

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Contents
1Overview .........................................................................................................6
2Clock tree........................................................................................................7
3Code configuration .........................................................................................9
3.1 Functions ...........................................................................................................................9
3.2 Clock configuration..........................................................................................................10
3.2.1 CRM reset .............................................................................................................10
3.2.2 Clock source configuration.....................................................................................10
3.2.3 PLL configuration...................................................................................................11
3.2.4 Set bus frequency division.....................................................................................12
3.2.5 Switch system clock...............................................................................................12
3.2.6 Update core frequency...........................................................................................13
3.3 Example of clock configuration ......................................................................................13
4Clock configuration tools..............................................................................15
4.1 Environment requirement ...............................................................................................15
4.2 Installation........................................................................................................................15
4.3 Function overview ...........................................................................................................15
4.4 Menu bar..........................................................................................................................16
4.5 Create configuration project...........................................................................................16
4.6 Clock configuration interface..........................................................................................17
4.7 Generate code.................................................................................................................19
5Notes.............................................................................................................20
5.1 Modification of HEXT......................................................................................................20
5.2 Usage of tools..................................................................................................................20
6Application case 1: Switch system clock......................................................21
6.1 Introduction......................................................................................................................21
6.2 Resources........................................................................................................................21

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6.3 Software design...............................................................................................................21
6.4 Test result.........................................................................................................................23
7Application case 2: Clock fail detector .........................................................24
7.1 Introduction......................................................................................................................24
7.2 Resources........................................................................................................................24
7.3 Software design...............................................................................................................24
7.4 Test result.........................................................................................................................26
8Revision history............................................................................................27

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List of tables
Table 1. Document revision history............................................................................................... 27

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List of figures
Figure 1. AT32F403A/407 clock tree............................................................................................... 7
Figure 2. Clock configuration process........................................................................................... 10
Figure 3. Startup interface ............................................................................................................ 15
Figure 4. Configuration interface................................................................................................... 16
Figure 5. Menu bar ....................................................................................................................... 16
Figure 6. Select MCU ................................................................................................................... 17
Figure 7. Clock configuration interface.......................................................................................... 17
Figure 8. Clock configuration block............................................................................................... 18

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1 Overview
As the necessary condition for the correct and efficient running of chips, proper clock configuration
is of great importance. The clock configuration of each AT32 series MCU may be slight different.
This application note mainly introduces how to use BSP_V2.x.x provided by Artery to performclock
configuration of the corresponding AT32 MCU series.
The clock is configured with the following methods:
1. Manually write code to call the driver functions in BSP to implement clock configuration;
2. Use clock configuration tools to set and generate the corresponding source code file.

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2 Clock tree
Before configuring the clock, it is necessary to have a comprehensive understanding of the clock
tree, with focuses on the clock source, frequency multiplication and system clock.
Figure 1. AT32F403A/407 clock tree
USB
Divider
/1,1.5,
2,2.5,
3,3.5,
4HICK_TO_USB
USB48MUSBCLK To
USB interface
/128
LEXT RTCCLK RTC
LICK RC
40 kHz
RTCSEL[1:0]
LICK To WDT
WDTCLK
CLKOUT
Divider
/1,2..512
Clock
Output /2
/4
CLKOUT PLLCLK
PLLCLK
HICK
HEXT
SCLK
USB48M
ADCCLK
LICK
LEXT
CLKOUT_SEL
Peripheral
Clock
enable
PCLK1/2
Max.120 MHz
Max.240 MHz
ADC Divider
/2,4,6,8,12,16 To ADC1,2,3 ADCCLK Max.28 MHz
Peripheral
clock
enable
To SDIO/EMAC/
XMC/DMA/
memory
MACTXCLK
MII_RMII_SEL
EMAC_MII_TX_CLK
EMAC_MII_RX_CLK
0
1
0
1
/2,20
MII_RMII_SEL
To EMAC
To EMAC
EMACRMIICLK
MACRXCLK
ACC
HICK RC
48 MHz
/6
HICK48M
/2
HICK8M
HICK4M
HICKDIV
HICK
HEXT_OUT
HEXT_IN
HEXT OSC
4-25 MHz HEXT
HEXT
PLLRCS
64,…,*16,
*2,*3,*4
PLL
PLLMULT
HEXT
Divider
/2,3,4,5
PLLHEXTDIV
HICK4M
HEXT PLLCLK
PLLCLK
LEXT OSC
32.768 kHz
LEXT_IN
LEXT_OUT
LEXT
LICK
HICK_TO_SCLK
PLLCLK
SCLKSEL
CFD
HEXT
HICK8M
HEXT
HICK
HICK SCLK
Max.
240 MHz 12S1/2/3/4 CLK
Peripheral
clock
enable
AHB
Divider
/1,2...512
HCLK
Max.
240MHz
CPU FCLK
/8 CPU SysTick
APB1/2
Divider
/1,2,4,8,16
HCLK
Max.240MHz
to TMRxCLK
Peripheral
clock enable
To APB1/2
peripheral
PCLK2
Max.120 MHz
MII_RMII_SEL
To EMAC
SCLK
Max.
240 MHz
PCLK1/2
Max.120 MHz
APB1/2 divider ==1
x 2
PCLK1/2
Max.120 MHz

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Figure 1 contains the following key elements:
1) SCLKSEL: The system clock can be selected from HEXT, PLLCLK and HICK.
2) HEXT: It is a high-speed external oscillator that is connected externally to a 4~25 MHz crystal
or clock source.
3) HICK: It is a high-speed internal oscillator that is clocked by a high-speed RC, and the internal
frequency of the HICK clock is 48 MHz. The HICKDIV bit is used to select HICK (48 MHz) or
HICK/6 (if the HICK/6 is selected, the clock frequency is 8 MHz).
4) PLLCLK: PLL clock = PLL entry clock * PLL multiplication factor.
5) PLL entry clock: It is determined by PLLRCS and PLLHEXTDIV bits, and it can be selected
from HICK 4 MHz, HEXT and HEXTDIV (derived from HEXT division, HEXT/2 by default).

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3 Code configuration
This section introduces how to use library functions to configure the clock.
3.1 Functions
The interface functionsfor hardware clock configuration in BSP of the corresponding MCU series
are encapsulated and can be called. Functions commonly used for clock configuration are listed
below. Refer to at32f403a_407_crm.c/.h for detailsabout parameters and return value of each
function.
/* CRM resetfunction, whichresets clockconfigurationtodefault*/
void crm_reset(void);
/* HEXT bypass enablefunction */
void crm_hext_bypass(confirm_statenew_state);
/* Status flag get function, such as the stable status flag of PLL/HEXT/HICK */
flag_status crm_flag_get(uint32_tflag);
/* Wait for HEXT clock to stabilize*/
error_status crm_hext_stable_wait(void);
/* Clock source enablefunction,suchas enablePLL/HEXT/HICK*/
void crm_clock_source_enable(crm_clock_source_type source,confirm_statenew_state);
/* Clock frequencydivisionfunctionwhenHEXT is selectedas thePLL clocksource */
void crm_hext_clock_div_set(crm_hext_div_typevalue);
/* PLL configurationfunction,including PLLclocksource,PLL multiplicationfactor,frequencyafter multiplication*/
void crm_pll_config(crm_pll_clock_source_typeclock_source,crm_pll_mult_type mult_value,
crm_pll_output_range_typepll_range);
/* System clockswitchfunction */
void crm_sysclk_switch(crm_sclk_typevalue);
/* Current system clockswitchstatus getfunction */
crm_sclk_typecrm_sysclk_switch_status_get(void);
/* Auto step-by-stepsystem clockswitch enablefunction;when PLLfrequency> 108MHz, enableauto step-by-
stepswitchbefore switchingthe system clockto PLL */
void crm_auto_step_mode_enable(confirm_statenew_state);
/* HICK/6 configurationfunction,which is mainlyusedto implementHICK48MHz as system clockand USB
clock */
void crm_hick_divider_select(crm_hick_div_6_type value);
/* Frequencyselectfunctionwhen HICK is selectedas system clock; thefrequencycan beset to a fixed value (8
MHz) or HICK/6 (depending ontheHICK divider selectfunction) */
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_typevalue);
/* System clockto AHB clockdivider configurationfunction */
void crm_ahb_div_set(crm_ahb_div_typevalue);
/* AHB clock to APB1 clock divider configurationfunction */

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void crm_apb1_div_set(crm_apb1_div_typevalue);
/* AHB clock to APB2 clock divider configurationfunction */
void crm_apb2_div_set(crm_apb2_div_typevalue);
3.2 Clock configuration
Figure 2 shows the clock configuration process.
Figure 2. Clock configuration process
CRM Reset
Clock Source Enable
PLL Configuration
UpdateCore Frequency
Switch System Clock
Set Bus Frequency Division
3.2.1 CRM reset
According to the configuration process, performCRM reset firstly, which switches system clock to
HICK, and write the default value to other system clock configuration registers. The code to reset
CRM is as follows:
crm_reset(); /* CRM reset*/
3.2.2 Clock source configuration
The HEXT or HICK can be selected as the system clock source, which can also be used as a
reference clock source of PLL. Before enabling PLL, enable the PLL reference clock source and
wait untilit becomes stable.
HEXT
If HEXT is connected externallyto an active clock, the HEXT bypass mode should be enabled. If
the crystal oscillator is used, the HEXT bypass mode should be disabled. The bypass mode is set
before enabling the HEXT clock source (disabled by default). The code to enable HEXT bypass
mode is as follows:
crm_hext_bypass(TRUE); /* HEXT bypass modeenable */
Enable HEXT clock source and wait untilHEXT clock becomes stable. The code is as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT,TRUE); /* Enable HEXT clocksource */
while(crm_hext_stable_wait()==ERROR) /* Wait until HEXT clock becomes stable */
{
}

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HICK
The HICK oscillator is clocked by a high-speed RC in the microcontroller. Enable HICK clock
source and wait until HICK clock becomes stable. The code is as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK,TRUE); /* Enable HICK clock source*/
while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) /* Wait until HICK stableflagis set*/
{
}
3.2.3 PLL configuration
PLL configuration includes PLL clock source, PLL multiplication factor and PLL frequency range
after multiplication. The frequency multiplication formula is PLLCLK = PLL entry clock * PLL
multiplication factor.
PLL clock source
PLL clock source can be selected fromHICK (4 MHz), HEXT and a divided HEXT. PLL clock
source is enabled and becomes stable before enabling the PLL configuration. The corresponding
parameters of these three clock sources in crm_pll_config function are as follows:
CRM_PLL_SOURCE_HICK
CRM_PLL_SOURCE_HEXT
CRM_PLL_SOURCE_HEXT_DIV
When the PLL is clocked by CRM_PLL_SOURCE_HEXT_DIV, the HEXT division factor is set by
the crm_hext_clock_div_set function. The HEXT is divided by 2, by default.
PLL multiplication factor
The PLL multiplication factor is set (from 2 to 64) according to the maximum frequency. For
example, select CRM_PLL_MULT_8, indicating that the multiplication factor is 8.
PLL frequency range
The frequency range is set according to PLLCLK after multiplication.
CRM_PLL_OUTPUT_RANGE_LE72MHZ /* PLLCLK≤72 MHz */
CRM_PLL_OUTPUT_RANGE_GT72MHZ /* PLLCLK> 72 MHz */
After the PLL configuration is completed, enable PLL and wait until the PLL becomes stable. For
example, select HEXT/2 (8 MHz/2= 4 MHz) as the PLL clock source, and the code to implement
240 MHz PLLCLK is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_60,
CRM_PLL_OUTPUT_RANGE_GT72MHZ); /* ConfigurePLLparameters */
crm_hext_clock_div_set(CRM_HEXT_DIV_2); /* ConfigureHEXT division factor*/
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL,TRUE); /* Enable PLLclock source */
while(crm_flag_get(CRM_PLL_STABLE_FLAG)!= SET) /* Wait until PLL stable flag is set*/
{
}

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3.2.4 Set bus frequency division
The bus frequency division configuration includes SCLK to AHBCLK, AHBCLK to APB1CLK and
AHBCLK to APB2CLK. The code to implement AHB bus (SCLK/1) and APB1/APB2 bus
(AHBCLK/2) is as follow:
crm_ahb_div_set(CRM_AHB_DIV_1); /* SCLK/1 is used as AHB bus clock*/
crm_apb2_div_set(CRM_APB2_DIV_2); /* AHBCLK/2 is used as APB2 bus clock */
crm_apb1_div_set(CRM_APB1_DIV_2); /* AHBCLK/2 is usedas APB1 bus clock */
3.2.5 Switch system clock
The system clock has three main sources: HICK, HEXT and PLLCLK. Before switching the system
clock to any of the three clocks, the corresponding clock source must be stable.
Auto step-by-step switch mode
The automatic frequency switch is designed to ensure a smooth and stable switch of system
frequency. When the operational target islarger than 108 MHz, it is recommended to enable the
auto step-by-step switch mode. Thisfunction is mainly used when PLLCLK is selected as system
clock, which is enabled before switching the system clock and disabled after the switching is
completed. The code is as follows:
crm_auto_step_mode_enable(TRUE); /* Enableauto step-by-step switchmode */
crm_auto_step_mode_enable(FALSE); /* Disable autostep-by-step switchmode */
HICK
The HICK is used as system clock source by default after system reset. As shown inFigure 1, the
HICK frequency is set to 8 MHz (by default) and can be set to 48 MHz.
The code to configure HICK 8 MHz as system clock is as follows:
crm_sysclk_switch(CRM_SCLK_HICK); /* Switch system clocksourceto HICK */
while(crm_sysclk_switch_status_get()!= CRM_SCLK_HICK) /* Wait until the system clock is switchedto
HICK */
{
}
The code of to configure HICK 48 MHz as system clock is as follows:
crm_hick_sclk_frequency_select (CRM_HICK_SCLK_48MHZ); /* Select 48 MHz HICK */
crm_sysclk_switch(CRM_SCLK_HICK); /* Switch system clocksource to
HICK */
while(crm_sysclk_switch_status_get()!= CRM_SCLK_HICK) /* Wait until the system clock is
switchedto HICK */
{
}
HEXT
When the HEXT is used as system clock source, the system clock frequency depends on the actual
external clock frequency (range: 4~25 MHz). The code to configure HEXT as system clock source

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is as follows:
crm_sysclk_switch(CRM_SCLK_HEXT); /* Switch system clocksourceto HEXT */
while(crm_sysclk_switch_status_get()!= CRM_SCLK_HEXT) /* Wait until the system clockis switched
to HEXT */
{
}
PLLCLK
When the PLLCLK is used as system clock source, the system clock frequency depends on the
actual PLL frequency multiplication and the maximum frequency. The code to configure PLLCLKas
system clock source is as follows:
crm_sysclk_switch(CRM_SCLK_PLL); /* Switchsystem clocksource to PLL */
while(crm_sysclk_switch_status_get()!= CRM_SCLK_PLL) /* Wait until the system clock is switchedto
PLL */
{
}
3.2.6 Update core frequency
The parameter “system_core_clock” indicating the system core frequency is reserved in the BSP
code framework to save the CPU core operating frequency. It is updated each time the system
clock is configured, so that peripherals can quicklyget and use the current core operating
frequency. The code is as follows:
system_core_clock_update(); /* Updatesystem corefrequency system_core_clock*/
3.3 Example of clock configuration
In this example, the 8 MHz HEXT is used as clock source, then select HEXT/2 and implement 240
MHz system clock through PLL multiplication; SCLK/1 is used as AHB bus clock, and AHBCLK/2 is
used as APB1/APB2 bus clock. The system_clock_config function code is as follows:
void system_clock_config(void)
{
crm_reset(); /* CRM reset*/
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT,TRUE); /* Enable HEXT clocksource */
while(crm_hext_stable_wait()==ERROR) /* Wait until HEXT clock becomes
stable*/
{
}
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_60,
CRM_PLL_OUTPUT_RANGE_GT72MHZ); /* Configure PLL: selectHEXT division
factor, setmultiplicationfactor=60 and PLL clock output range > 72 MHz; formula:PLLCLK= 8 / 2 * 60 = 240
MHz */
crm_hext_clock_div_set(CRM_HEXT_DIV_2); /* HEXT is divided by 2 */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL,TRUE); /* EnablePLL*/

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while(crm_flag_get(CRM_PLL_STABLE_FLAG)!= SET) /* Wait until PLL becomes stable */
{
}
crm_ahb_div_set(CRM_AHB_DIV_1); /* SCLK/1 is usedas AHB bus clock*/
crm_apb2_div_set(CRM_APB2_DIV_2); /* AHBCLK/2 is usedas APB2 bus clock */
crm_apb1_div_set(CRM_APB1_DIV_2); /* AHBCLK/2 is usedas APB1 bus clock */
crm_auto_step_mode_enable(TRUE); /* PLLCLK240 MHz >108MHz, enable
auto step-by-step switchmode */
crm_sysclk_switch(CRM_SCLK_PLL); /* Switchsystem clocksourceto PLL */
while(crm_sysclk_switch_status_get()!= CRM_SCLK_PLL) /* Wait until the system clock is switched
to PLL */
{
}
crm_auto_step_mode_enable(FALSE); /* Switchcompleted,disable autostep-by-
step switch mode */
system_core_clock_update(); /* Updatesystem corefrequency */
}

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4 Clock configuration tools
The New Clock Configuration is a graphicalconfiguration tool developed by Artery for configuring
the clock of AT32 series MCUs, to help users have a better understanding of the clock path,
configure the required frequency and generate source files.
4.1 Environment requirement
Software
Windows7 and above
4.2 Installation
Software installation
Run AT32_New_Clock_Configuration.exe directly.
4.3 Function overview
This section mainly introduces basic operations of this tool. The startup interface and configuration
interface are shown below.
Figure 3. Startup interface

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Figure 4. Configuration interface
4.4 Menu bar
The menu bar is shown below.
Figure 5. Menu bar
Project
New
Create a new configuration project
Open
Open an existing configuration project
Save
Save the current configuration project
Language
English
Select English as the display language
Chinese
Select simplified Chinese as the display language
Generate code
Configure the required clock path and clock frequency of the corresponding MCU series, then click
“Generate code” to select the storage path and generate the corresponding source file.
Help
New version download
Connect to network to download the latest version
Version
View the current version
4.5 Create configuration project
Double click to run the AT32_New_Clock_Configuration.exe; go to Project-->New in the startup
interface to create a newconfiguration project, and select the corresponding MCU series, as shown
in Figure 6.

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Figure 6. Select MCU
Click on the drop-down box to select the corresponding MCU series; then click on “OK” to enter the
configuration interface.
4.6 Clock configuration interface
Users can configure the clock path and parameters in the clock configuration interface. Figure 7
shows the clock configuration forAT32F403Aseries MCU.
The clock configuration interface mainly contains four blocks, as shown below.
Figure 7. Clock configuration interface
1. Title: Display the corresponding MCUseries of the current clock configuration project.
2. Configuration: Select and configure the clock path and parameters to meet application
requirements.
3. Output: Configure the clock output (CLKOUT).
4. SCLK: When the PLL is used as system clock, the SCLK field can be used as an input box of
desired system clock frequency to automatically configure the multiplication factor reversely.
5. Result: Display the clock frequency of peripherals and peripherals on the bus.
1
2
3
4
5

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Figure 8 illustrates the clock configuration block. The configuration process corresponds to MCU
clock tree, which may be slightly different for different MCU series. The clock path can be
configured by clicking on each checkbox according to the configuration process, as shown below.
Figure 8. Clock configuration block
1. rtc enable: drop-down box, which is used to enable RTC clock code configuration.
2. rtcsel: checkbox for RTCclock source selection; when the rtc is enabled, click on this checkbox
for configuration.
3. lext bypass: LEXT bypass enable.
4. hext: input box, which is 8 MHz by default; itcan be modified according to the actualexternal
clock source (note: if other frequency value is set, the HEXT_VALUE in
inc/at32f403a_407_conf.h in the corresponding BSP demo should be modified, or use the
at32f403a_407_conf.hfile generated by using tools).
5. hext bypass: HEXT bypass enable.
6. hextdiv: drop-down box, which is used to configure the HEXT division factor when a divided
HEXT is used as PLL clock source.
7. pllhextdiv: checkbox, which is used to configure HEXT or divided HEXT when HEXT is used as
PLL clock source.
8. pllrcs: checkbox, which is used to select HEXT or HICK as the PLL clock source.
9. Multiplication factor: the PLL_MULT is used for frequency multiplication (PLLCLK = PLL entry
clock * PLL_MULT). After the PLL entry clock is selected, input the desired frequency into the
output “sclk”field and then press “Enter”, and a set of proper or approximate multiplication
factors will be calculated automatically to meet requirements.
10. sclk select: checkbox, which is used to configure HEXT, PLL or HICK as the system clock.
11. sclk frequency: In forward configuration, it displays the configuration result of system clock
frequency. When it is used as an input box, users can input the desired frequency and press
“Enter”, and then a set of proper or approximate PLL multiplication factors will be calculated.
12. hick to sclk: checkbox, which is used to configure HICK/6 (8 MHz) or HICK (48 MHz) as the
system clock when HICK is selected in the “sclk select” checkbox (note: if 48 MHz HICK is
2
4
5
6
7
8
9
10
1
11
12
13
14
15
16
3

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selected, CLKOUT HICK frequency is also 48 MHz).
13. usbdiv: drop-down box, which is used to configure PLL division factor when PLL clock is
selected as the USB clock source.
14. hick to usb: checkbox, which is used to configure USB clocked by PLL clock or HICK 48 MHz.
The USB clock configuration code is controlled by the “to usb” drop-down box. The USB clock
is required to be fixed 48 MHz; therefore, with the division factor in “usbdiv”, USB 48 MHz may
not be implemented through PLL multiplication.
15. USB enable: drop-down box for enabling USB clock code configuration.
16. USB clock frequency display: this field calculates and displays USB clock frequency in a real-
time manner. If the configured USB clock frequency is not equal to 48 MHz, the frequency value
will be displayed in red; if USB clock is not used, select “disable” in the drop-down box and no
message will be displayed (note: it is only used for USB clock frequency configuration; USB
peripheral clocks are enabled separately as needed).
4.7 Generate code
After clock configuration is completed, click on “Generate code”, select and confirm the code
storage path, and then two folders “inc” and “src” are generated to save the header file and source
file, respectively. These files can be used together with the project in BSP_V2.x.x. The generated
clock code file (at32f4xx_clock.c/ at32f4xx_clock.h/ at32f4xx_conf.h) can replace the corresponding
file in the original BSP demo, and can be used by calling the system_clock_config in the main
function.

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5 Notes
5.1 Modification of HEXT
The HEXT involved in demo and configuration tools in this application note is 8 MHz. To modify the
8 MHz HEXT in actual applications, the following aspects should be noted:
Code
1. Compile the code according to the actual external clock frequency and the configuration
process and method as described in this application note to set the required clock
configuration and clock path.
2. Modify the HEXT_VALUE in at32f4xx_conf.h file of the corresponding demo project according
to the actualHEXT clock frequency. For example, if the 12.288 MHz externalcrystal oscillator
or clock source is used, modify the at32f4xx_conf.h file as below:
#if !defined HEXT_VALUE
#defineHEXT_VALUE ((uint32_t)12288000)
#endif
Tools
1. Input the actual frequency of external clock source to the HEXT input box, and then press
“Enter”.
2. Configure the required clock path and clock frequency, and then generate code. Use the
generated clock code file (at32f4xx_clock.c/ at32f4xx_clock.h/ at32f4xx_conf.h) to replace the
corresponding file or function content in the original BSP demo, and then call the
system_clock_config in the main function.
5.2 Usage of tools
Notes on using the New Clock Configuration tool:
1. The clock configuration source file generated by the New Clock Configuration tool should be
used together with BSP_V2.x.x provided by Artery.
2. The clock configuration source file generated for the specificMCU series should be used in the
corresponding project only.
3. After modifying parameters in each input box, press “Enter” to confirm.