artisan DAC128V Application guide

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DAC128V
8-Channel, 12-bit, 8-range
±10 V Digital-to-Analog Board
Hardware Reference
Document No. B-T-MR-DAC128V#-A-0-A4
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FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Systran reserves the right to make changes without notice.
Systran makes no warranty of any kind with regard to this printed material including, but not limited to,
the implied warranties of merchantability and fitness for a particular purpose.
ãCopyright 2001 Systran Corporation. All rights reserved.
ALTERA®and Altera®are registered trademarks of Altera Corporation.
HP®is a registered trademark of the Hewlett-Packard Company.
Motorola®is a registered trademark of the Motorola Corporation.
NuBusis a trademark of Texas Instruments, Inc.
OS-9®is a registered trademark of Microware Systems Corporation.
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
ViewDraw®and VIEWlogic®are registered trademarks of Viewlogic Systems, Inc.
ALTERA: Code © 1997, Systran Corp., All Rights Reserved. The code (programs) contained in this
product are proprietary to Systran Corp. and copying or other use of the bit-stream programs, except as
expressly authorized by Systran Corp., is expressly prohibited.
Any reference made within this document to equipment from other vendors does not constitute an
endorsement of their product(s).
Revised: July 13, 2001
Systran Corporation
4126 Linden Avenue
Dayton, OH 45432-3068 USA
[phone] (U.S. only)
[phone]
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FCC
This product is intended for use in industrial, laboratory or military environments. This product uses and
emits electromagnetic radiation, which may interfere with other radio and communication devices. The
user may be in violation of FCC regulations if this device is used in other than the intended market
environments.
CE
As a component part of another system, this product has no intrinsic function and is therefore not subject
to the European Union CE EMC directive 89/336/EEC.
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Copyright 2001 i DAC128V HARDWARE REFERENCE
TABLE OF CONTENTS
1. INTRODUCTION..................................................................................................................... 1-1
1.1 How to Use This Manual .......................................................................................... 1-1
1.1.1 Purpose .................................................................................................... 1-1
1.1.2 Scope........................................................................................................ 1-1
1.1.3 Conventions ............................................................................................. 1-1
1.2 Related Information .................................................................................................. 1-1
1.3 Quality Assurance ..................................................................................................... 1-2
1.4 Technical Support ..................................................................................................... 1-2
1.5 Ordering Process ....................................................................................................... 1-3
2. PRODUCT OVERVIEW........................................................................................................... 2-1
2.1 Overview................................................................................................................... 2-1
2.2 Features ..................................................................................................................... 2-1
2.3 Related Products........................................................................................................ 2-2
2.4 Block Diagram Description....................................................................................... 2-2
2.5 Detailed Description.................................................................................................. 2-4
2.6 Digital Components and their Functions................................................................... 2-4
2.7 DAC’s Voltage Ranges.............................................................................................. 2-5
2.7.1 High Reference For QDAC#1.................................................................. 2-5
2.7.2 Low Reference For QDAC#1 .................................................................. 2-6
2.7.3 High Reference For QDAC#2.................................................................. 2-6
2.7.4 Low Reference For QDAC#2 .................................................................. 2-6
2.8 Reference Voltage Generation................................................................................... 2-6
2.9 External Analog Supply ............................................................................................ 2-7
2.10 The Buffers.............................................................................................................. 2-7
2.11 The DACs................................................................................................................ 2-8
2.12 DAC128V Cleaning ................................................................................................ 2-8
3. INSTALLATION....................................................................................................................... 3-1
3.1 Unpacking the DAC128V ......................................................................................... 3-1
3.2 Visual Inspection of the DAC128V........................................................................... 3-1
3.3 DAC128V Installation............................................................................................... 3-1
4. PERFORMANCE ..................................................................................................................... 4-1
4.1 Overview................................................................................................................... 4-1
4.2 Timing measurements ............................................................................................... 4-1
4.3 IP Module Accesses .................................................................................................. 4-2
4.4 Wrong Supply Impact ............................................................................................... 4-3
4.5 Maximum Loads ....................................................................................................... 4-6
4.6 Beyond Temperature ................................................................................................. 4-8
4.7 Slew Time Tests........................................................................................................ 4-9
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TABLE OF CONTENTS
Copyright 2001 ii DAC128V HARDWARE REFERENCE
APPENDICES
APPENDIX A – SPECIFICATIONS............................................................................................ A-1
APPENDIX B – TYPICAL APPLICATIONS ............................................................................. B-1
APPENDIX C – PROGRAMMING GUIDE................................................................................C-1
GLOSSARY ................................................................................................................ GLOSSARY- 1
INDEX ................................................................................................................................INDEX-1
FIGURES
Figure 2-1 DAC128V Board ......................................................................................................... 2-1
Figure 2-2 DAC128V Simplified Block Diagram......................................................................... 2-2
Figure 2-3 Detailed Block Diagram .............................................................................................. 2-3
Figure 2-4 DAC128V Physical Assembly..................................................................................... 2-4
Figure 3-1 Installation of the DAC128V on a VME IP Module Carrier Board............................. 3-2
Figure 3-2 Installation of the DAC128V on an ISA IP Module Carrier Board. ............................ 3-2
Figure 4-1 IP Module Test Configuration for Oscilloscope and State Timing Measurements...... 4-1
Figure 4-2 I/O Write at IPA = 0x00 ..............................................................................................4-3
Figure 4-3 Typical Read Access Timing Sequence....................................................................... 4-5
Figure 4-4 Flatlined Overcurrent Condition Chart ........................................................................ 4-6
Figure 4-5 Typical Slew-Time Waveform .................................................................................... 4-9
TABLES
Table 3-1 Contents of DAC128V Shipping Package .................................................................... 3-1
Table 3-2 DAC128V Installation Tools ........................................................................................ 3-2
Table 3-3 IP Module Logic Bus Pin Assignments ........................................................................ 3-4
Table 3-4 IP Module I/O Connector Pin Assignments .................................................................. 3-5
Table 4-1 IP Module Access Time ................................................................................................ 4-2
Table 4-2 Wrong Power Supplies..................................................................................................4-4
Table 4-3 Fixed Overloads ............................................................................................................ 4-6
Table 4-4 Maximum Currents ....................................................................................................... 4-7
Table 4-5 Extreme Temperature Performance .............................................................................. 4-8
Table 4-6 Slew Time Tests.......................................................................................................... 4-10
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Copyright 2001 1-1 DAC128V HARDWARE REFERENCE
1. INTRODUCTION
1.1 How to Use This Manual
1.1.1 Purpose
This is a reference manual for Systran’s 8-channel, 12-bit, 8-range +V Digital to Analog
Converter (DAC) IndustryPack (also called IP Module) board, referred to in this manual
as the DAC128V (part number BHAS-DAC128V).
1.1.2 Scope
This reference manual covers the physical and operational description of the DAC128V,
both from hardware and software perspectives. This manual also contains detailed
technical information about the DAC128V’s performance characteristics, and some
typical applications.
You need a general understanding of computer processing, software and/or hardware
applications experience, and a working knowledge of the use of IP Modules on a carrier
board to effectively use this manual.
1.1.3 Conventions
• Called functions are italicized. For example, OpenConnect().
• Data types are italicized. For example, int.
• Function parameters are bolded. For example, Action.
• Path names are italicized. For example, utility/sw/cfg.
• File names are bolded. For example, config.c.
• Path file names are italicized and bolded. For example, utility/sw/cfg/config.c.
• Hexadecimal values are written with a “0x” prefix. For example, 0x7E.
• An ‘Active Low’ signal on a hardware product has a slash (/) prefix. For
example, /SYNC.
• Code and monitor screen displays of input and output are boxed and indented on
a separate line. Text that represents user input is bolded. Text that the computer
displays on the screen is not bolded. For example:
c:\>ls
file1 file2 file3
• Large samples of code are Courier font, at least one size less than context, and
are usually on a separate page or in an appendix.
1.2 Related Information
• Systran I/O Products Technical Note #2001 entitled Programmed Transfer Rate
Analysis of the IP Bus Onboard the Motorola MVME162 Controller
(Doc. A-T-ST-IPAC2001)
• American National Standard for IP Modules (ANSI/VITA 4 - 1995) published by
VMEbus International Trade Association (VITA), 7825 E. Gelding Drive, Suite
104, Scottsdale, AZ 85260-3415 USA. Phone: [phone], FAX: 480-951-
0720, E-mail: [email protected], URL: www.vita.com
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INTRODUCTION
Copyright 2001 1-2 DAC128V HARDWARE REFERENCE
• Systran Corporation: www.systran.com
1.3 Quality Assurance
Systran Corporate policy is to provide our customers with the highest quality products
and services. In addition to the physical product, the company provides documentation,
sales and marketing support, hardware and software technical support, and timely product
delivery. Our quality commitment begins with product concept, and continues after
receipt of the purchased product.
Systran’s Quality System conforms to the ISO 9001 international standard for quality
systems. ISO 9001 is the model for quality assurance in design, development, production,
installation and servicing. The ISO 9001 standard addresses all 20 clauses of the ISO
quality system, and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:
• Achieve, maintain and continually improve the quality of our products through
established design, test, and production procedures.
• Improve the quality of our operations to meet the needs of our customers,
suppliers, and other stakeholders.
• Provide our employees with the tools and overall work environment to fulfill,
maintain, and improve product and service quality.
• Ensure our customer and other stakeholders that only the highest quality product
or service will be delivered.
The British Standards Institution (BSI), the world’s largest and most respected
standardization authority, assessed Systran’s Quality System. BSI’s Quality Assurance
division certified we meet or exceed all applicable international standards, and issued
Certificate of Registration, number FM 31468, on May 16, 1995. The scope of Systran’s
registration is: “Design, manufacture and service of high technology hardware and
software computer communications products.” The registration is maintained under BSI
QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage
customers to contact us with questions, suggestions, or comments regarding any of our
products or services. We guarantee professional and quick responses to your questions,
comments, or problems.
1.4 Technical Support
Technical documentation is provided with all of our products. This documentation
describes the technology, its performance characteristics, and includes some typical
applications. It also includes comprehensive support information, designed to answer any
technical questions that might arise concerning the use of this product. We also publish
and distribute technical briefs and application notes that cover a wide assortment of
topics. Although we try to tailor the applications to real scenarios, not all possible
circumstances are covered.
Although we have attempted to make this document comprehensive, you may have
specific problems or issues this document does not satisfactorily cover. Our goal is to
offer a combination of products and services that provide complete, easy-to-use solutions
for your application.
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INTRODUCTION
Copyright 2001 1-3 DAC128V HARDWARE REFERENCE
If you have any technical or non-technical questions or comments (including software),
contact us. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight
Time.
• Phone: [phone] or [phone]
• E-mail: [email protected]
• Fax: [phone]
• World Wide Web address: www.systran.com
1.5 Ordering Process
To learn more about Systran products or to place an order, please use the following
contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern
Standard/Daylight Time.
• Phone: [phone] or [phone]
• E-mail: [email protected]
• World Wide Web address: www.systran.com
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INTRODUCTION
Copyright 2001 1-4 DAC128V HARDWARE REFERENCE
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Copyright 2001 2-1 DAC128V HARDWARE REFERENCE
2. PRODUCT OVERVIEW
2.1 Overview
The DAC128V is a singlewide IP Module board, conforming both mechanically and
electrically to the ANSI VITA/4-1995, American National Standard for IP Modules. For a
typical IP Module carrier that holds four IP Modules, it can provide up to 32 channels of
DACs for a single slot on a computer bus backplane, or be mixed with other IP Modules
for a more customized, modular I/O system solution.
The DAC128V maintains the highest possible accuracy by minimizing accumulative
errors through the use of the best parts for the tasks to be accomplished.
Figure 2-1 DAC128V Board
2.2 Features
• Eight independent channels of 12-bit resolution DACs in two groups of four
outputs scaled to one of eight possible voltage ranges between ±10 V, with no-
wait write and read-back accesses
• Jumper selectable output voltage ranges: 0 Þ+5 V, 0 Þ+10 V, -5 Þ0 V,
-5 Þ+5 V, -5 Þ+10 V, -10 Þ0 V, -10 Þ+5 V, -10 Þ+10 V
• Output current is ±20 mA (Max.) for ±10 V output (running on ±15 V power)
• Buffered reference outputs: -10 V, -5 V, +5 V, and +10 V
• Jumper selectable analog power sources: ±12 V from carrier, or ±15 V from I/O
connector (recommended for 10 V ranges)
• Integral and differential nonlinearities are ±1 LSB (Max.); settling time is 6 µs
(Typical); Slew rate of 2.2 V/µs (Typical)
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PRODUCT OVERVIEW
Copyright 2001 2-2 DAC128V HARDWARE REFERENCE
•
()
Vout Vref Vref Vref N low
high low
=+ −
_
__*
4096 (where N= decimal digital code)
• Straight binary coding; DAC output at Mid-scale on power-up.
2.3 Related Products
• Software: ‘C’ library and OS-9 device driver routines with documentation.
2.4 Block Diagram Description
IP Module
Logic Bus
Interface
& DAC
Control
Circuitry
QUAD
12-bit
DAC Channel 0
Vref
Generator
Channel 3
QUAD
12-bit
DAC Channel 4
Channel 7
I
P
M
O
D
U
L
E
L
O
G
I
C
B
U
S
I
P
M
O
D
U
L
E
I
/
O
Figure 2-2 DAC128V Simplified Block Diagram
Figure 2-2 presents a simplified block diagram of the DAC128V. On the left side is the IP
Module's Logic Bus connector through which all transfers between the IP Module carrier
and the DAC128V’s registers and data sources are conducted. The block labeled “IP
Module Logic Bus Interface and DAC Control Circuitry” contains the ID “PROM” data,
the DACs’ access detection and control logic, the IP Module transfer sequence/control
logic, and the data path gate control signals. All of this circuitry is implemented in one
small EPLD. The block labeled “Vref Generator” consists of a precision (+10.000)
voltage reference, a quad voltage (±10 V, ±5 V) derivation circuit with buffers, two sets
of high and low reference voltage selection blocks with buffers (one set per quad DAC),
and four reference voltage buffers with connections to the I/O connector (not shown in
this block diagram).
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PRODUCT OVERVIEW
Copyright 2001 2-3 DAC128V HARDWARE REFERENCE
Figure 2-3 Detailed Block Diagram
Each of the elements labeled “QUAD 12-bit DAC” consists of four 12-bit digital-to-
analog converters with output voltage buffers, individual high and low reference inputs
shared by all four DACs, double-buffered WRITE registers, and read-back gating. As
depicted in Figure 2-2, all eight DAC outputs have both direct connections, and series-
resistance connections (for applications with highly capacitive loads) to the I/O
connector. On the right side is the DAC128V’s I/O connector, providing sixteen DAC
analog outputs, four buffered reference outputs, two external power supply inputs, and 28
connections to the ground plane.
Figure 2-3 presents a detailed block diagram of the DAC128V. Again, on the left side is
carrier ↔IP Module interface via the IPDbus, the IPAbus, and the access Control
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PRODUCT OVERVIEW
Copyright 2001 2-4 DAC128V HARDWARE REFERENCE
signals. The block labeled “IPDbus DAC I/O GATEs” consists of a pair of bi-directional
bus transceivers for buffering the writes and quickly terminating read operations.
This second level “top” block diagram provides more detail to better understand the inner
functional elements of each of the quad DAC units, including the digital registration and
read-back capabilities, the buffered high and low voltage references, and the buffered
outputs to the I/O connector. Also provided in more detail (at the top of Figure 2-3) is the
ability to run this board using external (clean) power supplies, and the quad-reference
voltage generator, with individual buffers for the reference outputs to the I/O connector.
The table on the (upper half) left side of Figure 2-3 provides all of the eight valid voltage
ranges that can be selected per quad DAC unit, and their respective (centered) power-up
default voltage outputs.
2.5 Detailed Description
The DAC128V was developed using VHDL and Synthesis, targeted to an Altera EPLD,
schematic captured and integrated to standard integrated circuits, connectors, and discrete
components using VIEWLogic’s ViewDraw and associated packages.
2.6 Digital Components and their Functions
All IP Module Logic Bus transfers take place across J1, the IP Module Logic Connector,
located on the left side of all block diagrams. Refer to the ANSI/VITA 4-1995
specifications for details about the signals on this connector. This IP Module does not
support DMA or Interrupts, and has no memory accesses.
Figure 2-4 DAC128V Layout
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PRODUCT OVERVIEW
Copyright 2001 2-5 DAC128V HARDWARE REFERENCE
It performs no-wait ID reads, and no-wait reads from and writes to a short, eight-location
I/O map. Figure 2-4 is a physical assembly drawing for the DAC128V. Connector J1 is
located at the top of this drawing.
The DAC128V’s primary activity controller “S_DA128V” is housed within the
EPM7032LC44-10 EPLD located at U1 (just below J1 in Figure 2-4). It serves as the IP
Module transfer engine, whose responsibilities include:
• Detection of valid I/O and ID transfer operations within their respective, fully
decoded address ranges, including the support of HOLD cycles when generated
by a carrier.
• ID PROM emulation data pattern generation for ID read transfers.
• DAC chip select and read/write control signal generation for I/O reads and (16-
bit only) writes where QDAC#1 at U17 is enabled for the first four I/O locations
and QDAC#2 at U18 is enabled for the last four I/O locations.
• Direction with output-enable control signals for the data bus coupling (IPDbus
↔DACDbus) transceivers.
The data bus transceivers are implemented using a pair of 74FCT245SC devices, and are
designated U2 and U3 (just below J1 to the right of U1 in Figure 2-4). Normally an IP
Module does not require data bus transceivers. However, since the DACs’ specified time
for release of the data bus during read operations (low impedance →high impedance
state change time) exceeds the maximum time allowed by the ANSI/VITA 4-1995
specification, these transceivers are employed to quickly decouple the data buses.
2.7 DAC’s Voltage Ranges
The following description provides the user with the information necessary to properly
set the voltage output ranges for the DACs on the DAC128V. In general, there are three
high-side reference voltage levels and three low-side reference voltage levels per group
of four DAC outputs. There is one combination that is not logical for normal operations,
and this is the default shipment state of the DAC128V.
CAUTION: The DAC’s produce an invalid output when both high and low
references are set to ground; the voltage outputs remain at 0.000 V (±1.0 mV)
regardless of the binary code written to their respective registers.
This “shipped-state” configuration requires the user carefully ascertain and set the output
voltage ranges prior to using the DAC128V. The intent in shipping the DAC128V in this
benign state is to attempt to minimize the potential impact on the user’s external circuitry
to which the DAC128V is attached if it is simply installed upon arrival without properly
configuring the voltage range selections. Refer to the assembly drawing in Figure 2-4 for
the following four topic areas.
2.7.1 High Reference For QDAC#1
The high-side reference for the first four DAC outputs generated by QDAC#1 at U17 is
selected by placing the jumper shunt designated as H4 onto one pair of three jumper pads
designated as J5 (ground or 0.000 V), J6 (+5.000 V), or J7 (+10.000 V). The selection is
buffered by the Operational Amplifier at U13, which provides the high-side reference
voltage for QDAC#1. Using J6 or J7 is valid for any configuration. Use of J5 should
occur if, and only if, J8 is not used for the low reference for QDAC#1 (see subsection
2.7.2, below).
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PRODUCT OVERVIEW
Copyright 2001 2-6 DAC128V HARDWARE REFERENCE
2.7.2 Low Reference For QDAC#1
The low-side reference for the first four DAC outputs generated by QDAC#1 at U17 is
selected by placing the jumper shunt designated as H5 onto one pair of the three jumper
pads designated as J8 (ground or 0.000 V), J9 (-5.000 V), or J10 (-10.000 V). The
Operational Amplifier at U14 buffers the selection, which provides the low-side reference
voltage for QDAC#1. Using J9 or J10 is valid for any configuration. Use of J8 should
occur if, and only if, J5 is not used for the high reference for QDAC#1 (see subsection
2.7.1, above).
2.7.3 High Reference For QDAC#2
The high-side reference for the last four DAC outputs generated by QDAC#2 at U18 is
selected by placing the jumper shunt designated as H6 onto one pair of three jumper pads
designated as J11 (ground or 0.000 V), J12 (+5.000 V), or J13 (+10.000 V). The
Operational Amplifier at U15 buffers the selection, which in turn provides the high-side
reference voltage for QDAC#2. Using J12 or J13 is valid for any configuration. Use of
J11 should occur if, and only if, J14 is not used for the low reference for QDAC#2 (see
2.7.4, below).
2.7.4 Low Reference For QDAC#2
The low-side reference for the last four DAC outputs generated by QDAC#2 at U18 is
selected by placing the jumper shunt designated as H7 onto one pair of the three jumper
pads designated as J14 (ground or 0.000 V), J15 (-5.000 V), or J16 (-10.000 V). The
Operational Amplifier at U16 buffers the selection, which provides the low-side reference
voltage for QDAC#2. Using J15 or J16 is valid for any configuration. Use of J14 should
occur if, and only if, J11 is not used for the high reference for QDAC#2 (see 2.7.3,
above).
2.8 Reference Voltage Generation
The principle voltage reference is the LM369DM device at U8, and is based upon a
buried zener reference technology. Its nominal output voltage is +10.000 V, with a typical
error of ±70 ppm or ±700 µV. Its temperature coefficient over the product's specified
operating range is typically 5 ppm/°C. The multi-reference generator places a constant
load on this voltage reference, regardless of the demands of the DACs or the user’s loads
for the reference voltages supplied to the I/O connector. That load is a constant 500 µA.
The 0.1 µF capacitor at C16 provides additional noise filtering such that the noise voltage
is reduced to a typical value of 4 µVrms for the spectrum of 10 Hz through 10 kHz.
This reference has a relatively low drop-out voltage ceiling which enables proper
operation even when running the DAC128V from a carrier-sourced ±12 V supply. At
25°C, the minimum supply voltage is about +11 V, with it increasing to about +11.5 V for
the low temperature operations of the DAC128V, and down to about +10.5 V for the high
temperature end. The reference generator’s power supply connections are identical to
those of the remaining analog circuitry, and are switched to the externally supplied power
sources when jumpered to do so (see section 2.9, below).
The resistor divider network located at U7, in conjunction with the three Operational
Amplifiers at U10, U11, and U12 derive the remaining three reference voltages (not
supplied by U8): +5.000 V, -5.000 V, and -10.000 V. U7 contains four 10 KΩresistors
that have an absolute tolerance (not very important for this application) of ±0.1%, and a
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PRODUCT OVERVIEW
Copyright 2001 2-7 DAC128V HARDWARE REFERENCE
ratiometric tolerance of ±0.05% (very important) that track at 5 ppm/°C, in the worst
case.
All four reference voltages are buffered by the four Operational Amplifiers at U4, U5,
U6, and U9 to provide the user with outputs at the I/O connector for the voltages of
+10.00 V, -5.00 V, +5.00 V, and -10.00 V, respectively.
2.9 External Analog Supply
The DAC128V has provisions for running all of its analog circuitry off of an external
power source. There are at least two reasons for taking this action. First, some
applications may require “quieter” performance than is possible using the carrier’s power
sources. These are usually developed using noisier “switcher” technology than the older
“linear” techniques.
Second, and more importantly, the external power source provides greater accuracy.
While the reference circuitry is capable of running well from the +12 V provided by a
carrier, the DAC128V will not be able to maintain accuracy specifications when using
either of the +10 V rails to drive loads.
The DAC128V is shipped with the analog power selections configured for running from
the carrier's ±12 V supplies. This is implemented by the placement of the shunt H2 at the
two-by-two jumper block designated J3, and the shunt H3 at the jumper block J4 at the
top (towards the IP Module logic connector J1, away from the I/O connector J2) pair of
jumper pins. The printed circuit board’s silk-screen has these positions labeled as “+12v”
and “-12v”, respectively.
To operate the DAC128V from external (±12 →) ±15 V supplies:
• First ensure that the +15 V is wired to pin 48 of the I/O connector, and that -15 V
is wired to pin 45 of the I/O connector.
• Ensure its power supply ground is well connected to the DAC128V’s ground
connections at J2.
• Then, move jumper H2 to the bottom connections of J3, and move jumper H3 to
the bottom connections of J4 (bottom ≡away from the logic connector J1,
towards the I/O connector J2).
These positions are silk-screen labeled on the printed circuit board as “+15v” and “-15v",
respectively.
2.10 The Buffers
There are eleven analog buffers used on the DAC128V, located at U4, U5, U6, U9, U10,
U11, U12, U13, U14, U15, and U16. They are all configured as unity-gain (non-
inverting) voltage followers, all using the ultra-precision Operational Amplifier
#OP177GS. This device was selected because it provides performance characteristics that
approach those typically only possible with chopper-stabilized amplifiers, without the
usual “chopper” problems of noise and spikes, large size with mandatory external storage
capacitors, limited common-mode input ranges, and high expense.
The 60 µV maximum input offset voltage (over temperature) is so small that offset
voltage reduction circuitry implemented with trim-potentiometers would fail to provide
significant accuracy improvements over temperature due to the tracking problems of
dissimilar temperature coefficients between the Operational Amplifiers and the
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PRODUCT OVERVIEW
Copyright 2001 2-8 DAC128V HARDWARE REFERENCE
potentiometers. Therefore, all buffers are untrimmed, which also increases reliability and
reduces costs.
2.11 The DACs
Most of the functional and architectural topics concerning the DACs used have been
covered. For the sake of completeness, both DACs are supplied by Analog Devices,
#DAC-8412FPC.
.
NOTE: This technology was obtained from the former company “PMI” and that these
two devices, designated as U17 and U18, may be marked as PMI instead of AD or ADI.
The technical specifications in Appendix A, and the performance data presented in
Chapter 4 completely cover the remaining text concerning the DACs. Comparison of the
specifications published as tables by Analog Devices and to those presented in this
document will reveal certain anomalies. The specifications presented in Appendix A
include (beyond those of ADI) empirical data as well as information obtained from
characteristic curves, and not just those tabulated by ADI.
2.12 DAC128V Cleaning
If, for some reason, this product requires cleaning after delivery, most solvents are safe to
use that are based on: Fluorine, Chlorine, Aqueous, and Alcohol.
CAUTION: Do NOT use gasoline or thinner-type solvents on this product.
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Copyright 2001 3-1 DAC128V HARDWARE REFERENCE
3. INSTALLATION
3.1 Unpack the DAC128V
The contents of the DAC128V shipping package is listed in Table 3-1:
Table 3-1 Contents of DAC128V Shipping Package
Qty Description
1 DAC128V Printed Circuit Assembly
1 DAC128V Hardware Reference Manual *
The Printed Circuit Assembly is enclosed in an anti-static box. The box and the manual
are packaged together in a larger box. Save the shipping material in case the board needs
to be returned.
* One manual is shipped for each board ordered. Extra manuals may be purchased
by calling Systran or by mail. Use the prefix “BTMR-” followed by the product
order part number. (e.g., BTMR-DAC128V ).
3.2 Visually Inspect the DAC128V
Examine the DAC128V to determine if any damage occurred during shipping.
3.3 Install the DAC128V
.
NOTE: The DAC128V is an Electrostatic Sensitive Device (ESD). Install the DAC128V
on an anti-static workbench using good ESD practices to protect the IP Module and its
host carrier board.
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