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VMIVME-3111
48 ANALOG-TO-DIGITAL INPUTS
2-CHANNEL DIGITAL-TO-ANALOG OUTPUT BOARD
INSTRUCTION MANUAL
DOCUMENT NO. 500-003111-000 T
Revised June 19, 1995
VME MICROSYSTEMS INTERNATIONAL CORPORATION
12090 SOUTH MEMORIAL PARKWAY
HUNTSVILLE, AL 35803-3308
(205) 880-0444 FAX NO.: (205) 882-0859
1-800-322-3616
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500-003111-000
v
VMIVME-3111
48 ANALOG-TO-DIGITAL INPUTS
2-CHANNEL DIGITAL-TO-ANALOG OUTPUT BOARD
TABLE OF CONTENTS
Page
SECTION 1. GENERAL DESCRIPTION
1.1 INTRODUCTION..................................................................................1-1
1.2 FUNCTIONAL DESCRIPTION.............................................................1-2
1.3 REFERENCE MATERIAL LIST............................................................1-2
SECTION 2. PHYSICAL DESCRIPTION AND SPECIFICATIONS
SECTION 3. THEORY OF OPERATION
3.1 INTRODUCTION..................................................................................3-1
3.2 INTERNAL FUNCTIONAL ORGANIZATION........................................3-1
3.3 VMEbus CONTROL INTERFACE........................................................3-1
3.3.1 Read/Write Operations.........................................................................3-2
3.3.2 Bus Interrupter......................................................................................3-4
3.4 ADC CONTROL AND TIMING.............................................................3-4
3.4.1 Converter Controls and Status Flags ...................................................3-4
3.4.2 Throughput (Sample Rate) Factors......................................................3-7
3.4.3 Interleaved (Pipelined) Operation.........................................................3-7
3.4.4 Programmable Gain Amplifier ..............................................................3-8
3.5 FRONT PANEL (P3) ANALOG INPUTS...............................................3-8
3.5.1 P3 Low Pass Filters and Input Multiplexer............................................3-8
3.5.2 Current Loop Receiving Mode..............................................................3-8
3.6 REAR PANEL (P2) ANALOG INPUTS.................................................3-10
3.7 ANALOG INPUTS SIGNAL ROUTING.................................................3-10
3.7.1 Self-Test Multiplexer.............................................................................3-10
3.7.2 Analog Configuration Network..............................................................3-13
3.8 ANALOG OUTPUTS ............................................................................3-13
3.8.1 DACs....................................................................................................3-13
3.8.2 Output Buffers and Switches................................................................3-13
3.9 BUILT-IN-TEST....................................................................................3-14
3.9.1 Self-Test Multiplexers...........................................................................3-14
3.9.2 Loopback Testing of Inputs and Outputs..............................................3-15
3.9.3 Self-Test Standards..............................................................................3-15
3.9.4 Gain Autocalibration.............................................................................3-15
3.9.5 Zero Autocalibration .............................................................................3-15
3.10 BUILT-IN POWER CONVERTER ........................................................3-15
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500-003111-000
vi
TABLE OF CONTENTS (Continued)
Page
SECTION 4. PROGRAMMING
4.1 INTRODUCTION TO CONTROLLING THE VMIVME-3111 BOARD...4-1
4.2 CONTROL AND STATUS REGISTER DESCRIPTIONS.....................4-2
4.3 INITIALIZATION...................................................................................4-5
4.4 ANALOG INPUT MODES.....................................................................4-5
4.5 ACCESSING THE ANALOG INPUT CHANNELS................................4-6
4.5.1 Gain Selection......................................................................................4-6
4.5.2 Channel Selection ................................................................................4-7
4.5.3 Gain and Channel Selection Precedence.............................................4-8
4.6 CONTROLLING AND READING THE ADC.........................................4-9
4.6.1 ADC Timing..........................................................................................4-9
4.6.2 ADC Controls and Flags.......................................................................4-9
4.6.3 Reading ADC Codes............................................................................4-15
4.6.4 External Trigger Operation...................................................................4-17
4.7 CONTROLLING THE ANALOG OUTPUTS .........................................4-17
4.7.1 Writing to Outputs.................................................................................4-17
4.7.2 Off-Line Operation................................................................................4-18
4.8 SELF-TESTING THE VMIVME-3111 BOARD......................................4-18
4.8.1 Loopback Testing of Inputs and Outputs..............................................4-19
4.8.2 Calibration Self-Testing........................................................................4-22
4.8.3 Performing Autocalibration...................................................................4-25
4.9 BUS INTERRUPT CONTROL..............................................................4-25
4.9.1 Interrupt Control Register.....................................................................4-26
4.9.2 Interrupt Vector Register ......................................................................4-27
4.10 BOARD IDENTIFICATION REGISTER................................................4-28
SECTION 5. CONFIGURATION AND INSTALLATION
5.1 UNPACKING PROCEDURES..............................................................5-1
5.2 PHYSICAL INSTALLATION.................................................................5-1
5.3 BEFORE APPLYING POWER: CHECKLIST......................................5-1
5.4 OPERATIONAL CONFIGURATION.....................................................5-2
5.4.1 Factory-Installed Jumpers....................................................................5-2
5.4.2 Board Address and Address Modifier Selection...................................5-6
5.4.3 Analog Input Voltage Range Selection.................................................5-7
5.4.4 Current Loop Termination Resistors.....................................................5-7
5.4.5 Differential/Single-Ended Input Mode Selection...................................5-7
5.4.6 Analog Output Voltage Range Selection..............................................5-7
5.5 CALIBRATION .....................................................................................5-8
5.5.1 Equipment Required.............................................................................5-8
5.5.2 Internal Reference Voltage Calibration.................................................5-10
5.5.3 Programmable Gain Amplifier (PGA) Calibration .................................5-10
5.5.3.1 Voltage Input Option Calibration...........................................................5-10
5.5.3.2 Current Input Option Calibration...........................................................5-11
5.5.4 Manual ADC Calibration.......................................................................5-12
5.5.5 Analog Outputs Calibration...................................................................5-13
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500-003111-000
vii
5.6 CONNECTOR DESCRIPTIONS ..........................................................5-13
TABLE OF CONTENTS (Continued)
Page
SECTION 6. MAINTENANCE
6.1 MAINTENANCE...................................................................................6-1
6.2 MAINTENANCE PRINTS.....................................................................6-1
LIST OF FIGURES
Figure Page
1.2-1 VMIVME-3111 Functional Block Diagram ............................................1-3
3.3.1-1 VMEbus Control Signals and Interface Logic.......................................3-3
3.3.2-1 Bus Interrupt Logic...............................................................................3-5
3.4-1 ADC Timing Logic and Control Signals ................................................3-6
3.5-1 Analog Inputs and Signal Routing ........................................................3-9
3.6-1 32-Channel Filtered Analog Inputs.......................................................3-11
3.7-1 Self-Test Multiplexer.............................................................................3-12
3.8-1 Analog Output Channels ......................................................................3-14
3.9.4-1 Converter Channel Autocalibration.......................................................3-16
3.10-1 ±15 VDC Board Power.........................................................................3-17
4.6.2-1 Program Flowchart - Basic ADC Control Sequence.............................4-11
4.6.2-2 Program Example - Basic ADC Control Sequence...............................4-12
4.6.2-3 Program Flowchart - Pipelined ADC Control Sequence.......................4-13
4.6.2-4 Program Example - Pipelined ADC Control Sequence.........................4-14
4.8.1-1 Program Flowchart - Loopback Self-Test.............................................4-20
4.8.1-2 Program Example - Loopback Self-Test...............................................4-21
4.8.2-1 Program Flowchart - Converter Autocalibration....................................4-23
4.8.2-2 Program Example - Converter Autocalibration.....................................4-24
5.4-1 Jumper Locations.................................................................................5-3
5.5-1 Test Point and Adjustment Locations...................................................5-9
5.6-1 P2 Connector - Pin Configuration.........................................................5-15
5.6-2 P3 Connector - Pin Configuration.........................................................5-17
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500-003111-000
viii
TABLE OF CONTENTS (Concluded)
LIST OF TABLES
Table Page
4.1-1 Communications Register Map ............................................................4-1
4.2-1 Control Register Functions...................................................................4-2
4.2-2 Status Register Flags...........................................................................4-4
4.4-1 Analog Input Control Modes.................................................................4-6
4.5.2-1 Analog Input Channel Selection...........................................................4-8
4.6.3-1 ADC Format and Coding......................................................................4-16
4.7.1-1 DAC Data Format and Coding..............................................................4-18
4.8.2-1 Calibration Test Limits..........................................................................4-22
4.9-1 Interrupt Registers................................................................................4-26
5.4-1 Programmable Jumper Functions ........................................................5-4
5.4.2-1 Typical Board Address (FF8F00 HEX) Selection .................................5-6
5.4.3-1 Voltage Range Configuration ...............................................................5-7
5.6-1 P2 Connector (Rear Panel Inputs) Signal Assignments.......................5-16
5.6-2 P3 Connector Signal Assignments.......................................................5-18
APPENDIX
A Schematic and Assembly Drawing
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NOTICE
The information in this document has been carefully checked and is
believed to be entirely reliable. While all reasonable efforts to ensure accuracy
have been taken in the preparation of this manual, VMIC assumes no
responsibility resulting from omissions or errors in this manual, or from the use
of information contained herein.
VMIC reserves the right to make any changes, without notice, to this
or any of VMIC's products to improve reliability, performance, function, or design.
VMIC does not assume any liability arising out of the application or use
of any product or circuit described herein; nor does VMIC convey any license
under its patent rights or the rights of others.
For warranty and repair policies, refer to VMIC's Standard Conditions
of Sale.
AMXbus, BITMODULE, DMAbus, MEGAMODULE, NETbus, SRTbus,
TESTCAL, TURBOMODULE, UCLIO, UIOD, VMEmanager, VMEnet, VMEnet II,
WARPNET, and WinUIOC are trademarks of VME Microsystems International
Corporation. The VMIC logo and UIOC are registered trademarks of VME
Microsystems International Corporation. Other registered trademarks are the
property of their respective owners.
VME Microsystems International Corporation
All Rights Reserved
This document shall not be duplicated, nor its contents used for any
purpose, unless granted express written permission from VMIC.
Copyright © August 1988 by
VME Microsystems International Corporation
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iii
VMIC
SAFETY SUMMARY
THE FOLLOWING GENERAL SAFETY PRECAUTIONS MUST BE OBSERVED DURING ALL
PHASES OF THE OPERATION, SERVICE, AND REPAIR OF THIS PRODUCT. FAILURE TO
COMPLY WITH THESE PRECAUTIONS OR WITH SPECIFIC WARNINGS ELSEWHERE IN THIS
MANUAL VIOLATES SAFETY STANDARDS OF DESIGN, MANUFACTURE, AND INTENDED USE
OF THIS PRODUCT. VME MICROSYSTEMS INTERNATIONAL CORPORATION ASSUMES NO
LIABILITY FOR THE CUSTOMER'S FAILURE TO COMPLY WITH THESE REQUIREMENTS.
GROUND THE SYSTEM
To minimize shock hazard, the chassis and system cabinet must be connected to an
electrical ground. A three-conductor AC power cable should be used. The power
cable must either be plugged into an approved three-contact electrical outlet or used
with a three-contact to two-contact adapter with the grounding wire (green) firmly
connected to an electrical ground (safety ground) at the power outlet.
DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE
Do not operate the system in the presence of flammable gases or fumes. Operation of
any electrical system in such an environment constitutes a definite safety hazard.
KEEP AWAY FROM LIVE CIRCUITS
Operating personnel must not remove product covers. Component replacement and
internal adjustments must be made by qualified maintenance personnel. Do not replace
components with power cable connected. Under certain conditions,
dangerous voltages may exist even with the power cable removed. To avoid injuries,
always disconnect power and discharge circuits before touching them.
DO NOT SERVICE OR ADJUST ALONE
Do not attempt internal service or adjustment unless another person, capable of
rendering first aid and resuscitation, is present.
DO NOT SUBSTITUTE PARTS OR MODIFY SYSTEM
Because of the danger of introducing additional hazards, do not install substitute parts
or perform any unauthorized modification to the product. Return the product to VME
Microsystems International Corporation for service and repair to ensure that safety
features are maintained.
DANGEROUS PROCEDURE WARNINGS
Warnings, such as the example below, precede only potentially dangerous
procedures throughout this manual. Instructions contained in the warnings must be
followed.
WARNING
DANGEROUS VOLTAGES, CAPABLE OF CAUSING DEATH, ARE PRESENT IN THIS SYSTEM.
USE EXTREME CAUTION WHEN HANDLING, TESTING, AND ADJUSTING.
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500-003111-000
1-1
SECTION 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
The VMIVME-3111 Analog-to-Digital Converter (ADC) Board provides
both the stimulus and the response functions encountered in VME closed-loop
analog systems. Self-contained, with a resident 12-bit ADC and Digital-to-Analog
Converters (DACs), the VMIVME-3111 board represents a single board solution to
the analog input/output requirements of such VME applications as process control,
simulators, trainers, and supervisory control.
Because it does not rely upon additional supporting analog boards for
A/D or D/A conversion, the VMIVME-3111 simplifies the task of designing any VME
system which requires both analog inputs and outputs. The following brief
overview of the principal features illustrates the flexibility and performance that is
available with the VMIVME-3111 Board:
a. Thirty-two single-ended or 16 differential P2 analog inputs
b. Sixteen single-ended front panel analog input channels (cable
compatible with the 3V and 5V series signal conditioners)
c. Two analog output channels with 10 mA drive capability
d. Program-controlled off-line operation of analog outputs
e. Resident 12-bit ADCs and DACs
f. Input and output ranges selectable as 0 to +5 V, 0 to +10 V, ±2.5 V,
±5 V, and ±10 V
g. Optional low pass filters available for analog input noise elimination
h. ADC data coding program-selectable as either binary, offset binary, or
two's complement format
i. Automatic ADC timing simplifies programming
j. Stable on-board precision voltage references
k. Program-controlled autocalibration of gain and zero
l. 19 µs A/D conversion time (sample plus conversion)
m. 8 to 120 µs input acquisition time (gains of x1 to x500)
n. On-board smart controller permits interleaved (pipelined) operation
for maximum A/D conversion throughput
o. All inputs and outputs protected against line transients and short
circuits
p. Front panel FAIL indicator
q. Double Eurocard form factor
r. Individually coded/keyed VME connectors
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500-003111-000
1-2
1.2 FUNCTIONAL DESCRIPTION
The VMIVME-3111 ADC Board is a self-contained, 12-bit board. The
analog inputs can be configured either as 48 single-ended channels, or as 16
differential plus an additional 16 single-ended inputs. In addition to user-selectable
ranges, the VMIVME-3111 offers real-time programmable input gains of x1, x10,
x100, and x500. Autocalibration features permit program-controlled calibration of
zero offsets and input gain. A block diagram of the VMIVME-3111 is shown in
Figure 1.2-1.
All inputs are available with low pass filters for noise elimination.
Thirty-two of the input channels are available at the rear panel P2 connector; the
front panel P3 connector contains 16 input channels which are cable compatible with
the VMIC 3V/5V Series of signal conditioners. A resident smart controller permits
"pipelined" ADC operation, and automatically inserts all necessary settling delays.
These features reduce program control of the ADC to a simple handshake
sequence, and provide the highest possible throughput or sample rate, without
degrading accuracy.
Two wideband analog outputs can supply 10 mA of drive current over the
full output range of ±10 V, and can be operated off-line for self-test. Built-in-Test
(BIT) features permit off-line verification of all active components by routing the
analog outputs through the analog input multiplexers.
1.3 REFERENCE MATERIAL LIST
For a detailed explanation of the VMEbus and its characteristics, the
publication "The VMEbus Specification" is available from the following:
VITA
VFEA International Trade Association
10229 N. Scottsdale Road
Scottsdale, AZ 85253
(602) 951-8866
The following Application and Configuration Guides are available from
VMIC to assist in the selection, specification, and implementation of systems based
upon VMIC's products:
TITLE DOCUMENT NO.
Digital Input Board Application Guide 825-000000-000
Change-of-State Application Guide 825-000000-002
Digital I/O (with Built-in-Test) Product Line Description 825-000000-003
Synchro/Resolver (Built-in-Test) System Configuration Guide 825-000000-004
Analog I/O Products (with Built-in-Test) Configuration Guide 825-000000-005
Connector and I/O Cable Application Guide 825-000000-006
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500-003111-000
1-3
VOLTAGE
REFERENCE
P2
INPUT
MULTIPLEXER
LOW PASS
FILTERS
SELF-TEST
MULTIPLEXER
LOW PASS
FILTERS
P3
INPUT
MULTIPLEXER
ANALOG CONTROL
LOGIC
BUS INTERRUPT
LOGIC
VME
INTERFACE
LOGIC
POWER
CONVERTER
DUAL 12-bit
DAC
AUTO CAL
PGA
ANALOG BUFFER
AND
SWITCHES
T & H
AMP 12-bit
ADC
ADC TIMING
(FEEDBACK)
2
2
ON-LINE/OFF-LINE
ANALOG
OUTPUTS
(2)
10 mA
2
I/O CONN.
P2
ADC DATA
SETTLING
DELAY
GAIN TRACK CONV
CMD CONV
COMPL
12
S.E.
ZERO GAIN
±15 V
OUTPUT MONITOR
2
12 DIFF PAIRS
15
LO
HI
HI/LO
LO
ANALOG
CONFIGURATION
CONTROL
STDS
+10 V
4 DIFF PAIRS 1PAIR
I/O CONN.
P2
ANALOG
INPUTS
(32)
PSEUDO-DIFF RTN
16 DIFF
PAIRS
ANALOG
INPUTS
(16)
I/O CONN
P3
GND SENSE
16 S.E.
PIN-COMPATIBLE
WITH VMIC 3V/5V
I/O CABLES
VME
CONTROL
BUS
VMEbus
CONN.
P1
Figure 1.2-1. VMIVME-3111 Functional Block Diagram
DIFF
+5 V M3111/F1.2-1
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500-003111-000
2-1
SECTION 2
PHYSICAL DESCRIPTION AND SPECIFICATIONS
REFER TO 800-003111-000 SPECIFICATION
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500-003111-000
3-1
SECTION 3
THEORY OF OPERATION
3.1 INTRODUCTION
The VMIVME-3111 Board is a 12-bit, programmable gain,
Analog-to-Digital Converter (ADC) board which is designed to operate on the
standard VMEbus. With a resident 12-bit ADC, a Digital-to-Analog Converter
(DAC), and loopback self-test features, the board is self-contained and does not
require additional boards to provide high-quality analog input and output
functions. The VMIVME-3111 is a flexible system I/O element which offers
Built-in-Test and off-line operational features not found in many other products.
3.2 INTERNAL FUNCTIONAL ORGANIZATION
The VMIVME-3111 is divided into the following functional categories
which are illustrated in the functional block diagram shown in Figure 1.2-1. All
VMIVME-3111 functions are discussed in detail in subsequent sections of this
manual.
a. VMEbus Interface
b. Bus Interrupter
c. Analog Input Filters and Multiplexers
d. Analog Configuration Networks
e. Programmable Gain Amplifier
f. ADC Channel
g. Self-Test Multiplexer
h. DACs
i. Analog Output Buffers and Switches
j. Autocalibration
k. Power Converter
3.3 VMEbus CONTROL INTERFACE
The VMIVME-3111 communication registers are memory mapped as
16 (decimal), 16-bit words. The registers are contiguous and may be user-
located on any 32-byte boundary within the short I/O address space of the
VMEbus. The
board can be user-configured to respond to either short supervisory or
nonprivileged bus communications.
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500-003111-000
3-2
3.3.1 Read/Write Operations
During each READ/WRITE operation, all VMEbus control signals are
ignored unless the board selection comparator detects a match between the
on-board selection jumpers shown in Figure 3.3.1-1 and the address and address
modifier lines from the backplane. The appropriate board response occurs if a
valid match is detected, after which the open-collector DTACK interface signal is
asserted ON (LOW). Subsequent removal of the CPU READ/WRITE command
causes the board-generated DTACK signal to return to the OFF (HIGH) state.
After board selection has occurred, three groups of VMEbus signals
control READ/WRITE communications with the board:
a. Data Bus lines D00 to D15
b. Address lines A01, A02, A03, A04
c. Bus Control Signals:
1. WRITE*
2. DS0*, DS1*
3. SYS CLK
4. SYS RESET* ("*" = Asserted LOW)
Data bus lines are bidirectional and move data to or from the board
through a 16-bit data transceiver in response to control signals from the control
decoder. The data transceiver serves as a buffer for the internal data bus which
interconnects all data devices on the board.
Address lines A01 through A04 map the 16 communication registers
onto a 32-byte boundary within the VME address space (Section 4). The control
signals determine whether data is to be moved to the board (WRITE) or from the
board (READ). The control signals also provide the necessary data strobes (DS0,
DS1), and supply a 16 MHz clock (SYS CLK) for use by on-board timers. A SYS
RESET input resets all timers and flags.
Static controls are latched into the Control Register, and are used
primarily to establish the operational mode of the boards. Status flags, necessary
for monitoring and controlling the analog input multiplexer and the ADC, are read
through the Status Register. The Control and Status Registers (CSRs) are referred
to collectively as the Control and Status Register (CSR). Most of the Control
Register outputs can be monitored directly through the Status Register.
Each of the two analog output channels are controlled by writing 12-bit
right-justified data into a dedicated 16-bit READ/WRITE register. The lower 12 bits
(D00 to D11) of each Analog Output Register are loaded directly into the DAC for
the output, while the upper four bits (D12 to D15) are ignored.
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500-003111-000
3-3
CONTROL
DECODER
CONTROL
REGISTER
STATUS
REGISTER
CSR
DECODED
READ/WRITE
CONTROLS
REGISTERED
CONTROLS
STATUS
FLAGS
DATA
TRANSCEIVER INTERNAL
DATA BUS
DTACK
GENERATOR
A01 TO
A04
4
DTACK
(
SELECTION
COMPARISON
)
ADDRESS AND
ADDRESS MODIFIER
BOARD-SELECTION
COMPARATOR
21
A01 TO A15
AM0 TO AM5
VMEbus
(P1)
SELECTION JUMPERS
VME CONTROLS 5
• WRITE
• DS0
• DS1
• SYS CLK
• SYS RESET
16
16
D00 TO D15
Figure 3.3.1-1. VMEbus Control Signals and Interface Logic
M3111/F3.3.1-1
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500-003111-000
3-4
3.3.2 Bus Interrupter
To eliminate the processing overhead usually associated with ADC
polling, the VMIVME-3111 provides access to the VME interrupt structure through
the Bus Interrupter Module (BIM) shown in Figure 3.3.2-1. Control Registers for the
interrupter are located at relative addresses 10 and 18 (HEX) in the VMIVME-3111
assigned address space. These control registers are for INT0. Once the BIM has
been programmed and an A/D conversion has been started, the bus signals IACK,
IACKIN, and IRQ1 to IRQ7 control communication of the final NEW DATA RDY
flag to the VME controller. Details of interrupt control requirements are described in
Section 4.
3.4 ADC CONTROL AND TIMING
Control commands and status flags associated with controlling the ADC
are illustrated in Figure 3.4-1, and are described both in the following sections and
in Section 4.
3.4.1 Converter Controls and Status Flags
A conversion sequence is initiated by writing a "1" to the START
SETTLING and EN START CONV controls bits, and is composed of the following
consecutive time intervals:
a. Settling Delay
b. Tracking Interval
c. Analog-to-Digital Conversion
All ADC timing intervals discussed in this section are performed
automatically by the on-board smart controller. Program control of the converter
consists of basic handshake sequences.
The settling delay occurs directly after a state change has occurred in the
analog networks (such as selecting a new input channel), and represents the
settling time of the networks. After the settling delay has been completed, the
track-and-hold (T&H) amplifier (see Figure 1.2-1) enters the tracking mode and the
tracking interval begins.
During the tracking interval, the output of the T&H amplifier settles to a
value which is equal to its input voltage. The SETTLING BUSY flag is set HIGH at
the beginning of the settling delay, and is cleared LOW at the end of the tracking
interval. The CONV BUSY flag is set HIGH by the EN START CONV control bit,
and remains HIGH until the conversion sequence has been completed.
At the end of the tracking interval, the T&H amplifier enters the HOLD
MODE, in which the output of the amplifier is held at a constant level, and a CONV
CMD from the timing decoder causes the A/D conversion to begin. The A/D
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500-003111-000
3-5
OPEN-
COLLECTOR
BUFFERS
BUS
INTERRUPTER
MODULE
(BIM)
VME
INTERFACE
LOGIC
VMEbus
IACK*
IACKIN*
WRITE*
SYSCLK
A01
A02
A03
DATA RDY
INT 0
IDB00 TO
IDB07 8
DTACK
7
IRQ1 TO
IRQ7
IRQ1* TO
IRQ7*
DTACK*
7
Figure 3.3.2-1. Bus Interrupt Logic
M3111/F3.3.2-1
VMEbus
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500-003111-000
3-6
CONVERTER
CONTROL
LOGIC
BOARD RESET
SYS RESET
START SETTLING
EN START CONV
SETTLING BUSY
CONV BUSY
NEW DATA RDY
MICROSECOND
TIMER
CONV COMPL L
1 MHz CLK
TIMER BUS
TIMER RST
SHORT SETTLING
4
TRACKING
CONV CMD
SYS CLK
(16 MHz) CONVERTER
TIMING
DECODE
FROM
ADC
REGISTER
CONTROL
FROM CSR
REGISTERED
CONTROLS
FROM CSR
DECODED
READ/WRITE
CONTROLS
STATUS
FLAGS
TO CSR
TO ADC
Figure 3.4-1. ADC Timing Logic and Control Signals
M3111/F3.4-1
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500-003111-000
3-7
conversion digitizes the output of the T&H amplifier into a 12-bit data word, and
then terminates the conversion sequence. The CONV COMPL L flag from the
ADC is HIGH during the conversion, and is LOW otherwise.
Completion of the A/D conversion causes the NEW DATA RDY flag to
be set HIGH, indicating that valid data is present in the Converter Data Register
(Section 4). The action of reading the Converter Data Register resets the NEW
DATA RDY and CONV BUSY flags to the LOW ("0") state. ADC output coding
can be program-selected as either binary or two's complement.
3.4.2 Throughput (Sample Rate) Factors
Total system throughput (sample rate) FTcan be expressed generally
as:
FT= 1/ [n X (T1 + T2 + T3) ],
Where:
FT= Throughput (samples per second, per channel)
N = Number of channels
T1 = 3111 settling delay . . . . . . . . . .8-120 µs (Gain x1 to x500)
T2 = 3111 A/D conversion time . . 19 µs
T3 = CPU (controlling processor) time invested per channel
If CPU time is negligible relative to the conversion sequence, then T3
is zero, and the expression for maximum throughput (N=1) is:
FT(maximum) = 1 / (T1 + T2)
Maximum throughput for a gain of "x1" then, 37,037 samples per
second for a single input channel.
3.4.3 Interleaved (Pipelined) Operation
By allowing a new channel to settle before conversion of the
previously selected channel has been completed, T1will be eliminated from FT
(maximum). The VMIVME-3111 control logic permits this to take place if the
board is operated in the interleaved (pipelined) mode. Operating requirements
for the interleaved
mode are discussed in Section 4. By eliminating T1, maximum throughput in
this mode is:
FT(maximum) = 53 kHz.
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3-8
3.4.4 Programmable Gain Amplifier
Voltage gain of the ADC channel is program-selectable as x1, x10,
x100, and x500. The gain may be changed between channel selections by
controlling
the two least significant bits (LSBs) (D00, D01) in the Gain Control Register
located at relative address 0E (HEX). When changing the gain, refer to Section
4.5.3 "Gain and Channel Selection Precedence" for proper software sequence.
3.5 FRONT PANEL (P3) ANALOG INPUTS
Sixteen single-ended, high-level, analog input channels are available
at the front panel through the P3 connector. By connecting the analog return in
the remote device to the INPUT GROUND SENSE input (Figure 3.5-1) in the P3
connector, the single-ended lines can be operated as pseudo-differential inputs.
3.5.1 P3 Low Pass Filters and Input Multiplexer
The 16 front panel analog inputs are available with low pass filters.
The outputs from the filters are then multiplexed into the analog configuration
network
for selection into the ADC channel. To achieve maximum system accuracy with
filtered analog inputs, the sample rate should be limited to 300 Hz or less per
channel (4.8 kHz for 16 channels). Higher sample rates will produce reflected
"pumpback" currents at the inputs which can induce error voltages across the
filter input resistors.
Each of the P3 analog inputs is selected by the four LSBs (D00 to
D03) from the Control Register, these are shown as MUX A0 H through MUX A3
H in Figure 3.5-1. When set HIGH, CSR bit D07 selects the P3 multiplexer.
Channel "00" is routed through the self-test multiplexer before appearing at the
P3 multiplexer.
Signal pin assignments in the P3 connector are arranged for
cable-compatibility with the 3V and 5V series signal conditioner assemblies.
3.5.2 Current Loop Receiving Mode
P3 analog inputs may be used as current loop receivers by replacing
the filter capacitors with loop termination resistors. The resistance of the
terminators should be selected to produce a total termination power dissipation
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