Asahi KASEI AK4493 User manual

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1. General Description
The AK4493 is a new generation Premium 32-bit 2ch DAC with VELVET SOUNDTM technology,
achieving industry’s leading level low distortion characteristics. The newly adopted OSR-Doubler
technology establishes wide signal band, low power consumption and low distortion characteristics.
Moreover, the AK4493 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in a
wide range of applications. The AK4493 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal
for high-resolution audio source playback that is becoming widespread in network audio, USB-DAC, etc.
Application: AV Receivers, CD/SACD Players, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, IC-Recorder, Bluetooth
Headphone, HD Audio/Voice Conference Systems.
2. Features
THD+N: -113dB
DR, S/N: 123dB (2Vrms), 125dB (Large Amplitude Mode), 126dB (Mono Mode)
256 Times Over Sampling
Sampling Rate: 8kHz 768kHz
32-bit 8x Digital Filter
-Short Delay Sharp Roll-off, GD = 6.0/fs,
-Short Delay Slow Roll-off, GD = 5.0/fs
-Sharp Roll-off
-Slow Roll-off
-Low Dispersion Short Delay Filter
-Super Slow Roll-off
High Tolerance to Clock Jitter
Low Distortion/ Low Noise High Performance Differential Amplifier Output
Large Amplitude Output Mode
DSD64, DSD128, DSD256, DSD512 Input Support
-Filter1 (fc = 39kHz, DSD64 mode), Filter2 (fc = 76kHz, DSD64 mode)
Digital De-emphasis for 32, 44.1 and 48kHz sampling
Soft Mute
Digital Attenuator (255 levels and 0.5dB step + mute)
Mono Mode
External Digital Filter Interface
Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I2S, DSD, TDM
Master Clock
8kHz ~ 32kHz: 256fs or 384fs or 512fs or 768fs or 1152fs
8kHz ~ 54kHz: 256fs or 384fs or 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 32fs or 48fs or 64fs or 96fs
~ 768kHz: 16fs or 32fs or 48fs or 64fs
3-wire, I2C-bus Register Control Interface, or Pin Control
Power Supply:
TVDD = AVDD = 3.0 3.6V (by internal LDO), VDDL/R = 4.75 ~ 5.25V
TVDD = AVDD = DVDD 3.6V (by external supply), DVDD = 1.7V 1.98V
VDDL/R = 4.75 ~ 5.25V
Operational Temperature: -40 ~ 85 °C
AK4493
Quality Oriented 32-Bit 2ch DAC

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Digital Input Level: CMOS
Package: 48-pin LQFP

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3. Table of Contents
1. General Description........................................................................................................................ 1
2. Features.......................................................................................................................................... 1
3. Table of Contents............................................................................................................................ 3
4. Block Diagram................................................................................................................................. 5
5. Pin Configurations and Functions................................................................................................... 6
■Pin Configurations.............................................................................................................................. 6
■Pin Functions ..................................................................................................................................... 7
■Handling of Unused Pin..................................................................................................................... 9
6. Absolute Maximum Ratings.......................................................................................................... 10
7. Recommended Operating Conditions .......................................................................................... 11
8. Electrical Characteristics .............................................................................................................. 12
■Analog Characteristics..................................................................................................................... 12
■DSD Mode........................................................................................................................................ 14
■Sharp Roll-Off Filter Characteristics................................................................................................ 15
■Slow Roll-Off Filter Characteristics.................................................................................................. 17
■Short Delay Sharp Roll-Off Filter Characteristics............................................................................ 19
■Short Delay Slow Roll-Off Filter Characteristics.............................................................................. 21
■Low Dispersion Short Delay Filter Characteristics.......................................................................... 23
■DSD Filter Characteristics................................................................................................................ 25
■DC Characteristics........................................................................................................................... 25
■Switching Characteristics................................................................................................................. 26
■Timing Diagram................................................................................................................................ 30
9. Functional Descriptions................................................................................................................. 35
■D/A Conversion Mode (PCM Mode, DSD Mode, EXDF Mode) ...................................................... 37
■D/A Conversion Mode Switching Timing ......................................................................................... 38
■System Clock................................................................................................................................... 39
■Audio Interface Format .................................................................................................................... 45
■Digital Filter...................................................................................................................................... 55
■De-emphasis Filter (PCM) ............................................................................................................... 55
■Output Volume (PCM, DSD and EXDF Modes; Register Control Mode only)................................ 56
■Gain Adjustment Function (PCM, DSD and EXDF Modes; Register Control Mode only).............. 57
■Zero Detection (PCM, DSD and EXDF Modes; Register Control Mode only) ................................ 57
■LR Channel Output Signal Select, Phase Inversion Function (PCM, DSD and EXDF Modes)...... 59
■Sound Quality Adjustment Function (PCM, DSD, EXDF; Register Control Mode only)................. 59
■DSD Signal Full-Scale (FS) Detection............................................................................................. 60
■Automatic Mode Switching Function (PCM/EXDF ⇔DSD Mode; Register Control Mode only).... 63
■Soft Mute Operation (PCM, DSD, EXDF)........................................................................................ 71
■LDO.................................................................................................................................................. 72
■Shutdown Switch.............................................................................................................................. 72
■Analog Output Overcurrent Protection............................................................................................. 72
■Power Up/Down Function................................................................................................................ 73
■Power-OFF/Reset Function............................................................................................................. 77
■Synchronize Function (PCM, EXDF)............................................................................................... 80
■Register Control Interface................................................................................................................ 82
■Register Map.................................................................................................................................... 86
■Register Definitions.......................................................................................................................... 88
10. Recommended External Circuits.................................................................................................. 96
11. Package...................................................................................................................................... 101
■Outline Dimensions (48-pin LQFP)................................................................................................101
■Material & Terminal Finish.............................................................................................................101
■Marking...........................................................................................................................................102

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12. Ordering Guide ...........................................................................................................................103
■Ordering Guide............................................................................................................................... 103
13. Revision History..........................................................................................................................103
IMPORTANT NOTICE............................................................................................................................104

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4. Block Diagram
MCLK
SDATA/DSDL/DINL
SMUTE/CSN
BICK/DCLK/BCK
SD/CCLK/SCL
SLOW/CDTI/SDA
VSSR
VDDR
PDN
AVDD
SCF
SCF
Clock
Divider
DVSS
DVDD
SSLOW/WCK
ACKS/
CAD1
PSN
DIF0/
DZFL
DIF2/
CAD0
VSSL
VDDL
VCML
AOUTRN
VCMR
VREFHL
VREFLL
VREFLR
VREFHR
AVSS
AOUTLP
AOUTLN
AOUTRP
PCM
Data
Interface
External
DF
Interface
Control
Register
Bias
Vref
LRCK/DSDR/DINR
DEM0
DIF1/
DZFR
DATT
Soft Mute

Modulator
Volume bypass
DSDD bit “1”
Normal path
DSDD bit “0”
I2C/INV
LDO
LDOE
TVDD
De-emphasis
&
Interpolator
DSD Data
Interface
&
DSD Filter
MCLK
Stop
Detection
TESTE
Figure 1. Block Diagram

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5. Pin Configurations and Functions
■Pin Configurations
37
36
38
39
40
41
42
43
44
45
46
47
35
34
33
32
31
30
29
28
27
26
DVDD
1
2
PDN
3
BICK/DCLK/BCK
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
13
Top View
48
12
24
25
AK4493
SDATA/DSDL/DINL
SMUTE/CSN
LRCK/DSDR/DINR
SSLOW/WCK
SD/CCLK/SCL
SLOW/CDTI/SDA
DIF0/DZFL
DIF1/DZFR
DEM0
LDOE
INV/I2C
PSN
VREFHR
VREFHR
OUTRP
VREFLR
VREFLR
NC
VCMR
ACKS/CAD1
AOUTLN
VDDL
VDDL
VSSL
VSSL
VSSR
VSSR
VDDR
VDDR
AOUTRN
AOUTRP
VCML
VREFLL
VREFLL
VREFHL
VREFHL
AVSS
MCLK
DVSS
TVDD
AVDD
1
NC
AOUTLP
NC
1
DIF2/CAD0
TESTE
Figure 2. Pin Layout

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■Pin Functions
No.
Pin Name
I/O
Function
1
DVDD
O
(LDOE pin = “H”)
LDO OutputPin, This pin should be connected to DVSS with 1.0µF (+/-50%).
This pin is prohibited to connect other devices.
-
(LDOE pin = “L”)
1.8V Power Input Pin
2
PDN
I
Power-Down Mode Pin
When at “L”, the AK4493 is in power-down mode and is held in reset.
The AK4493 must always be reset upon power-up.
3
BICK
I
Audio Serial Data Clock Pin in PCM Mode
DCLK
I
DSD Clock Pin in DSD Mode
BCK
I
Audio Serial Data Clock Pin in EXDF Mode
4
SDATA
I
Audio Serial Data Input Pin in PCM Mode
DSDL
I
DSD Lch Data Input Pin in DSD Mode
DINL
I
Lch Audio Serial Data Input Pin in EXDF Mode
5
LRCK
I
L/R Clock Pin in PCM Mode
DSDR
I
DSD Rch Data Input Pin in DSD Mode
DINR
I
Rch Audio Serial Data Input Pin in EXDF Mode
6
SSLOW
I
Digital filter setting in Pin Control Mode
WCK
I
Word Clock input pin in EXDF Mode
7
SMUTE
I
Soft Mute Pin in Pin Control Mode
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
CSN
I
Chip Select Pin in Register Control Mode, I2C = “L”
8
SD
I
Digital filter setting in Pin Control Mode
CCLK
I
Control Data Clock Pin in Register Control Mode, I2C = “L”
SCL
I
Control Data Clock Pin in Register Control Mode, I2C = “H”
9
SLOW
I
Digital filter setting in Pin Control Mode
CDTI
I
Control Data Input Pin in Register Control Mode, I2C = “L”
SDA
I/O
Control Data Clock Pin in Register Control Mode, I2C = “H”
10
DIF0
I
Digital Input Format 0 Pin in PCM Mode
DZFL
O
Lch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
11
DIF1
I
Digital Input Format 1 Pin in PCM Mode
DZFR
O
Rch Zero Input Detect Pin in Register Control Mode (Internal pull-down pin)
12
DIF2
I
Digital Input Format 2 Pin in PCM Mode
CAD0
I
Chip Address 0 Pin in Register Control Mode
13
PSN
I
Pin or Register Control mode Select Pin (Internal pull-up pin)
“L”: Register Control Mode, “H”: Pin Control Mode
14
INV
I
L/R channel Output Polarity Select Pin in Pin Control Mode
I2C
I
I2C mode select pin in Register Control Mode
15
DEM0
I
44.1k De-emphasis Enable Pin in Pin Control Mode. “L”: Enable, “H”: Disable
16
LDOE
I
Internal LDO Enable Pin. “L”: Disable, “H”: Enable

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No.
Pin Name
I/O
Function
17
ACKS
I
Master Clock Auto Setting Mode Pin in Pin Mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CAD1
I
Chip Address 1 Pin in Serial Control Mode
18
TESTE
I
Test Mode Enable pin. (Internal pull-down pin)
19
VREFHR
I
Rch High Level Voltage Reference Input Pin
20
VREFHR
I
Rch High Level Voltage Reference Input Pin
21
VREFLR
I
Rch Low Level Voltage Reference Input Pin
21
VREFLR
I
Rch Low Level Voltage Reference Input Pin
23
VCMR
-
Right channel Common Voltage Pin,
Connect this pin to VREFLR with a 10uF electrolytic capacitor.
This pin is prohibited to connect to any other load.
24
NC
-
No internal bonding.
Connect to GND.
25
AOUTRP
O
Rch Positive Analog Output Pin
26
AOUTRN
O
Rch Negative Analog Output Pin
27
VDDR
-
Rch Analog Power Supply Pin, 4.75 5.25V
28
VDDR
-
Rch Analog Power Supply Pin, 4.75 5.25V
29
VSSR
Ground Pin
30
VSSR
Ground Pin
31
VSSL
Ground Pin
32
VSSL
Ground Pin
33
VDDL
-
Lch Analog Power Supply Pin, 4.75 5.25V
34
VDDL
-
Lch Analog Power Supply Pin, 4.75 5.25V
35
AOUTLN
O
Lch Negative Analog Output Pin
36
AOUTLP
O
Lch Positive Analog Output Pin
37
NC
-
No internal bonding.
Connect to GND.
38
VCML
-
Left channel Common Voltage Pin,
Connect this pin to VREFLL with a 10uF electrolytic capacitor.
This pin is prohibited to connect to any other load.
39
VREFLL
I
Lch Low Level Voltage Reference Input Pin
40
VREFLL
I
Lch Low Level Voltage Reference Input Pin
41
VREFHL
I
Lch High Level Voltage Reference Input Pin
42
VREFHL
I
Lch High Level Voltage Reference Input Pin
43
NC
-
No internal bonding.
Connect to GND.
44
AVDD
-
Analog Power Supply Pin,
(LDOE pin = “H”) AVDD = 3.0 3.6V, (LDOE pin = “L”) AVDD = DVDD 3.6V
45
AVSS
-
Ground Pin
46
MCLK
I
Master Clock Input Pin
47
DVSS
-
Ground Pin
48
TVDD
-
Digital Power Supply Pin,
(LDOE pin = “H”) TVDD = 3.0 3.6V, (LDOE pin = “L”) TVDD = DVDD 3.6V
Note 1. All input pins except internal pull-up/down pins must not be left floating.
Note 2. The AK4493 must be reset by the PDN pin when changing control mode (Pin Control ⇔Register
Control) by the PSN pin.
Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings.

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■Handling of Unused Pin
Unused I/O pins must be connected appropriately.
(1) Pin Control Mode (PCM mode only)
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
TESTE
Connect to DVSS
or Open
(2) Register Control Mode
1. PCM Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
WCK, DEM0
Connect to DVSS
TESTE
Connect to DVSS
or Open
DZFL, DZFR
Open
2. DSD Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
WCK, DEM0
Connect to DVSS
TESTE
Connect to DVSS
or Open
DZFL, DZFR
Open
3. EXDF Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
DEM
Connect to DVSS
TESTE
Connect to DVSS
or Open
DZFL, DZFR
Open
4. With I2C-Bus
Classification
Pin Name
Status
Digital
CSN
Connect to DVSS

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5. Pull-up, Pull-down Pin List
Classification
Pin Name
Internal connection
pull-up pin (typ = 100kΩ)
PSN
TVSS
pull-down pin(typ = 100kΩ)
DZFL, DZFR, TESTE
DVSS
6. Absolute Maximum Ratings
(AVSS = DVSS = VSSL = VSSR = VREFLL = VREFLR = 0V;Note 4)
Parameter
Symbol
Min.
Max.
Unit
Power
Supplies:
Digital I/O
Digital Core
Clock Interface
Analog
|AVSS DVSS| (Note 5)
|AVSS VSSL| (Note 5)
|AVSS VSSR| (Note 5)
|DVSS VSSL| (Note 5)
|DVSS VSSR| (Note 5)
|VSSL VSSR| (Note 5)
TVDD
DVDD
AVDD
VDDL/R
GND
GND
GND
GND
GND
GND
0.3
0.3
0.3
0.3
-
-
-
-
-
-
4.0
2.5
4.0
6.0
0.3
0.3
0.3
0.3
0.3
0.3
V
V
V
V
V
V
V
V
V
V
Voltage
Reference
“H”voltage reference
(Note 6)
“L”voltage reference
VREFHL/R
VREFLL/R
-0.3
-0.3
VDDL/R+0.3
Or 6.0
+0.3
V
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Digital Input Voltage
(Note 7)
VIND
0.3
TVDD+0.3
or 4.0
V
Ambient Temperature (Power supplied)
Ta
40
85
C
Storage Temperature
Tstg
65
150
C
Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
Note 6. Regarding VREFHL/R pins, maximum value which is lower value (VDDL/R+0.3) or 6.0V.
Note 7. Regarding Digital input pins, maximum value which is lower value (VDDL/R+0.3) or 4.0V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.