Asahi KASEI AK5602A User manual

[AK5602A]
MS1285-E-00 2011/02
- 1 -
”Suitable for three phase, 3 wired or 4 wired
energy metering or energy monitoring application
”Provide less than 0.1 % active & reactive energy
error over a dynamic range of 1000 to 1,
compatible with IEC 0.5S
”Provide instantaneous active power, reactive
power and apparent power
”Provide voltage RMS, current RMS, voltage
instantaneous value, current instantaneous value
and power factor in each phase.
”Provide less than 0.5 % voltage RMS, current
RMS and power factor error
”Provide very accurate 90 degree phase shifter over
45Hz to 65Hz input frequency range, which is
used for reactive power calculation
”Provide minute input voltage monitoring function
”Wide phase adjust. range between V & I (11 °)
”Provide positive and negative power indication
”Built-in temperature sensor
”Single power supply (3 V or 5V)
”48LQFP
AK5602A is one of the most advanced and functional
LSIs for multi phase energy measurement.
Current and voltage signals through CT, Hall sensor, or
Shunt Resistors are converted into digital signal with
18bit ADC.
Instantaneous voltage and current in each phase is
multiplied and is added in total phases.
The value changes into active power after passing
through LPF and added with the value of a light load
register. After this value is compared with the value of
rated standard value register, it outputs pulses in
proportion to the calculation.
Regarding reactive power, input current is precisely
shift by 90 degree and multiplied with respective voltage
input signal. It outputs pulses in the same manner of
active power calculation.
And apparent power can be selectively derived from
either active power and reactive power calculation or
VRMS x IRMS calculation and it outputs pulses as the
result of calculation.
V
”
”
”
”
”
”
”
± °
”°
”
”
a
CIF
C_IF
CI
F
Φ Φ Φ
Energy Metering LSI for multi phase, high accurate application
AK
5602A

[AK5602A]
MS1285-E-00 2011/02
- 2 -
Ich 1
I1P
I1N
PGA
x1 to x32 Sigma-
Delta
Mod.
FIR
+
RPL
Active
Power to
Frequency
Conversion
+
+
RPST
RPO
TPST
TPO
I2P
I2N
Vch 1
V1P
FIR
V2P
Ich 2
Vch 2
F1
F2
PXP
-1
-XP
XP+RPL
-
XP+TPL
Reference
Voltage
VCOM
VREFO
VREFI
Oscillator
XOUT
XIN
RST
STBY
RDY
Serial to pararell
conversion control
SCLK
CS
DI
DO
BVSS
AVDD
AVSS
DVDD
DVSS
Reactive
(Apparent )
Power to
Frequency
Conversion
+
+
RQST
RQO
TQST
TQO
XQ
-1
-XQ
XQ+RQL
-XQ+TQL
Ich 3
I3P
I3N
Vch 3
V3P
VIN
PGA
x1 to x4
F3
I2
V2
HPF
P1
I1
V1 HPF
90 degree
phase
shifter
Q1
+
Q
Temp.
sensor
Phase
Adj.
DIS
TPL
RQL
TQL
Gain
Adj.
LPF
LPF
RMS
Value
Apparent
Power
Power
Factor
S1
PF1
Calculation
Block (ch1)
P2
Q2
S2
PF2
P3
Q3
S3
PF3
I3
V3
Calculation
Block (ch2)
Calculation
Block (ch3)
TEST1
TEST2
TEST3
V3 Frequency
Output
V1 Frequency
Output
V2 Frequency
Output
VS
Sigma-
Delta
Mod.
Phase
Adj.
Gain
Adj.
Vn
Threshold
x
x
x
x
x

[AK5602A]
MS1285-E-00 2011/02
- 3 -
PGA
(Programmable
Gain Amp)
Current Input Gain selection (from ×1 to ×32)
Voltage Input Gain selection (from ×1 to ×4)
This PGA becomes operative with RST =STBY = “H”
Sigma Delta
Modulator
Sigma Delta Modulator with 3 channel differential inputs.
This modulator becomes operative with RST =STBY = “H”
Phase Adjuster This adjusts the phase difference between current IF and voltage IF.
This phase shifter becomes operative with RST =STBY = “H”
FIR Filter LPF. This produces 18 bit ADC data in current side and 16 bit ADC data
in voltage side from the sigma delta modulator.
This Filter becomes operative with RST =STBY = “H”
HPF This HPF is a selectable filter. It removes the DC part arising from DC
offset of ADC or input signal.
In a case of passing through the DC part of input signal, only DC offset o
f
ADC can be removed by calibration command. This HPF is not selected
in the default setting. This HPF becomes operative with RST =STBY
= “H”
Gain Adjustment Values of input current and input voltage can be adjusted against ideal
values with a gain adjustment (full-scale) command.
This adjustment becomes operative with RST =STBY = “H”
90 degree phase
shifter
90-degree phase shifter.
This shifter becomes operative with RST =STBY = “H”
RMS value calculator It calculates RMS value from an instantaneous signal.
This calculator becomes operative with RST =STBY = “H”
LPF LPF.
This filter becomes operative with RST =STBY = “H”
Apparent power
calculator
Apparent power can be derived from either VRMS ×IRMS calculation or
active power & reactive power calculation.
This calculator becomes operative with RST =STBY = “H”
Power Factor Power factor can be derived from active power & apparent power
calculation.
Power factor becomes operative with RST =STBY = “H”
Active energy to
frequency conversion
Positive active energy or negative active energy is converted into
respective frequency, which is proportional to its active energy.
This block becomes operative with RST =STBY =DIS = “H”

[AK5602A]
MS1285-E-00 2011/02
- 4 -
Reactive energy to
frequency conversion
Positive reactive energy or negative reactive energy is converted into
respective frequency, which is proportional to its reactive energy.
This block becomes operative with RST =STBY =DIS = “H”
Temperature sensor This block measures the temperature of AK5602A.
This block becomes operative with RST =STBY =DIS = “H”
Frequency pulse
outputs
Each voltage input is digitized according to each threshold value, and
digitized frequency is output.
This block becomes operative with RST =STBY = “H”
Reference voltage
generator
This block generates 1.17V reference voltage.
This block becomes operative with RST =STBY = “H”
Oscillator The crystal oscillator which oscillates around 12.9024MHz is connected.
This block becomes operative with RST =STBY = “H”
Serial to parallel
controller
Serial interface to CPU.
This block becomes operative with RST = “H”
L L L All blocks are off
H L L Only serial to parallel controller block is operative.
H H L All blocks except power to frequency conversion blocks are operative.
H H H All blocks are operative.

[AK5602A]
MS1285-E-00 2011/02
- 5 -
AI : Analog input DI : Digital input PWR : Power
AO : Analog output DO : Digital output GND : Ground
1
RST DI Reset input ( Schmitt trigger input )
All circuits become inoperative with “L” level input.
A
ll registers including input or output registers,
controlling registers, data registers are initialized.
2 STBY DI Standby input ( Schmitt trigger input )
All circuits except serial pararell controller block become
inoperative with “L” level input after RST = “H”
It is possible to write in and read registers through the
serial to the parallel conversion controller.
3 DIS DI Disable input ( Schmitt trigger input )
Active energy to frequency conversion and reactive energ
y
to frequency conversion blocks are stopped and data
registers in those blocks are initialized with “L” level input
after RST =STBY = “H”.
4 TQO DO Negative reactive power pulse output
“H” pulse is output when accumulated negative reactive
energy value is over the setting standard value.
This pin becomes inoperative when RST = “L” or
STBY = “L” or DIS = “L”.
5 TQST DO Negative reactive energy flag output (This pin is not use
d
in IEC mode.)
“H” level is output when an interval of output pulses at
TQO is under the setting starting value.
This pin becomes inoperative when RST = “L” or
STBY = “L” or DIS = “L”.
6 RQO DO Positive reactive energy pulse output
“H” pulse is output when accumulated positive reactive
power value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.
7 RQST DO Positive reactive energy flag output (This pin is not used in
IEC mode.)
“H” level is output when an interval output pulses at RQO
is under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.

[AK5602A]
MS1285-E-00 2011/02
- 6 -
8 DVSS GND Digital ground.
9 DVDD PWR Digital power.
10 TPO DO Negative active energy pulse output.
“H” pulse is output when accumulated negative active power
value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
11 TPST DO Negative active power flag output.
“H’ level is output when an interval of output pulses at TPO
is under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY
= “L” or DIS = “L”.
12 TEST1 DI Internal use only. Connects to DVSS.
13 RPO DO Positive active energy pulse output
“H” pulse is output when accumulated positive active power
value is over the setting standard value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
14 RPST DO
Positive active power flag output.
“H” level is output when an interval output pulses at RPO is
under the setting starting value.
This pin becomes inoperative when RST = “L” or STBY =
“L” or DIS = “L”.
15 TEST2 DI Internal use only. Connects to DVSS.
16 TEST3 DI Internal use only. Connects to DVSS.
17 BVSS GND Silicon base reference GND. Connects AVSS.
18 XOUT AO
19 XIN AI
Crystal oscillator connection.
Connects 12.8 MHz oscillator.
20 AVDD PWR Analog power.
21 AVSS GND Analog ground.
22
VREFO AO Reference voltage output, 1.17V
It outputs with the reference to AVSS. This output usuall
y
connects to VREFI pin. Connects 4.7uF (under 10uF)
electrolytic capacitor and 0.1uF ceramic capacitor between
this pin and AGND. This output is an internal use only and
should not be connected to circuits outside the IC.

[AK5602A]
MS1285-E-00 2011/02
- 7 -
23 VREFI AI Reference voltage input.
It usually connects to VREFO.
An outside VREF is connected between this pin and AVSS in
a case that an inside VREF of the IC is not used.
24 VCOM AO Common voltage output, 1.17V.
It feeds a common voltage to an internal block of the IC.
It should not be connected to the outside circuits of the LSI.
Connect 0.1uF ceramic capacitor between this pin and AVSS.
25 VS AO Controlling voltage output for input switches.
It generates the voltage which controls input switches
referenced to AVSS in ON and OFF state.
This is an internal use only. It should not be connected to the
outside circuits of the IC. Connects 0.1uF ceramic capacitor
between this pin and AVSS.
26 VIN AI Voltage side common analog negative input.
27 V3P AI Voltage side ch3 analog positive input.
28 V2P AI Voltage side ch2 analog positive input.
29 V1P AI Voltage side ch1 analog positive input.
30 NC NC No connection. Connects to AVSS.
31 I1P AI Current side ch1 analog positive input.
32 I1N AI Current side ch1 analog negative input.
33 I2P AI Current side ch2 analog positive input.
34 I2N AI Current side ch2 analog negative input.
35 I3P AI Current side ch3 analog positive input.
36 I3N AI Current side ch2 analog negative input.
37 NC NC No connection. Connects to AVSS.
38 RDY DO Reading approval pin of registers
The content of registers can be read when this pin becomes
“low”.
This pin becomes “high” when RST = “L” or STBY = “L” or
DIS = “L”.

[AK5602A]
MS1285-E-00 2011/02
- 8 -
39 CS DI Serial interface selection input (Schmitt trigger input)
Serial interface become operative with “L” level input at
this pin while RST = “H”.
40 SCLK DI Serial data clock input
41 BVSS GND Silicon base reference GND. Connects to AVSS.
42 DVSS GND Digital ground.
43 DVDD PWR Digital power.
44 DI DI Serial data input
This DI pin becomes valid with CS = “L” while RST =
“H” and it inputs data in synchronization with the risin
g
edge of the clock at SCLK pin. Stored data is transferre
d
into the respective register in the synchronization with
the rising edge of CS .
45 DO DO Serial data output
This DO pin becomes valid with CS = “L” while RST =
“H” and it outputs data in synchronization with the
falling edge of the clock at SCLK pin.
This DO pin becomes a high impedance state except
CS = “L” while RST = “H”.
46 F3 DO V3 frequency output
A
rectangular wave produced by a waveform shapin
g
circuit is output.
This pin becomes low level when RST = “L” or STBY
= “L”.
47 F2 DO V2 frequency output
A
rectangular wave produced by a waveform shapin
g
circuit is output.
This pin becomes low level when RST = “L” or STBY
= “L”.
48 F1 DO V1 frequency output
A rectangular wave produced by a waveform shapin
g
circuit is output.
This pin becomes low level when RST = “L” or STBY
= “L”.

[AK5602A]
MS1285-E-00 2011/02
- 9 -
DVDD -0.3 +6.5Power supply voltage
AVDD -0.3 +6.5
V
Ground level AVSS
DVSS
BVSS
0
V
Voltage reference level
Input current IIN ±10 mA Except power pin
Analog input
voltage1
VINA1 -0.3 (AVDD)+0.3 V
Analog input
voltage2
VINA2 -3.0 +3.0 V I1P, I1N, I2P,
I2N, I3P, I3N,
V1P, V2P, V3P, VIN
Digital input voltage
I IND -0.3 DVDD+0.3 V
Storage temperature T stg -50 125
°C
Note ) It may cause a permanent damage to the device if used beyond listed conditions.

[AK5602A]
MS1285-E-00 2011/02
- 10 -
AVDD 2.7 5.25Power supply
voltage
DVDD 2.7 5.25
V
Note 1
Analog reference
input voltage
VREF
1.11
1.17
1.23
V
Note 2
Analog input
maximum voltage
VAIN
MAX
-1.0
1.0
V
Note 3
A
nalog input
volta
g
e
VAIN -FS +FS V Note 4
Operating
tem
p
erature
Ta -40 85
°C
Note 1: -0.1V ≤DVDD - AVDD ≤+0.1V
Note 2: This is a case when outside reference voltage is connected to VREFI.
1.17V±5%
Note 3: This range of analog input signal is to be calculated.
Note 4:
VAIN = ( AINP ) - (AINN)
AINP: V1P, V2P, V3P; AINN: VIN
Gain ×1 : -FS = -1.0V, +FS = 1.0V
×2 : -FS = -0.5V, +FS = 0.5V
×4 : -FS = -0.25V, +FS = 0.25V
AINP: I1P, I2P, I3P; AINN: I1N, I2N, I3N
Gain ×1 : -FS = -1.0V, +FS = 1.0V
×2 : -FS = -0.5V, +FS = 0.5V
-
×8 : -FS = -0.125V, +FS = 0.125V
-
×16 : -FS = -0.0625V, +FS = 0.0625V
-
×24 : -FS = -0.0417V, +FS = 0.0417V
-
×32 : -FS = -0.03125V, +FS = 0.03125V
”
-
”
-

[AK5602A]
MS1285-E-00 2011/02
- 11 -
Conditions: Ta=25°C, AVDD=DVDD=5.0V,
VREF = 1.17V, XCLK = 12.9024MHz,
Signal frequency = 50Hz, Measured bandwidth = 10 to 1.5kHz;
Unless otherwise specified.
Voltage side
Input range
Gain setting :
×4 (12 dB)
×2 (6 dB)
×1 (0 dB)
±0.95
±0.25
±0.5
±1.0
±1.05
Vp-p Note 5
Input impedance 350 kΩNote 6
Note 5: Only applicable for V (voltage) input. This is a full-scale value of analog input voltage
(VAIN= (AINP) - (AINN)). VIN is usually connected to AGND and each analog input
voltage is added with reference to VIN.
Note 6: Input impedance between AINP (V1P, V2P, V3P) and AINN (VIN).
Minimum value is when gain is set at ×4 (12dB). Input impedance is reversed
proportional to the gain setting.
Current side
Input range
Gain setting:
×32 (30dB)
×24 (27.6dB)
×16 (24 dB)
×8 (18 dB)
×4 (12 dB)
×2 (6 dB)
×1 (0 dB)
±0.95
±0.0313
±0.0417
±0.0625
±0.125
±0.25
±0.5
±1.0
±1.05
Vp-p Note 7
Input impedance 200 kΩNote 8
Note 7: Only applicable for I(current) input (differential input). This is a full-scale value of
analog input voltage (VAIN = (AINP) - (AINN)).
Note 8: Input impedance between AINP (I1P, I2P, I3P) and AINN (I1N, I2N, I3N).
Minimum value is when gain is set at ×8 (18dB). Input impedance is reversed
proportional to gain setting.

[AK5602A]
MS1285-E-00 2011/02
- 12 -
Resolution 16 bit
S/N+D 65 dB Note 9
Isolation between
current and voltage
100
dB
Note 10
Crosstalk between
voltage channels
100 dB
Power factor adjustment
range between current
and voltage
-613.84 613.84 us Note 11
Power factor adjustment
accuracy between
current and voltage
1.24
us
Note 12
ADC period 3.15 kHz Note 13
Note 9: This is the value when analog input signal is applied at -6dB of full scale value with
PGA = 0 dB. This is the ratio between RMS value of input signal and summation of
RMS values of all frequencies from 10Hz to 1.5kHz excluding the input signal.
Note 10: This is the isolation value between voltage side ADC and current side ADC.
Note 11: This is the delay adjustment range of voltage side against current side.
+ side setting delays starting point of A/D conversion at voltage side against starting
point of A/D conversion at current side in the range of 0us to +613.84us, while - side
setting delays starting point of A/D conversion at current side against starting point of
A/D conversion at voltage side in the range of 0us to +613.84us. This enables the delay
adjustment range at voltage side against current side from -613.84us to +613.84us.
Please note that when the delay adjustment is changed from + to - or - to + during the
operation of the IC, A/D conversion data becomes uncontinuous.
Note 12: Delay adjustment step is 1.24us.
Note 13: ADC period is 3.15kHz at every channel.

[AK5602A]
MS1285-E-00 2011/02
- 13 -
Resolution 18 bit
S/N+D 65 dB Note 14
Isolation between
current and voltage
100
dB
Note 15
Crosstalk between
current channels
100 dB
ADC period 3.15 kHz Note 16
Note 14: This is the value when analog input signal is applied at -6dB of full scale value with
PGA = 0 dB. This is the ratio between RMS value of input signal and summation of
RMS values of all frequencies from 10Hz to 1.5kHz excluding the input signal.
Note 15: This is the isolation value between voltage side ADC and current side ADC.
Note 16: ADC period is 3.15kHz at every channel.
VREF output level 1.11 1.17 1.23 V Note 17
V
REF temperature drift 30 ppm/°CNote 18
Note 17: Output level of VREFO. It outputs 1.17V±5% with reference to AVSS.
Note 18: The temperature drift of VREFO output level.
Temperature range -40 85 °C
Resolution 1
°C Note 19
Accuracy
±5 °C Note 20
Note 19: Resolution value when the value of temperature register is read from the register.
Note 20: This is the difference between the value of temperature register and real value at
25°C.

[AK5602A]
MS1285-E-00 2011/02
- 14 -
Power consumption 18 40 70 mW Note 21
Standby Current 1 1 20 uA Note 21
Note 21: TYP1 is the value at AVDD = DVDD = 3.0V and TYP2 is the value at AVDD = DVDD
= 5.0V. Consumption current is measured on condition of which all digital inputs
are connected to DVDD or DVSS and all analog inputs are connected to analog
input bias level. It does not contain output current. AVDD = DVDD = 2.7V to 5.25V.
Ta = -40 to 85°C, AVDD=DVDD=2.7V to 5.25V,
XCLK=12.9024 MHz (Filter characteristics is proportional to the frequency of XCLK.)
±0.008dB 45 66
Pass band
+0.008dB
-0.910dB
0
1500
Hz
Attenuation
level at stop band
at 10.0kHz 74.0 dB
-3 dB 1.3
-0.5 dB 3.6
-0.1dB 8.7
-0.004 dB 45
Frequency
response
-0.002 dB 66
Hz
Phase shift value 45 to 66Hz 1.13 1.66 degree

[AK5602A]
MS1285-E-00 2011/02
- 15 -
Phase shift
value
45 to
66Hz 89.98 90 90.02 degree Note 22
Gain error 0
to 1500Hz ±0.001 dB Note 23
Note 22: Phase difference between two inputs.
Note 23: Gain error between input and output of 90 degree phase shifter.
Pass band ±0.1dB 0 0.4 Hz
Attenuation
level at stop
band
at 100Hz 60 dB
Ta = -40 to 85°C, AVDD=DVDD=2.7 to 5.25V
High level input voltage VIH 0.7(DVDD) V Note 24
Low level input voltage VIL 0.3(DVDD) V Note 24
High level output voltage
Iout=0.5mA
For RPO/TPO/RQO/TQO
Iout=2mA
VOH (DVDD)-0.4
Low level output voltage
Iout=-0.5mA
For RPO/TPO/RQO/TQO
Iout=-2mA
VOL 0.4 V
Input leak current IIN
±
10 uA
Note 24: Except TEST1, TEST2, and TEST3 pins.

[AK5602A]
MS1285-E-00 2011/02
- 16 -
Ta=-40 to 85°C, AVDD=DVDD=2.7~5.25V,
CL=20pF, XCLK=12.9024MHz
Serial Clock Frequency fSCLK SCLK 4 MHz
tSCKH SCLK 100 ns Fig.1“H” pulse width
tOUTH RPO,TPO
RQO,TQO
59.5
±
0.2
us Fig.3
Note 25
tSCKL SCLK 100 ns
Fig.1
tRSTL RST 1
tSTBL STBY 1
“L” pulse width
tDISL DIS 1
us
Fig.4
tCCKH CS
→
SCLK 100
Hold time
tCKDH SCLK
→DI
50
ns
Fig.1
tCKDS SCLK
→DI
50
Setup time
tCCKS CS
→
SCLK
100
ns
Fig.1
tCKDV SCL
K
→DO
80 ns Fig.2
Data output
tCKDZ
SCL
K
→DO
200
Note 25: In case of PULSW11-0=000H (default).

[AK5602A]
MS1285-E-00 2011/02
- 17 -
RPO
TPO
tOUTH
Fig.3
RST
STBY tRSTL
0.7DVDD
0.3DVDD
Fig.4
tSTBL
0.7DVDD
0.3DVDD
tCCKS
0.7DVDD
0.3DVDD
tCC K H
CS
SCLK
tSCK H
tSCKLtCK DS tCKDH
DI
0.7DVDD
0.3DVDD
Fig.1
0.7DVDD
0.3DVDD
tCCKS
0.7DVDD
0.3DVDD
tCC K H
CS
SCLK
tSCK H
tSCKLtCKDV
tCK DZ
DO
Fig.2
In writing
In reading
High-Z High-Z
DIS
tDISL
RQO
TQO
(Note) Reading and writing control is executed by commands of Control setting register,
ADD.’21h’.

[AK5602A]
MS1285-E-00 2011/02
- 18 -
Ph1
RST : L
Operation of all circuits including serial interface and oscillator
circuits is halted and digital circuits including input / output register,
control register and data register are initialized. At the same time F1,
F2, F3, RPO, TPO, RQO,TQO, TPST, RQST and TQST becomes “L”
level and DO becomes high impedance state.
Ph2
STBY : L
RST : H
A serial interface circuit (input / output register) becomes active and it
is possible to write in and read registers.
Ph3
DIS : L
STBY : H
RST : H
All circuits except active power to frequency conversion circuit and
reactive power to frequency conversion circuit become active. At this
moment, RPO, TPO, RQO, TQO, RPST, TPST, RQST and TQST keeps
“L” level.
Oscillator circuit starts oscillation with RST =STBY = “H” and ADC
sequence is started. It normally needs before oscillation
frequency and HPF are stabilized. The accuracy of ADC and
calibration is not guaranteed during this period.
Ph4
DIS : H
STBY : H
RST : H
All circuits become active, but the changing of the state from Ph3 to
Ph4 must be done after 300mS are being elapsed in Ph3 state.
AVDD=DVDD
RST
STBY
DIS
ph1 ph2 ph3 ph4 ph3 ph4
Fig.5 Power on sequence

[AK5602A]
MS1285-E-00 2011/02
- 19 -
It is possible to access a serial interface circuit with RST = “H”, CS = “L”.
By applying a serial clock at SCLK pin, input data is written into an input shift register.
Input data consists of 7 bits of address, one bit “L” level writing command and 16 bits data
strings.
The state of DI is sampled at rising edge of SCLK for 24 times after CS = “L” and
transferred into the shift register. 16 bits data, which have been written into input shift
data register will be transferred to the corresponding control register at the rising edge
of CS .
In a case that the number of clocks of SCLK is either less than 24 times or more than 25
times, input data will not be transferred into the corresponding control register.
The number of clocks of SCLK should be applied for 24 times even if the writing data
consist of less than 16 bits format. And SCLK must be started at “H” state and ended at
“H” state.
CS
SCLK
1 2 8 9 23 24710
DI A6 A5 A0 L D15 D14 D1 D0
Fig.6 writing timing to registers
Starting address (8bit) Writing in data

[AK5602A]
MS1285-E-00 2011/02
- 20 -
It is possible to access a serial interface circuit with RST = “H”, CS = “L”.
By applying a serial clock at SCLK pin, input data is written into an input shift register.
Input data consists of 7 bits of address, one-bit “H” level reading command is followed.
The state of DI is sampled at rising edge of SCLK for 8 times after CS = “L”, transferred
into the shift register and specified the starting address.
In the starting address, the first 7 bits show the address of the control register which data
should be stored and the next 1 bit shows either reading or writing. If the bit is “H”, it means
reading. If the bit is “L”, it means writing.
In case that data specified with only one address is read (when ADD. ‘21h’, bit1=’1’), 16 bit
data which is specified by reading indication register is loaded into the shift register from
the controlling register at the first falling edge of SCLK following after the starting address
and data is output at DO pin. After that, data is continuously output at every SCLK’s falling
edge and 16-bit data, which have been loaded into the output shift register are output.
Furthermore, the next 16-bit data at the next address are output if SCLK is input
continuously. This makes it possible to read data from registers continuously without
readdressing.
If SCLK is applied even after, data at the last address ADD. ‘59h’ being output, the LSI
outputs “L” as far as CS pin remains “L”. DO pin becomes high impedance state when
CS pin is controlled at “H” state. In a case that CS pin becomes “H” state before all data
being output, DO pin becomes high impedance state and reading procedure is halted.
In addition, SCLK must be started at “H” state and ended at “H” state.
When the data loading period into the output register and data renewal period coincide
each other, the bit15 (INVALID) of data at ADD. ‘21h’ becomes “H” level. The INVALID bit
at ADD. ‘21h’ keeps “H” level until the content of ADD. ‘21h’ will have been read, and it will
be cleared after the reading.
CS
SCLK
1 2 8 9 23 24710
DI A6 A5 A0 H
Fig.7 Reading timing from controlling registers
Starting address(8bit) Readin g data output
DO D15 D14 D1 D0
Hi-Z Hi-Z
"L"
All registers are initialized and the initial values are loaded with “L” level at RST pin.
Table of contents
Other Asahi KASEI Measuring Instrument manuals
Popular Measuring Instrument manuals by other brands

Essilor Instruments
Essilor Instruments SL 650 user manual

Siemens
Siemens sitrans PROBE LU instruction manual

PCB Piezotronics
PCB Piezotronics J320C03 Installation and operating manual

GRAPHTEC
GRAPHTEC midi LOGGER GL800 quick start guide

ADC
ADC advantage connect 6024N Instructions for use

geo-FENNEL
geo-FENNEL ECOLINE EL 515 manual