Atari 810 User manual

JULY I.980
FSOlSO5i
REV. 1

TABLE OF CONTENTS
SPECIFICATIONS
THEORY OF OPERATION
BLOCK DIAGP&m & SCHEMATICS
1.
2.
3.
4.
5
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6.
7.
8.
9.
10.
FLOPPY QUICKCHECK
TROUBLESHOOTI’NG GUIDE
DISASSPMELY/REASSE:.!BLY
ADJUSTllESTS
PARTS LISTS
APPENDIX
INDEX
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10.
TECIip!ICAL SPECIFICATIONS
Uses ANSI standard Sk inch diskettes in a
soft sectored format.
40 tracks at 48 TPI track.density.
Sinqle density (FM), single sided recording.
Over 905 bytes storage per diskette.
709 sectors of 128 bytes each.
Mininum data access time: 236 milliseconds.
Averaye data transfer rate: 6000 bits per second.
Automatic stand-by capability (built in
microprocessor).
Up to four Drives can.be daisy chained to a single
400/800 Computer Console (w/minimum 16K RAM)
via select switches at the rear of the Drive.
Drives directly interface with the ATARI 400/800
Computer Console (16K RAM) or indirectly through
the ATARI 850 Interface Module or 820 Printer.-
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THEORY OF OPERATION
The ATARI 400/800 Computer Console with 16K of RAM
installed connects directly to the 810 Floppy Disk
Drive.
The Drive may also be daisy chained through
the 820 Printer 6r the 850 Interface Module. up to
four Disk Drives can be connected to a single Console.
Refer to the Disk Drive Operators Manual for instal-
lation and oDerating instructions.
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The ATARI 810 Floppy Disk Drive consists of the
following major sections:
*Data Input/Output and Manipulation
*
Data Interface
* .Read/Write and Erase Heads
’ *
Stepper Motor and Logic
*
Diskette Drive Motor and Logic
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Power supply
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DATA INPUT/OUTPUT AND MANIPUWTION SECTION
Data, control commands and a VCC/RDY signal from the
Computer Console enter the Disk Drive through cithcr
of the two serial I/O connector jacks at the rear of,
the Drive chassis.
Each of the three main signal input lines are buffered
for,statlc protection an&to reduce power consumption
on the 800 I/O lines.
Data is sent by the Console in serial format, with
checksums accompanying the data for validity verification.
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The Drive’s PIA is primarily a buffering and signal
formatting device, with no decision making or compu-
tational capability. It is responsible for the
following:
*
Applying the Console’s serial outputs to the
Data 2nd Address Busses when requested by the
Drive’s Microprocessor Unit (NW).
*
Assisting in the control of the Read/Write
and Erase fiead position by buffering commands
sent to the Stepper Motor Logic.
*
Assisting in control of the Diskette Drive
,Motor Logic.
*
Providing 128 bytes of R&M for temporary
storage of status inforrnltion and data sent by
the Data Interface Section for application
to the HP".
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The MPU rjrovides the.primary decision making and
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cocputational capabilities for the Disk Drive.
The
Drive’s ?:PV is responsible for the following:
*
Controlling data transfers, through its
control over the Conmon Data and Address
Busses.
*
Intfr?retinq and controlling the accon,plishment
of Console commands (temporarily stored
in FLXM) and Disk Drive operating instructions
(permanently stored in ROM).
*
Controlling the Stepper, Disk Drive and llotor
Logics, which are buffered by the PIA.
The Drive’s ROM contains specific operating instructions
used by the CPU to accomplish a variety Qf-functions.
These functions include telling the Disk controller
(1771-01) what task to perform.
.
The Drivs’s RXY is used by the CPU for temporary storage
of both data and system information.
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The Drive’s Data Output Buffer transfers the
formatted data through the PIA to the’Data (out)
line going to the Computer Console.
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The Drive’s Power c’p Logic circuit resets the !&PU,
PIA and Data Interface Section whenever the Disk Drive
is turned on. The RESET references the electrical
circuits to their starting conditions. Additionally,
the Power Vp Logic circuit locks the Data Output
Buffer off during a short period when the Drive is
turned on. This prevents random pulses generated by
. the Drive’s circuitry (during the initializing period)
from being sent to the Console.
The Drive’s Clock circuitry generates both a crystal
contolled 1 MHz. and a 500 KHz. clock signal.
The
1 MHZ.
signal is used by the Data Interface Section.
The 500 KIIz. signal is used both as a clock signal to
the MPU, and to tjme data exiting from the Data Input/
Output and Manipulation Section into th&Data Interface
Section.
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DATA INTERFACE SECTION
The major element of the Data Interface Section is a
Floppy Disk Controller (FDC).
The FDC is a highly
specialized microprocessor. It-is responsible for
the following activities:
*
Combining data, timing and data validity
pulses into the serial format to be recorded.
*
Separating the above and Troviding "he otitput
data in parallel during a read qeration.
* Controlling the IGrite and Erase LoTic circuitry
during a write operation.
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Genrratinq the data validity codes (called
Cyclic Redundancy Chpcks - or CXC’s) during a
write operation,
and checking them during a
read operation.
The Drive’s Write and Erase Logic circuitry is ccntrolled
by,
and receives its data from the FDC.
Initially, the
Data Gate converts the leading edge of each pulse
(data, clock, etc.) into a single
correanqnding change
of si::ned level. These levels then determine the polarity
of the Drive’s currents applied to the Read/:irite Head
through the High and Low level Drives, The Write Driver
limits the write currents.
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The Data Gate converts ach pulse’s
lending edge iilto a logic level
change, as shown.
Basically, this is the signal applied to the head during a mite
operatim.
The high levels out of the Data Gore turn on the High
level Driver, and fhc low levels turn an the Low level Driver.
The Write and Erase Gate turns on both the Write and
Erase Drivers during a write oneration, and turns them
off during a read operation. The Erase Driver drives
the Erase Head durinq a write operation. See
the Read/
wrrte and Erase Head discussion for further information.
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Major elements of the Drive’s Read Data Conditioning
circuitry are:
*
Pifferential Amp - Initial amplification of
Read/Write Head signals.
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Differentiator - Squaring up the two differ-
ential amp outputs.
*
Zero Crossing Detector - The singleoutput
changes level whenever the two ,180 out-of-
phase input signals cross their zero axis
coincidentally (eliminates false pulses caused
by Read/Write Head signal decay, rather than
intentional signal level changes).
*
Symmetry Amp - Ensures exact zero’referencing of
the signal.
*
Time Domain Filter - Trims and further shapes
the signal.
*
Signal Gate - Produces a single pulse out for each
logic level transition.at its input. This results
in the reproduction of the original FDC signal.
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During a read operation the Read/Write Head produces
two 180 out-of-phase signals. These are very weak,
highly distorted versions of the original signals pro-
duced by the Write Logic Data Gate. The Read Data
Conditioning circuitry must amplify, square up and
filter the read signals to reproduce the origiqal
serial string of bits produced by the FIX.
This re-
produced signal is returned to the FDC by the Read
Data Conditioning circuitry.
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Two 180’ out-of-phase sinnals zre
generated by che’head du;ing a read
operation and amplified hy the
Di,ffercntial Amplifier.
The Differentiacor squares the two
out-of-phase signals.
The Zero Axis Crossing Detector
provides a single output, further
squared and now without any signal
decay effects.
The Time Domain Filter provides a
signal with very sharp leading and
trailing edges.
The Pulse Rfgeneraror converts each
logic level change into a single pulse,
recreating the original signal produced
by the WC during the write operation.
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The Drive’s Write Protect circuit senses the presence
or absence of a special notch in one side of the diskette
casing. R write protected diskette’s notch will be
covered with an opaque tape. The circuit is basically
an LED/photo transistor sensor, whose’ output is buf-
fered before being applied to the FDC.
With an unprotected diskette,
the ser.sor signal allows
the FDC to write data onto the diskette.
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STEPPER MOTOR AND LOGIC
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The Stc?p~er Motor is a four phase motor with a 3.6"
rotor rotation per step.
The motor has a total of 100
POlf.5, providing 100 rotor steps for the motor’s full
360° rotation. Each step change in the motcr is w-a&slated;
through a steel band connection, to a single track
change far the Read/Write and Record Bead assembly. ,The
diskette is divided into 40 tracks, so-the full range
of the Stepper !.:otor is not used.
The Stepper Logic is controlled from the PIA.
The four
PIA signals are logic levels acting as the Stepper
Motor's foilr phase inputs.
These levels, in their
various possible combinations, drive the
Stepptir Motor to
reposition the head assembly from track to track.
The Stepper Motor is supplied with a nominal 3 to 10 VAC
fron the Pcwer Supply.
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