Atmel AT90S8414 User manual

AT90S8414
Preliminary 4-1
Contents
PIN CONFIGURATIONS ............................................................................................................................................... 4-5
BLOCK DIAGRAM......................................................................................................................................................... 4-6
DESCRIPTION................................................................................................................................................................. 4-7
Pin Descriptions.............................................................................................................................................................. 4-8
Crystal Oscillator............................................................................................................................................................ 4-9
AT90S8414 AVR RISC MICROCONTROLLER CPU.......................................................................................... 4-10
Architectural Overview ................................................................................................................................................ 4-10
The General Purpose Register File............................................................................................................................... 4-11
THE X-REGISTER, Y-REGISTER AND Z-REGISTER .......................................................................................................................................4-12
The ALU - Arithmetic Logic Unit................................................................................................................................ 4-13
The Downloadable Flash Program Memory................................................................................................................. 4-13
The SRAM Data Memory - Internal and External ....................................................................................................... 4-13
The Program and Data Addressing Modes................................................................................................................... 4-15
REGISTER DIRECT, SINGLE REGISTER Rd......................................................................................................................................................4-15
REGISTER DIRECT, TWO REGISTERS Rd AND Rr..........................................................................................................................................4-15
I/O DIRECT..............................................................................................................................................................................................................4-16
SRAM DIRECT........................................................................................................................................................................................................4-16
SRAM DIRECT WITH DISPLACEMENT.............................................................................................................................................................4-16
SRAM/REGISTER INDIRECT ...............................................................................................................................................................................4-17
SRAM/REGISTER INDIRECT WITH PRE-DECREMENT .................................................................................................................................4-17
SRAM/REGISTER INDIRECT WITH POST-INCREMENT................................................................................................................................4-17
CONSTANT ADDRESSING USING THE LPM INSTRUCTION........................................................................................................................4-18
DIRECT PROGRAM ADDRESS, JMP AND CALL .............................................................................................................................................4-18
INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL ...............................................................................................................................4-18
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL............................................................................................................................4-19
The EEPROM Data Memory........................................................................................................................................ 4-19
Memory Access Times and Instruction Execution Timing.......................................................................................... 4-19
I/O Memory.................................................................................................................................................................. 4-22
THE STATUS REGISTER - SREG.........................................................................................................................................................................4-23
THE STACK POINTER - SP...................................................................................................................................................................................4-24
Reset and Interrupt Handling........................................................................................................................................ 4-24
RESET SOURCES ...................................................................................................................................................................................................4-25
POWER-ON RESET ................................................................................................................................................................................................4-26
EXTERNAL RESET ................................................................................................................................................................................................4-27
WATCHDOG RESET..............................................................................................................................................................................................4-27
INTERRUPT HANDLING ......................................................................................................................................................................................4-28
THE GENERAL INTERRUPT MASK REGISTER - GIMSK...............................................................................................................................4-28
THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK..................................................................................................................4-29
THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR ......................................................................................................................4-29
EXTERNAL INTERRUPTS....................................................................................................................................................................................4-30
INTERRUPT RESPONSE TIME.............................................................................................................................................................................4-32
MCU CONTROL REGISTER - MCUCR................................................................................................................................................................4-32
Sleep Modes.................................................................................................................................................................. 4-32
IDLE MODE.............................................................................................................................................................................................................4-33
POWER DOWN MODE ..........................................................................................................................................................................................4-33
TIMER / COUNTERS.................................................................................................................................................... 4-33
The Timer/Counter Prescaler........................................................................................................................................ 4-33
The 8-Bit Timer/Counter0............................................................................................................................................ 4-34
THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0...............................................................................................................................4-35
THE TIMER COUNTER 0 - TCNT0.......................................................................................................................................................................4-36
THE OUTPUT COMPARE REGISTER 0 - OCR0.................................................................................................................................................4-36
The 16-Bit Timer/Counter1.......................................................................................................................................... 4-36
THE TIMER/COUNTER1 CONTROL REGISTER A - TCCR1A ........................................................................................................................4-39

4-2 AT90S8414 Preliminary
THE TIMER/COUNTER1 CONTROL REGISTER B - TCCR1B.........................................................................................................................4-39
THE TIMER/COUNTER1 - TCNT1H AND TCNT1L...........................................................................................................................................4-40
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1AH AND OCR1AL.........................................................................................4-41
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1BH AND OCR1BL.........................................................................................4-41
THE TIMER/COUNTER1 INPUT CAPTURE REGISTER - ICR1H AND ICR1L..............................................................................................4-41
TIMER/COUNTER1 IN PWM MODE ...................................................................................................................................................................4-42
THE WATCHDOG TIMER.......................................................................................................................................... 4-43
THE WATCHDOG TIMER CONTROL REGISTER - WDTCR...........................................................................................................................4-44
EEPROM READ/WRITE ACCESS............................................................................................................................. 4-44
THE EEPROM ADDRESS REGISTER - EEAR ....................................................................................................................................................4-45
THE EEPROM DATA REGISTER - EEDR ...........................................................................................................................................................4-45
THE EEPROM CONTROL REGISTER - EECR....................................................................................................................................................4-45
THE SERIAL PERIPHERAL INTERFACE - SPI..................................................................................................... 4-46
THE SPI CONTROL REGISTER - SPCR...............................................................................................................................................................4-48
THE SPI STATUS REGISTER - SPSR...................................................................................................................................................................4-49
THE SPI DATA REGISTER - SPDR ......................................................................................................................................................................4-50
THE UART...................................................................................................................................................................... 4-50
Data Transmission ........................................................................................................................................................ 4-50
Data Reception.............................................................................................................................................................. 4-52
UART Control.............................................................................................................................................................. 4-53
THE UART I/O DATA REGISTER - UDR ............................................................................................................................................................4-53
THE UART STATUS REGISTER - USR ...............................................................................................................................................................4-53
THE UART CONTROL REGISTER - UCR...........................................................................................................................................................4-54
THE BAUD RATE GENERATOR..........................................................................................................................................................................4-55
THE UART BAUD RATE REGISTER - UBRR.....................................................................................................................................................4-56
THE ANALOG COMPARATOR................................................................................................................................. 4-57
THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR............................................................................................4-57
I/O-PORTS...................................................................................................................................................................... 4-58
Port A............................................................................................................................................................................ 4-58
THE PORT A DATA REGISTER - PORTA...........................................................................................................................................................4-59
THE PORT A DATA DIRECTION REGISTER - DDRA......................................................................................................................................4-59
THE PORT A INPUT PINS ADDRESS - PINA.....................................................................................................................................................4-59
PORTA AS GENERAL DIGITAL I/O....................................................................................................................................................................4-59
PORT A SCHEMATICS..........................................................................................................................................................................................4-60
Port B............................................................................................................................................................................ 4-60
THE PORT B DATA REGISTER - PORTB ...........................................................................................................................................................4-61
THE PORT B DATA DIRECTION REGISTER - DDRB ......................................................................................................................................4-61
THE PORT B INPUT PINS ADDRESS - PINB......................................................................................................................................................4-61
PORTB AS GENERAL DIGITAL I/O....................................................................................................................................................................4-61
ALTERNATE FUNCTIONS FOR PORTB.............................................................................................................................................................4-62
PORT B SCHEMATICS ..........................................................................................................................................................................................4-63
Port C............................................................................................................................................................................ 4-66
THE PORT C DATA REGISTER - PORTC ...........................................................................................................................................................4-66
THE PORT C DATA DIRECTION REGISTER - DDRC ......................................................................................................................................4-67
THE PORT C INPUT PINS ADDRESS - PINC......................................................................................................................................................4-67
PORTC AS GENERAL DIGITAL I/O....................................................................................................................................................................4-67
PORT C SCHEMATICS ..........................................................................................................................................................................................4-67
Port D............................................................................................................................................................................ 4-69
THE PORT D DATA REGISTER - PORTD...........................................................................................................................................................4-69
THE PORT D DATA DIRECTION REGISTER - DDRD......................................................................................................................................4-69
THE PORT D INPUT PINS ADDRESS - PIND.....................................................................................................................................................4-69
PORTD AS GENERAL DIGITAL I/O....................................................................................................................................................................4-70
ALTERNATE FUNCTIONS FOR PORTD.............................................................................................................................................................4-70
PORTD SCHEMATICS...........................................................................................................................................................................................4-71
MEMORY PROGRAMMING...................................................................................................................................... 4-74

AT90S8414
Preliminary 4-3
Program Memory Lock Bits......................................................................................................................................... 4-74
Programming the Flash and EEPROM......................................................................................................................... 4-74
Parallel Programming................................................................................................................................................... 4-75
Serial Downloading...................................................................................................................................................... 4-75
SERIAL PROGRAMMING ALGORITHM............................................................................................................................................................4-75
Programming Characteristics........................................................................................................................................ 4-79
ABSOLUTE MAXIMUM RATINGS........................................................................................................................... 4-79
D.C. CHARACTERISTICS........................................................................................................................................... 4-80
A.C. CHARACTERISTICS........................................................................................................................................... 4-81
EXTERNAL DATA MEMORY READ CYCLE......................................................................................................... 4-81
EXTERNAL MEMORY WRITE CYCLE .................................................................................................................. 4-82
XTERNAL CLOCK DRIVE WAVEFORMS ............................................................................................................. 4-82
EXTERNAL CLOCK DRIVE....................................................................................................................................... 4-82
ORDERING INFORMATION...................................................................................................................................... 4-83
AT90S8414 REGISTER SUMMARY........................................................................................................................... 4-84
AT90S8414 INSTRUCTION SET SUMMARY........................................................................................................... 4-85

4-4 AT90S8414 Preliminary

AT90S8414
Preliminary 4-5
Features
·· Utilizes the AV R ää Enhanced RISC Architecture
·· AV
R ää - High Performance and Low Power RISC Architecture
·· 120 Powerful Instructions - Most Single Clock Cycle Execution
·· Efficient Context Switching Concept
·· 8 Kbytes of In-System Reprogrammable Downloadable Flash
SPI Serial Interface for Program Downloading
Endurance: 1,000 Write/Erase Cycles
·· 256 bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
·· 256 bytes Internal RAM
·· 32 x 8 General Purpose Working Registers
·· 32 Programmable I/O Lines
·· Programmable Serial UART
·· SPI Serial Interface
·· VCC Min.: 2.7 V
·· Fully Static Operation
·· One 8-Bit Timer/Counter with Separate Prescaler
·· One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
·· Dual 10 bit PWM
·· External and Internal Interrupt Sources
·· Programmable Watchdog Timer
·· On-Chip Analog Comparator
·· Low Power Idle and Power Down Modes
·· Programming Lock for Software Security
Pin Configurations
8-Bit
Microcontroller
with 8K bytes
Downloadable
Flash

4-6 AT90S8414 Preliminary
Block Diagram
Figure 1: The AT90S8414 Block Diagram

AT90S8414
Preliminary 4-7
Description
The AT90S8414 is a low-power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the AT90S8414 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
The
AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is
more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The
architecture supports high level languages efficiently while on-chip context switching hardware allows high performance,
low power real timer control system design.
The AT90S8414 provides the following features: 8K bytes of Downloadable Flash, 256-bytes EEPROM, 256-bytes
SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes,
internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator,
an SPI serial port and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the
SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register
contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip Downloadable
Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional
nonvolatile memory programmer. By combining an enhanced RISC 8 bit CPU with Downloadable Flash on a monolithic
chip, the Atmel AT90S8414 is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The AT90S8414
AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

4-8 AT90S8414 Preliminary
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pullups (selected for each bit). The Port A output
buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current (IIL) if the internal pullups are activated.
Port A serves as Multiplexed Address/Data input/output when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pullups. The Port B output buffers can sink 20 mA. As inputs, Port
B pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port B also serves the functions of various special features of the AT90S8414 as listed on Page 4-62.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pullups. The Port C output buffers can sink 20 mA. As inputs, Port
C pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port C also serves as Address output when using external SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pullups. The Port D output buffers can sink 20 mA. As inputs, Port
D pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port D also serves the functions of various special features of the AT90S8414 as listed on Page 4-70.
RESET
Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP / VPP
ICP is the input pin for the Timer/Counter1 Input Capture function.
When programming the AT90S8414 in parallel programming mode, the programming voltage, VPP is applied to this pin.
OC1B
OC1B is the output pin for the Timer/Counter1 Output CompareB function

AT90S8414
Preliminary 4-9
ALE / PROG
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-
order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the
second access cycle.
In parallel programming mode, this pin is pulsed to write data.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively , of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2: Oscillator Connections
Figure 3: External Clock Drive Configuration

4-10 AT90S8414 Preliminary
AT90S8414 AVR RISC Microcontroller CPU
The AT90S8414 AVR RISC microcontroller is upward compatible with the AVR Enhanced RISC Architecture. The
programs written for the AT90S8414 MCU are fully compatible with the range of
AVR 8-bit MCUs (AT90Sxxxx) with
respect to source code and clock cycles for execution.
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is executed, and the result is stored back in the register file - in
one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for SRAM addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4: The AT90S8414 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S8414
AVR Enhanced RISC microcontroller
architecture.

AT90S8414
Preliminary 4-11
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost SRAM addresses, allowing them to be
accessed as though they were ordinary memory locations.
The
AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-
fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly accessed. All
AVR instructions have a
single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts
are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through the four different addressing modes supported in the
AVR
architecture.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The memory spaces in the
AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the
status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of
the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower
the interrupt address vector the higher priority.

4-12 AT90S8414 Preliminary
The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
Figure 5: AVR CPU general purpose working registers
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and
a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the
registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user SRAM area. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X ,Y and Z registers can be set to index any
register in the file.
The 256 bytes of SRAM available for general data are implemented as addresses $0020 to $011F.

AT90S8414
Preliminary 4-13
THE X-REGISTER, Y-REGISTER AND Z-REGISTER
The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for
indirect addressing of the SRAM. The three indirect address registers X, Y and Z are defined as:
15 0
X - register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y - register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z - register 7 0 7 0
R31 ($1F) R30 ($1E)
Figure 6: The X, Y and Z Registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
The ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within
a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided
into three main categories - arithmetic, logic and bit-functions. Some microcontrollers in the
AVR product family feature
a hardware multiplier in the arithmetic part of the ALU.
The Downloadable Flash Program Memory
The AT90S8414 contains 8K bytes on-chip downloadable Flash memory for program storage. Since all instructions are
single 16-bit words, the Flash is organized as 4K x 16 words. The Flash memory has an endurance of at least 1000
write/erase cycles.
See Page 4-74 for a detailed description on Flash data downloading.
Constant tables must be allocated within the address 0-4K (see the LPM - Load Program Memory instruction
description).
See Page 4-15 for the different program memory addressing modes.

4-14 AT90S8414 Preliminary
The SRAM Data Memory - Internal and External
The following figure shows how the AT90S8414 SRAM Memory is organized:
Register File SRAM
R0 $0000
R1 $0001
R2 $0002
¼¼
R29 $001D
R30 $001E
R31 $001F
Internal SRAM start®$0020
$0021
¼
$011D
$011E
Internal SRAM end®$011F
External SRAM start®$0120
$0121
…
$FFFE
External SRAM end®$FFFF
Figure 7: SRAM Organization
The 288 top SRAM Memory locations address both the Register file and the internal data SRAM. The first 32 locations
address the register file, and the next 256 locations address the internal data SRAM. An optional external data SRAM can
be placed in the same SRAM memory space. Following the last address of the internal SRAM space and up to 64K - 1, is
the external data SRAM address area.
When the addresses accessing the SRAM memory space exceeds the internal data SRAM locations, the external data
SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data SRAM is
accessed, the read and write strobe pins ( RD and WR ) are inactive during the whole access cycle. The external data
SRAM physical address locations corresponding to the internal data SRAM addresses can not be reached by the CPU.
External SRAM operation is enabled by setting the SRE bit in the MCUCR register. See Page 4-32 for details.
The five different addressing modes for the SRAM data memory cover: Direct, Direct with Displacement, Indirect,
Indirect with Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the
indirect addressing pointer registers.
The Direct with Displacement mode features a 63 address locations reach from the base address given by the Y or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are decremented and incremented.

AT90S8414
Preliminary 4-15
The 32 general purpose working registers, the 256 bytes of internal data SRAM, and the 64K bytes of optional external
data SRAM in the AT90S8414 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
The Program and Data Addressing Modes
The AT90S8414 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to
the program memory (Flash) and data memory (SRAM). This section describes the different addressing modes supported
by the
AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all
figures show the exact location of the addressing bits.
REGISTER DIRECT, SINGLE REGISTER Rd
Figure 8: Direct Single Register Addressing
The operand is contained in register d (Rd).
REGISTER DIRECT, TWO REGISTERS Rd AND Rr
Figure 9: Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

4-16 AT90S8414 Preliminary
I/O DIRECT
Figure 10: I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
SRAM DIRECT
Figure 11: Direct SRAM Addressing
A 16-bit SRAM or Register Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination
or source register.
SRAM DIRECT WITH DISPLACEMENT
Figure 12: SRAM Direct with Displacement
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction
word.

AT90S8414
Preliminary 4-17
SRAM/REGISTER INDIRECT
Figure 13: SRAM Indirect Addressing
Operand address is the contents of the X, Y or the Z-register.
SRAM/REGISTER INDIRECT WITH PRE-DECREMENT
Figure 14: SRAM Indirect Addressing With Pre-Decrement
The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y
or the Z-register.
SRAM/REGISTER INDIRECT WITH POST-INCREMENT
Figure 15: SRAM Indirect Addressing With Post-Increment
The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register
prior to incrementing.

4-18 AT90S8414 Preliminary
CONSTANT ADDRESSING USING THE LPM INSTRUCTION
Figure 16: Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K) and LSB, select
low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
DIRECT PROGRAM ADDRESS, JMP AND CALL
Figure 17: Direct Program Memory Addressing
Program execution continues at the address immediate in the instruction words.
INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL
Figure 18: Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z-
register).

AT90S8414
Preliminary 4-19
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL
Figure 19: Relative Program Memory Addressing
Program execution continues at address PC + k. The relative address k is ±2K.
The EEPROM Data Memory
The AT90S8414 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between
the EEPROM and the CPU is described on Page 4-44 specifying the EEPROM address register, the EEPROM data
register, and the EEPROM control register.
For the SPI data downloading, see Page 4-75 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The
AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No
internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
System Clock Ø
T1 T2 T3 T4
1’st Instruction Fetch
1’st Instruction Execute
2’nd Instruction Fetch
2’nd Instruction Execute
3’rd Instruction Fetch
3’rd Instruction Execute
4’th Instruction Fetch
Figure 20: The Parallel Instruction Fetches and Instruction Executions

4-20 AT90S8414 Preliminary
Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
System Clock Ø
T1 T2 T3 T4
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Store Result in Register
Figure 21: Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
System Clock Ø
T1 T2 T3 T4
Internal Address Bus
Internal Data Bus (read)
Internal Write Signal
Internal Read Signal
Internal Data Bus (write)
Figure 22: On-Chip Data SRAM Access Cycles
The external data SRAM access is performed in two System Clock cycles as described in Figure 23.