Atmel AT91SAM7SE-EK User manual

AT91SAM7SE-EK Evaluation Board
..............................................................................................
User Guide

-2 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07

AT91SAM7SE-EK Evaluation Board User Guide -i
6241B–ATARM–22-Mar-07
Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1 Scope........................................................................................................1-1
1.2 Deliverables ..............................................................................................1-1
1.3 AT91SAM7SE-EK Evaluation Board ........................................................1-1
Section 2
Setting Up the AT91SAM7SE-EK Board .............................................. 2-1
2.1 Electrostatic Warning ................................................................................2-1
2.2 Requirements............................................................................................2-1
2.3 Layout .......................................................................................................2-2
2.4 Powering Up the Board.............................................................................2-3
2.5 Getting Started..........................................................................................2-3
2.6 AT91SAM7SE-EK Block Diagram ............................................................2-4
Section 3
Board Description ................................................................................. 3-1
3.1 AT91SAM7SE Microcontroller ..................................................................3-1
3.2 AT91SAM7SE Block Diagram ..................................................................3-4
3.3 Memory .....................................................................................................3-5
3.4 Clock Circuitry...........................................................................................3-5
3.5 Reset Circuitry ..........................................................................................3-5
3.6 Power Supply Circuitry..............................................................................3-5
3.7 Remote Communication ...........................................................................3-5
3.8 Audio Stereo Interface ..............................................................................3-5
3.9 User Interface ...........................................................................................3-5
3.10 Debug Interface ........................................................................................3-5
3.11 Expansion Slot ..........................................................................................3-5
3.12 PIO Usage ................................................................................................3-6
Section 4
Configuration ........................................................................................ 4-1
4.1 Jumpers ....................................................................................................4-1
4.2 Audio Configuration ..................................................................................4-1
4.3 JTAG/ICE..................................................................................................4-2
4.4 Microcontroller Clock ................................................................................4-2
4.5 Memory .....................................................................................................4-2
4.6 Ethernet ....................................................................................................4-2
4.7 Miscellaneous ...........................................................................................4-3

-ii AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
Section 5
Schematics ........................................................................................... 5-1
5.1 Schematics ...............................................................................................5-1
Section 6
Errata.................................................................................................... 6-1
6.1 PIO Usage ................................................................................................6-1
6.2 TWI line pullups are too weak for Fast Mode operation............................6-1
Section 7
Revision History.................................................................................... 7-1
7.1 Revision History ........................................................................................7-1

AT91SAM7SE-EK Evaluation Board User Guide 1-1
6241B–ATARM–22-Mar-07
Section 1
Overview
1.1 Scope The AT91SAM7SE-EK evaluation board enables the evaluation of and code develop-
ment for applications running on an AT91SAM7SE device.
This guide focuses on the AT91SAM7SE-EK board as an evaluation platform.
1.2 Deliverables
1.2.1 Standard Version
AT91SAM7S-EK
VAR
The AT91SAM7SE-EK package contains the following items:
!An AT91SAM7SE-EK board
!One Universal input AC/DC power supply with US and Europe plug adapter
!One A/B-type USB cable
!One serial RS232 cable
!One CD-ROM containing summary and full datasheets, datasheets with electrical and
mechanical characteristics, application notes and getting started documents for all
development boards and AT91 microcontrollers. An AT91 software package with C
and assembly listings is also provided. This allows the user to begin evaluating the
AT91 ARM®Thumb®32-bit microcontroller quickly.
1.3 AT91SAM7SE-
EK Evaluation
Board
The board is equipped with an AT91SAM7SE512 (128-pin LQFP package) together with
the following:
!32 Mbytes of SDRAM memory
!256 Mbytes of NAND Flash memory
!One USB device port interface
!One DBGU serial communication port
!One additional serial communication port with RTS/CTS handshake control
!One JTAG/ICE debug interface
!One Atmel AT73C213 Stereo Audio DAC

Overview
1-2 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
!One power LED and two general-purpose LEDs
!One joystick and two user input pushbuttons
!One Reset pushbutton
!Three expansion connectors (PIO A, PIO B, PIO C)
!One EBI expansion BGA-like footprint connector

AT91SAM7SE-EK Evaluation Board User Guide 2-1
6241B–ATARM–22-Mar-07
Section 2
Setting Up the AT91SAM7SE-EK
Board
2.1 Electrostatic
Warning
The AT91SAM7SE-EK evaluation board is shipped in protective anti-static packaging.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic element.
2.2 Requirements In order to set up the AT91SAM7SE-EK evaluation board, the following items are
needed:
!The AT91SAM7SE-EK evaluation board itself.
!AC/DC power adapter (5V at 2A), 2.1 mm x 5.5 mm

Setting Up the AT91SAM7SE-EK Board
2-2 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
2.3 Layout Figure 2-1. AT91SAM7SE-EK Layout - Top View

Setting Up the AT91SAM7SE-EK Board
AT91SAM7SE-EK Evaluation Board User Guide 2-3
6241B–ATARM–22-Mar-07
Figure 2-2. AT91SAM7SE-EK Layout - Bottom View
2.4 Powering Up the
Board
The AT91SAM7SE-EK requires 5V DC (±5%). DC power is supplied to the board via the
2.1 mm x 5.5 mm socket J1. Coaxial plug center positive standard.
2.5 Getting Started The AT91SAM7SE-EK evaluation board is delivered with a CD-ROM containing all nec-
essary information and step-by-step procedures for working with the most common
development toolchains. Please refer to this CD-ROM, or to the AT91 web site,
http://www.atmel.com/products/AT91/, for the most up-to-date information on getting
started with the AT91SAM7SE-EK.

Setting Up the AT91SAM7SE-EK Board
2-4 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
2.6 AT91SAM7SE-EK Block Diagram
RAS
CAS
SDA10
SDWE
SDCS
SDCK
SDCKE
NBS1
PWM0
NANDOE
NANDWE
A22
A21
D[0..31]
A16
A17
A[2..14]
NRST
SDCK
PB[0..31]
DTXD
DRXD NRST
NANDCS
RDYBSY
D[0..15]
TWCK
TWD
D[0..15]
TXD0
RTS0
RXD0
CTS0
D13PC13
D6PC6
D11PC11 D10PC10
D0PC0
D5PC5
D15PC15
D7PC7
D4PC4 D3PC3
D1PC1
D9PC9
D14PC14
D2PC2
D12PC12
D8PC8
A[0..22]
A21PC19
A15PB15
A10PB10
D29PB31
A1PB1
D22PB24
A12PB12
A9PB9
D27PB29 D26PB28
A14PB14
D16PB18
A17PB17
A20PC18
A7PB7
D21PB23
D31PA31
A11PB11
A0PB0
D23PB25
A5PB5
D20PB22
A13PB13
D19PB21
D17PB19
D25PB27
A22PC20
A4PB4
D30PA30
A19PC17 D18PB20
A3PB3
A16PB16
A2PB2
D28PB30
A6PB6
A8PB8
A18PC16
D24PB26
D[0..31]PA[0..31]
PA0 PWM0
PA1 PWM1
PA2 PWM2
PA3 TWD
PA5 RXD0
PA6 TXD0
PA7 RTS0
PA4 TWCK
PA9 DRXD
PA10 DTXD
PA11 NPCS0
PA8 CTS0
PA13 MOSI
PA14 SPCK
PA15 TF
PA12 MISO
PA17 TD
PA18
PA19
PA16 TK
PA21
PA22
PA23 NBS1
PA20 NCS2
PA25 SDCKE
PA26 SDCS
PA27 SDWE
PA24 SDA10
PA29 RAS
PA30 IRQ1
PA31 NPCS1
PA28 CAS
PB1
PB2
PB3
PB5
PB6
PB7
PB4
PB9
PB10
PB11
PB8
PB13
PB14
PB15
PB12
PB17
PB18 NANDCS
PB19 RDYBSY
PB16
PB21
PB22
PB23
PB20
PB25
PB26
PB27
PB24
PB29
PB30
PB31 PCK2
PB28
PB[0..31]
PB0 PC1
PC2
PC3
PC5
PC6
PC7
PC4
PC9
PC10
PC11
PC8
PC13
PC14
PC15
PC12
PC17 NANDOE
PC18 NANDWE
PC19
PC16
PC21 NWE
PC22 NRD
PC23
PC20
PC[0..23]
PC0
A[0..22]
PA[0..31]
PC[0..23]
PC19
MOSI
MISO
SPCK
NPCS0
NCS2
IRQ1
NRST
D[0..15]
A12
NWE
NRD
TF
TD
TK
PCK2
MISO
MOSI
SPCK
NPCS1
NRST
PWM1
PWM2
A0
PB22
PB23
PB24
PB26
AD[4..7]
PB27
PB25
SDRAMNANFLASH
DAC
AT73C213
5VDC
DBGU
USB
DEVICE
COM0
RS232FAST ETHERNET
EEPROM
SERIAL SERIAL
DATAFLASH
PIO USAGE
USER'S INTERFACE
POPULATED
NOT
POPULATED
NOT
POPULATED
NOT
AT91SAM7SE
02 - AT91SAM7SE
PA[0..31]
PB[0..31]
NRST
DDM
DDP
PC[0..23]
SDCK
AD[4..7]
MEMORY
03 - MEMORY
CAS
SDWE
SDCKE
SDCK
SDA10
RAS
NRST
NANDOE
NANDWE
RDYBSY
NANDCS
ALE
CLE
SCK
CS
BA0
BA1
SCL
SDA
SI
SO
D[0..15]
D[0..15]
SDCS
NBS1
NBS0
A[2..14]
EXPANSION CONNECTORS
06 - EXPANSION CONNECTORS
PA[0..31]
A[0..22]
D[0..31]
PB[0..31]
NRST
SDCK
PC[0..23]
AD[4..7]
SERIAL INTERFACES
05 - COMMUNICATION
DDM
DDP
USBCNX
DRXD
DTXD
RXD
CTS
RTS
TXD
RMII_MII ETHERNET
03 - RMII_MII ETHERNET
INT
CMD
D[0..15]
IOR
PWRST
IOW
CS
POWER SUPPLY
01 - POWER SUPPLY
NRST
POWERLED
BCLK
LRFS
DIN
MCLK
SDIN
DOUT
CLK
CS
DOWN
RIGHTCLIC
LEFT
RIGHT
UP
USERLED1
USERLED2
PUSHLEFTCLIC

AT91SAM7SE-EK Evaluation Board User Guide 3-1
6241B–ATARM–22-Mar-07
Section 3
Board Description
3.1 AT91SAM7SE
Microcontroller
•Incorporates the ARM7TDMI®ARM®Thumb®Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™In-circuit Emulation, Debug Communication Channel Support
•Internal High-speed Flash
– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes
Dual Plane (AT91SAM7SE512)
– 256 Kbytes (AT91SAM7SE256) Organized in One Bank of 1024 Pages of 256
Bytes Single Plane (AT91SAM7SE256)
– 32 Kbytes (AT91SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes
Single Plane (AT91SAM7SE32)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15
ms
– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
•32 Kbytes (AT91SAM7SE512/256) or 8 Kbytes (AT91SAM7SE32) of Internal
High-speed SRAM, Single-cycle Access at Maximum Speed
•One External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash®and
ECC-enabled NANDFlash
•Memory Controller (MC)
– Embedded Flash Controller
– Memory Protection Unit
– Abort Status and Misalignment Detection
•Reset Controller (RSTC)
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
– Provides External Reset Signal Shaping and Reset Source Status
•Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
•Power Management Controller (PMC)

Board Description
3-2 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz)
and Idle Mode
– Three Programmable External Clock Signals
•Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
•Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
•Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
•Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
•Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
•Three Parallel Input/Output Controllers (PIO)
– Eighty-eight Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– Schmitt Trigger on All inputs
•Eleven Peripheral DMA Controller (PDC) Channels
•One USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs
•One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
•Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA®Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1
•One Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
•One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
•One Four-channel 16-bit PWM Controller (PWMC)
•One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs
Supported
– General Call Supported in Slave Mode
•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with
Digital I/Os
•SAM-BA™
– Default Boot program
– Interface with SAM-BA Graphic User Interface

Board Description
AT91SAM7SE-EK Evaluation Board User Guide 3-3
6241B–ATARM–22-Mar-07
•IEEE®1149.1 JTAG Boundary Scan on All Digital Pins
•Four High-current Drive I/O lines, Up to 16 mA Each
•Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External
Components
– 1.8V or 3,3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH
Flash Power Supply
– 1.8V VDDCORE Core Power Supply with Brownout Detector
•Fully Static Operation: Up to 48 MHz at 1.65V and 85°C Worst Case Conditions
•Available in a 128-lead LQFP Green Package, or a 144-ball LFBGA RoHS-compliant
Package

Board Description
3-4 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
3.2 AT91SAM7SE
Block Diagram
Figure 3-1. AT91SAM7SE Block Diagram
Reset
Controller
PMC
APB
ICE
JTAG
SCAN
ARM7TDMI
Processor
System Controller
AIC
DBGU PDC
PDC
PLL
OSC
RCOSC
BOD
POR
PIO
PIT
WDT
RTT
PIOA
PIOB
PIOC
PIO
PIO PIO
USART0
USART1
SPI
Timer Counter
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
TC0
TC1
TC2
ADC
ADVREF
TWI
SSC
PWMC
USB Device
FIFO
Static Memory
Controller
ECC
Controller
SDRAM
Controller
EBI
CompactFlash
NAND Flash
SRAM
32 Kbytes (SE512/256)
or
8 Kbytes (SE32)
Flash
512 Kbytes (SE512)
256 Kbytes (SE256)
32 Kbytes (SE32)
1.8V
Voltage
Regulator
Memory Controller
Embedded
Flash
Controller
Address
Decoder
Abort
Status
Misalignment
Detection
Memory Protection
Unit
Peripheral DMA
Controller
11 Channels
Peripheral Bridge
Fast Flash
Programming
Interface
SAM-BA
Transciever
PDC
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
ADTRG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
TCLK0
TCLK1
TCLK2
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
NRST
VDDCORE
VDDCORE
VDDFLASH
XIN
XOUT
PLLRC
PCK0-PCK2
DRXD
DTXD
IRQ0-IRQ1
FIQ
TST
TDI
TDO
TMS
TCK
JTAGSEL
VDDIN
GND
VDDOUT
VDDCORE
VDDIO
VDDFLASH
ERASE
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN1
D[31:0]
A0/NBS0
A1/NBS2
A[15:2], A[20:18]
A21/NANDALE
A22/REG/NANDCLE
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2/CFCS1
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NBS3/CFIOW
SDCKE
RAS
CAS
SDWE
SDA10
CFRNW
NCS4/CFCS0
NCS5/CFCE1
NCS6/CFCE2
NCS7
NANDOE
NANDWE
NWAIT
SDCK
DDM
DDP
PWM0
PWM1
PWM2
PWM3
TF
TK
TD
RD
RK
RF
TWD
TWCK

Board Description
AT91SAM7SE-EK Evaluation Board User Guide 3-5
6241B–ATARM–22-Mar-07
3.3 Memory !512 Kbytes of Internal Flash
!32 KBytes of Internal High Speed SRAM
!32 Mbytes of SDRAM memory (16-bit bus width)
!256 Mbytes of NANDFlash memory (8-bit bus width)
3.4 Clock Circuitry !18.432 MHz 20 pF miniature AT cut strip crystal
!Internal RC Oscillator
3.5 Reset Circuitry !Internal reset controller with a bi-directional reset pin
!External reset push button
3.6 Power Supply
Circuitry
!Embedded 1.8V regulator (drawing up to 100 mA for the core and external
components)
!On board 3.3V linear regulator
3.7 Remote
Communication
!One Serial interface (DBGU COM Port) via RS-232 DB9 male connectors
!One additional serial interface (COM Port 0) with RTS/CTS handshake control via
RS-232 DB9 male connectors
!USB V2.0 Full-speed compliant, 12 Mbits per Second (UDP)
3.8 Audio Stereo
Interface
!One Atmel stereo audio DAC (AT73C213)
!One 32 Ohm/20 mW Stereo Headset output (J3) with master volume and mute
controls
3.9 User Interface !One 5-way joystick (4 directions and push for confirmation)
!Two user input pushbuttons
!Two user green LEDs
!One yellow power LED (can be also software controlled)
3.10 Debug Interface !20-pin JTAG/ICE interface connector
!DBGU COM Port
3.11 Expansion Slot !All I/Os of the AT91SAM7SE are routed to peripheral extension connectors

Board Description
3-6 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
!All EBI Signals of the AT91SAM7SE are routed to extension footprint connectors
(J14)
This allows the developer to check the integrity of the components and to extend the
features of the board by adding external hardware components or boards.
3.12 PIO Usage
Table 3-1. PIO Controller A
I/O Line Peripheral A Peripheral B Comments Function
PA0 PWM0 A0_NBS0 High-Drive Power LED
PA1 PWM1 A1_NBS2 High-Drive User LED 1
PA2 PWM2 A2 High-Drive User LED 2
PA3 TWD A3 High-Drive EEPROM AT24C256 (SDA)
PA4 TWCK A4 EEPROM AT24C256 (SCL)
PA5 RXD0 A5 RS232 COM PORT (RXD)
PA6 TXD0 A6 RS232 COM PORT (TXD)
PA7 RTS0 A7 RS232 COM PORT (RTS)
PA8 CTS0 A8 RS232 COM PORT (CTS)
PA9 DRXD A9 SERIAL DEBUG PORT(RXD)
PA10 DTXD A10 SERIAL DEBUG PORT(TXD)
PA11 NPCS0 A11 SPI DATAFLASH memory (Chip Select)
PA12 MISO A12 SPI DATAFLASH & Audio DAC (MISO)
PA13 MOSI A13 SPI DATAFLASH & Audio DAC (MOSI)
PA14 SPCK A14 SPI DATAFLASH & Audio DAC (SPCK)
PA15 TF A15 Audio DAC AT73C213 (LRFS)
PA16 TK A16_BA0 Audio DAC AT73C213 (BCLK)
PA17 TD A17_BA1 AD0 Audio DAC AT73C213 (SDIN)
PA18 RD NBS3_CFIOW AD1
PA19 RK NCS4_CFCS0 AD2
PA20 RF NCS2_CFCS2 AD3 ETHERNET DM9000A (Chip Select)
PA21 RXD1 NCS6_CFCE2
PA22 TXD1 NCS5_CFCE1
PA23 SCK1 NWR1_NBS1_CFIOR SDRAM DEVICE (NBS1)
PA24 RTS1 SDA10 SDRAM DEVICE (SDA10)
PA25 CTS1 SDCKE SDRAM DEVICE (SDCKE)
PA26 DCD1 NCS1_SDCS SDRAM DEVICE (Chip Select)
PA27 DTR1 SDWE SDRAM DEVICE (SDWE)
PA28 DSR1 CAS SDRAM DEVICE (CAS)

Board Description
AT91SAM7SE-EK Evaluation Board User Guide 3-7
6241B–ATARM–22-Mar-07
PA29 RI1 RAS SDRAM DEVICE (RAS)
PA30 IRQ1 D30 ETHERNET DM9000A (IRQ)
PA31 NPCS1 D31 SPI Audio DAC AT73C213 (Chip Select)
Table 3-2. PIO Controller B
I/O Line Peripheral A Peripheral B Comments Function
PB0 TIOA0 A0_NBS0 ADDRES BUS (PB0..PB17)
PB1 TIOB0 A1_NBS2
PB2 SCK0 A2
PB3 NPCS3 A3
PB4 TCLK0 A4
PB5 NPCS3 A5
PB6 PCK0 A6
PB7 PWM3 A7
PB8 ADTRG A8
PB9 NPCS1 A9
PB10 NPCS2 A10
PB11 PWM0 A11
PB12 PWM1 A12
PB13 PWM2 A13
PB14 PWM3 A14
PB15 TIOA1 A15
PB16 TIOB1 A16_BA0
PB17 PCK1 A17_BA1
PB18 PCK2 D16 NandFlash (NANDCS)
PB19 FIQ D17 NandFlash (RDYBSY)
PB20 IRQ0 D18
PB21 PCK1 D19
PB22 NPCS3 D20 RIGHT clic push button
PB23 PWM0 D21 Joystick UP
PB24 PWM1 D22 Joystick DOWN
PB25 PWM2 D23 Joystick LEFT
PB26 TIOA2 D24 Joystick RIGHT
PB27 TIOB2 D25 Joystick PUSH and LEFT clic push button
PB28 TCLK1 D26
Table 3-1. PIO Controller A (Continued)
I/O Line Peripheral A Peripheral B Comments Function

Board Description
3-8 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
PB29 TCLK2 D27
PB30 NPCS2 D28
PB31 PCK2 D29 Audio DAC AT73C213 (MCLK)
Table 3-3. PIO Controller C
I/O Line Peripheral A Peripheral B Comments Function
PC0 D0 DATA BUS (PC0..PC15)
PC1 D1
PC2 D2
PC3 D3
PC4 D4
PC5 D5
PC6 D6
PC7 D7
PC8 D8 RTS1
PC9 D9 DTR1
PC10 D10 PCK0
PC11 D11 PCK1
PC12 D12 PCK2
PC13 D13
PC14 D14 NPCS1
PC15 D15 NCS3_NANDCS
PC16 A18 NWAIT
PC17 A19 NANDOE NandFlash (NANDOE)
PC18 A20 NANDWE NandFlash (NANDWE)
PC19 A21 USB_CNX (VBUS DETECT) and NandFlash
(ALE). See errata section
PC20 A22 NCS7 NandFlash (CLE)
PC21 NWR0_NWE_CFWE
PC22 NRD_CFOE
PC23 CFRNW NCS0
Table 3-2. PIO Controller B (Continued)
I/O Line Peripheral A Peripheral B Comments Function

AT91SAM7SE-EK Evaluation Board User Guide 4-1
6241B–ATARM–22-Mar-07
Section 4
Configuration
4.1 Jumpers
Note: 1. These jumpers are provided for power consumption measurement use. By default,
they are closed. To use this feature, the user has to open the strap and insert an
anmeter.
4.2 Audio
Configuration
Table 4-1. Jumpers
Designation
Default
Setting Feature
J2 Closed 3.3V Jumper (1)
J5-1 Opened Erases all internal Flash memory when the board is
powered. To do so, the user will have to close this
jumper for at least 10 ms.
J5-2 Closed VDDIO Jumper(1)
J5-3 Closed VDDCORE Jumper (1)
J5-4 Closed VDDIN Jumper (1)
J5-5 Closed VDDPLL Jumper (1)
J5-6 Closed VDDFLASH Jumper (1)
Table 4-2. Audio Configuration
Designation
Default
Setting Feature
R5 Soldered Enables the use of the audio stereo DAC AT73C213

Configuration
4-2 AT91SAM7SE-EK Evaluation Board User Guide
6241B–ATARM–22-Mar-07
4.3 JTAG/ICE
4.4 Microcontroller
Clock
4.5 Memory
4.6 Ethernet NOT POPULATED
Table 4-3. JTAG/ICE Configuration
Designation
Default
Setting Feature
S1 Opened Selects ICE mode or JTAG mode (Closed)
R11 Soldered Enables the ICE NRST input
Table 4-4. Microcontroller Clock Configuration
Designation
Default
Setting Feature
R13/R15 Soldered Enables the use of 18.432MHz crystal. If external clock
used, R13/R15 must be unsoldered and S3 closed.
S3 Opened
Table 4-5. Memory Configuration
Designation
Default
Setting Feature
SDRAM
R18 Soldered Enables MN4 Chip select access
NAND FLASH (MN6x)
R22
R20
S5
Soldered
Soldered
Opened
Enables the use of NANDFlash (MN6x)
Enables the use of Ready Busy signal
Disables write protect
SERIAL DATAFLASH (MN5) (NOT POPULATED)
R26
S4
Soldered
Opened
Enables the use of the Serial DataFlash
Disables the write protect.
TWI SERIAL EEPROM (MN10) (NOT POPULATED)
R30
R31
Soldered
Soldered
Enables SCL access
Enables SDA access
Table 4-6. Ethernet Configuration
Designation
Default
Setting Feature
R37 Soldered Enables the use of the Ethernet controller DM9000A
R11 Soldered Enables the use of the IRQ Ethernet controller