Atmel TSEV83102G0B User manual

ADC 10-bit 2 Gsps Evaluation
Board - TSEV83102G0B
..............................................................................................
User Guide

TSEV83102G0B - Evaluation Board User Guide i
2166B–BDC–04/03
Table of Contents
Section 1
Overview...............................................................................................1-1
1.1 Description................................................................................................1-1
1.2 TSEV83102G0B Evaluation Board...........................................................1-2
1.3 Board Mechanical Characteristics.............................................................1-3
1.4 Analog Input, Clock Input and De-embedding Fixture Accesses..............1-4
1.5 Digital Outputs Accesses..........................................................................1-4
1.6 Power Supplies and Ground Accesses.....................................................1-4
1.7 ADC Function Setting Accesses...............................................................1-4
Section 2
Layout Information................................................................................2-1
2.1 Board ........................................................................................................2-1
2.2 AC Inputs/Digital Outputs..........................................................................2-1
2.3 DC Function Settings................................................................................2-1
2.4 Power Supplies.........................................................................................2-2
Section 3
Operating Procedures and
Characteristics......................................................................................3-1
3.1 Introduction ...............................................................................................3-1
3.2 Operating Procedure (ECL Mode) ............................................................3-1
3.3 Use with DMUX Evaluation Board ............................................................3-2
3.4 Electrical Characteristics...........................................................................3-3
3.5 Operating Charcteristics............................................................................3-4
Section 4
Application Information.........................................................................4-1
4.1 Introduction ...............................................................................................4-1
4.2 Analog Inputs............................................................................................4-1
4.3 Clock Inputs ..............................................................................................4-1
4.4 Setting the Digital Output Data Format.....................................................4-1
4.5 ADC Gain Adjust.......................................................................................4-2
4.6 SMA Connectors and Microstrip Lines De-embedding Fixture.................4-2
4.7 Die Junction Temperature Monitoring.......................................................4-3
4.8 Decimation Function .................................................................................4-5
4.9 Pattern Generator Enable.........................................................................4-5
4.10 Data Ready Output Signal Reset..............................................................4-6
4.11 Sampling Delay Adjusting.........................................................................4-6
4.12 Test Bench Description.............................................................................4-7

Table of Contents
ii TSEV83102G0B - Evaluation Board User Guide
2166B–BDC–04/03
Section 5
Package Description.............................................................................5-1
5.1 TS83102G0B Pinout.................................................................................5-1
5.2 Thermal Characteristics............................................................................5-3
5.2.1 Thermal Resistance from Junction to Ambient: Rthja ........................5-3
5.2.2 Thermal Resistance from Junction to Case: Rthjc .............................5-4
5.2.3 Heatsink..............................................................................................5-4
5.3 Ordering Information.................................................................................5-5
Section 6
Schematics ...........................................................................................6-1
6.1 TSEV83102G0B Electrical Schematic......................................................6-1

TSEV83102G0B - Evaluation Board User Guide 1-1
Rev. 2166B–BDC–04/03
Section 1
Overview
1.1 Description The TSEV83102G0B Evaluation Board (EB) is a prototype board which has been
designed in order to facilitate the evaluation and the characterization of the
TS83102G0B device (in CBGA152) up to its 3 GHz full power bandwidth at up to 2 Gsps
in the extended temperature range.
The high speed of the TS83102G0B requires careful attention to circuit design and lay-
out to achieve optimal performance. This four metal layer board with an internal ground
plane has the functions that allow a quick and simple evaluation of the TS83102G0B
ADC performances over the temperature range.
The TS83102G0B Evaluation Board (EB) is very straightforward as it only implements
the TS83102G0B ADC device, SMA connectors for input/output accesses and a
2.54 mm pitch connector compatible with high speed acquisition system high frequency
probes.
The board has been designed to be fully compatible with Atmel’s DMUX evaluation
board (TSEV81102G0).
The board also implements a de-embedding fixture in order to facilitate the evaluation of
the high frequency insertion loss of the input microstrip lines.
The board is constructed like a sandwich of two dielectric layers, featuring low insertion
loss and enhanced thermal characteristics for operation in the high frequency domain
and extended temperature range.
The board dimensions are 120 mm x 150 mm.
The board set comes fully assembled and tested, with the TS83102G0B installed and
with a heatsink.

Overview
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1.2 TSEV83102G0B
Evaluation Board
Figure 1-1. TSEV83102G0B Block Diagram
CLK
CLKB
Differential
Clock inputs
Z0 = 50Ω
Z0 = 50Ω
CLK
CLKB
TS83102G0B
VIN
VINB
Differential
analog inputs
Z0 = 50Ω
Z0 = 50Ω
VIN
VINB
GAIN
GA
SDA
SDA
OA
SDAEN
VEE
TEST
VEE
B/BG
PGEB
DR/DRB
D0/D0B Z0 = 50Ω Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
D7/D7B
PC/PCB
VCC
DRRB
VCC = +5V
GND
VPLUSD
GND = 0V
VPLUSD = -0.8V (ECL)
VPLUSD = 1.6V (LVDS)
VEE
DVEE
DIODE
VEE = -5V
DVEE = -5V
J - diode
V - diode
DRRB
V-GND
I-GND
CAL1
CAL2
L = 50 mm typ
LVIN/VINb = LCLK/CLKb = 43 mm typ
Loutputs = 58 mm typ
+5V
VCC +5V
VEE
GND +5V
DVEE
Short-circuit
possibility
here

Overview
TSEV83102G0B - Evaluation Board User Guide 1-3
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1.3 Board
Mechanical
Characteristics
The board’s layer number, thickness, and functions are given below, from top to bottom.
The TSEV83102G0B is an eleven layer PCB made of six copper layers and five dielec-
tric layers. The six metal layers correspond respectively from top to bottom to the AC
and DC signals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer
(layer 7).
Considering the severe mechanical constraints due to the wide temperature range and
the high frequency domain in which the board is to operate, it is necessary to use a
sandwich of two different dielectric materials, with specific characteristics:
A low insertion loss RO4003 Hydrocarbon/Wovenglass dielectric layer of 200 µm
thickness, chosen for its low loss (-0.318 dB/inch) and enhanced dielectric
consistency in the high frequency domain. The RO4003 dielectric layer is dedicated
to the routing of the 50Ωimpedance signal traces (the RO4003 typical dielectric
constant is 3.4 at 10 GHz). The RO4003 dielectric layer characteristics are very close
to PTFE in terms of insertion loss characteristics.
A BT/Epoxy dielectric layer of 0.9 mm total thickness which is sandwiched between
the upper ground plane and the back-side supply layer.
Table 1-1. Board’s Layer Thickness Profile
Layer Characteristics
Layer 1
Copper layer
Copper thickness = 40 µm
AC signal traces = 50Ωmicrostrip lines
DC signal traces (B/GB, GAIN, DIODE, OA, TEST, SDA)
Layer 2
RO4003 dielectric layer
(Hydrocarbon/Wovenglass)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
-0.044 dB/inch insertion loss at 2.5 GHz
-0.318 dB/inch insertion loss at 18 GHz
Layer 3
Copper layer Copper thickness = 39 µm Ground plane = reference plane 50Ωmicrostrip return
Layer 4
BT/Epoxy dielectric layer Layer thickness = 330 µm
Layer 5
Copper layer Copper thickness = 35 µm Power and ground planes
Layer 6
BT/Epoxy dielectric layer Layer thickness = 330 µm
Layer 7
Copper layer Copper thickness = 35 µm Power and ground planes (identical to layer 5)
Layer 8
BT/Epoxy dielectric layer Layer thickness = 330 µm
Layer 9
Copper layer Copper thickness = 35 µm Ground planes (identical to layer 3)
Layer 10
BT/Epoxy dielectric layer Layer thickness = 200 µm
Layer 11
Copper layer Copper thickness = 35 µm Power and ground planes

Overview
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The BT/Epoxy layer has been chosen because of its enhanced mechanical characteris-
tics for elevated temperature operation. The typical dielectric constant is 4.5 at 1 MHz.
More precisely, the BT/Epoxy dielectric layer offers enhanced characteristics compared
to FR4 Epoxy, namely:
Higher operating temperature values: 170°C (125°C for FR4).
Better withstanding of thermal shocks (-65°C up to 170°C).
The total board thickness is 1.6 mm. The previously described mechanical and fre-
quency characteristics makes the board particularly suitable for device evaluation and
characterization in the high frequency domain and in military temperature ranges.
1.4 Analog Input,
Clock Input and
De-embedding
Fixture Accesses
The differential active inputs (Analog, Clock, De-embedding fixture) are provided by
SMA connectors.
Reference: VITELEC 142-0701-851.
Connector mounting plates have been used for fastening the SMA connectors.
1.5 Digital Outputs
Accesses Access to the differential output data port is provided by a 2.54 mm pitch connector,
compatible with the high speed digital acquisition system. It enables access to the con-
verter output data, as well as proper 50Ωdifferential termination.
1.6 Power Supplies
and Ground
Accesses
The power supply accesses are provided by five 2 mm section banana jacks respec-
tively for DVEE, VEET, VDD, VPLUSD and VCC.
The power supply access is provided by one 4 mm section banana jack for VEE.
The Ground accesses are provided by four 2 mm and one 4 mm banana jacks.
1.7 ADC Function
Setting Accesses For ADC function setting accesses (B/GB, Die junction temp., Test), 2 mm section
banana jacks are provided.
Three potentiometers are provided for ADC gain adjust, Sampling delay adjust and Off-
set adjust.
One sub-screw is provided for Asynchronous data ready reset.

TSEV83102G0B - Evaluation Board User Guide 2-1
Rev. 2166B–BDC–04/03
Section 2
Layout Information
2.1 Board The TS83102G0B requires proper board layout for optimum full speed operation.
The following explains the board layout recommendations and demonstrates how the
Evaluation Board fulfills these implementation constraints.
A single low impedance ground plane is recommended, since it allows the user to lay
out signal traces and power planes without interrupting the ground plane.
Therefore a multi-layer board structure has been retained for the TSEV83102G0B.
Six copper metal layers are used, dedicated respectively (from top to bottom) to the sig-
nal traces, ground planes and power supplies.
2.2 AC Inputs/Digital
Outputs The board uses 50Ωimpedance microstrip lines for the differential analog inputs, clock
inputs, and differential digital outputs.
The input signals and clock signals must be routed on one layer only, without using any
through-hole vias. The line lengths are matched to within 2 mm.
The digital output lines are 50Ωdifferentially terminated.
The output data trace lengths are matched to within 0.25 inch (6 mm) to minimize the
data output delay skew.
For the TSEV83102G0B the propagation delay is approximately 6.1 ps/mm
(155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.
For more informations about different output termination options refer to the specifica-
tion application notes.
2.3 DC Function
Settings The DC signal traces are low impedance.
They have been routed with a 50Ωimpedance near the device because of space
restriction.

Layout Information
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2.4 Power Supplies The bottom metal layers 5 and 7 and 11 are dedicated to power supply traces (VEE,
DVEE, VEET, VDD, VPLUSD and VCC).
The supply traces are approximately 6 mm wide in order to present low impedance, and
are surrounded by a ground plane connected to the two inner ground planes.
The analog and digital negative power supply traces are independent, but the possibility
exists to short-circuit both supplies on the top metal layer).
No difference in ADC high speed performance is observed when connecting both nega-
tive supply planes together. Obviously one single negative supply plane could be used
for the circuit.
Each power supply incoming is bypassed by a 1 µF Tantalum capacitor in parallel with
1 nF chip capacitor.
Each power supply access is decoupled very close to the device by 10 nF and 100 pF
surface mount chip capacitors in parallel.
Note: The decoupling capacitors are superposed. In this configuration, the 100 pF capacitors
must be mounted first.

TSEV83102G0B - Evaluation Board User Guide 3-1
Rev. 2166B–BDC–04/03
Section 3
Operating Procedures and
Characteristics
3.1 Introduction This section describes a typical single-ended configuration for analog inputs and clock
inputs.
The single-ended configuration is preferable, as it corresponds to the most straightfor-
ward and quickest TSEV83102G0B board setting for evaluating the TS83102G0B at full
speed in its temperature range.
The inverted analog input VINB and clock input CLKB common mode level is Ground
(on-chip 50Ωterminated). In this configuration, no balun transformer is needed to con-
vert properly the single-ended mixer output to balanced differential signals for the
analog inputs.
In the same way, no balun is necessary to feed the TS83102G0B clock inputs with bal-
anced signals.
Directly connect the RF sources to the in-phase analog and clock inputs of the
converter.
However, dynamic performances can be somewhat improved by entering either analog
or clock inputs in differential mode.
3.2 Operating
Procedure (ECL
Mode)
1. Connect the power supplies and Ground accesses
(VCC = +5V, GND = 0V, VPLUSD = 0V, VEE = DVEE = -5V) through the dedicated
banana jacks.
The -5V power supplies should be turned on first.
Note: one single -5V power supply can be used for supplying the digital DVEE and
analog VEE power planes.
2. The board is set by default for digital outputs in binary format.
3. Connect the CLK clock signal.
The inverted phase clock input CLKB may be left open (as on-chip 50Ωtermi-
nated). Use a low phase noise RF source. The clock input level is typically
4 dBm and should not exceed +10 dBm into the 50Ωtermination resistor (maxi-
mum ratings for the clock input power level is 15 dBm).

Operating Procedures and Characteristics
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4. Connect the analog signal VIN. The inverted phase clock input VINB may be left
open (as on cavity 50Ωterminated). Use a low phase noise RF source. Full
scale range is 0.5V peak to peak around 0V, (±250 mV), or -2 dBm into 50Ω.
Input frequency can range from DC up to 1.8 GHz. At 3.0 GHz, the ADC attenu-
ates the input signal by -3 dB. The board insertion loss (S21) will be furnished in
the definitive document release.
5. Connect the high speed data acquisition system probes to the output connector.
The connector pitch (2.54 mm) is compatible with high speed digital acquisition
system probes. The digital data are on-board differentially terminated. However,
the output data can be picked up either in single-ended or differential mode.
3.3 Use with DMUX
Evaluation Board The TSEV81102G0 DMUX evaluation board has been designed to be fully compatible
with the TSEV83102G0B ADC evaluation board.
The DEMUX input configuration has been optimized to be connected to the
TS83102G0B ADC (CBGA152 package).
When using the DEMUX board with the ADC board, do not forget to set, for proper use,
CLKINTYPE in mode DR/2 (jumper on-board).
The power-up sequence should be:
1. Supply the ADC first
2. Supply the DMUX
3. Perform an asynchronous reset on the DMUX board
When this power up sequence has been completed, the synchronization between the
DEMUX and ADC boards can be achieved via the DEMUXDelADjCtrl potentiometer on
the DEMUX evaluation board. To achieve a good synchronization between the two
boards, it is recommended to run the ADC at its full speed (max sampling rate) and tune
the DEMUX Delay Adjust Control potentiometer to the left and take down the settings for
which the boards are de-synchronized and similarly to the right to see the loss of syn-
chronization at the other extremity. The right setting of the potentiometer is in the middle
of these two settings and should be right for all sampling rates of the ADC.
Please refer to the "ADCs and Demux Application Notes" document for more
information.

Operating Procedures and Characteristics
TSEV83102G0B - Evaluation Board User Guide 3-3
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3.4 Electrical
Characteristics
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat
sink is mandatory.
Table 3-1. Absolute Maximum Ratings
Parameter Symbol Comments Value Unit
Positive supply voltage VCC GND to 5.5 V
Digital negative supply voltage DVEE GND to -5.5 V
Digital positive supply voltage VPLUSD GND -1.1 to 2.0 V
Negative supply voltage VEE GND to -5.5 V
Maximum difference between negative supply voltages DVEE to VEE 0.3 V
Analog input voltages VIN or VINB -1.5 to +1.5 V
Maximum difference between VIN and VINB VIN - VINB -1.5 to +1.5 V
Clock input voltage VCLK or VCLKB -1 to +1 V
Maximum difference between VCLK and VCLKB VCLK - VCLKB -1 to +1 V
Static input voltage VDGA/SDA -5 to +0.8 V
Digital input voltage VDSDAEN, DRRB,
B/GB, PGEB -5 to +0.8 V
Digital output voltage VOVPLUSD -2.2 to VPLUSD +0.3 V
Maximum junction temperature Tj+125 °C
Storage temperature Tstg -65 to +150 °C
Lead temperature (soldering 10s) Tleads +300 °C

Operating Procedures and Characteristics
3-4 TSEV83102G0B - Evaluation Board User Guide
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3.5 Operating
Characteristics The power supplies denoted by VCC, VEE, DVEE and VPLUSD are dedicated to the
TS83102G0B ADC.
The power supplies denoted VEET, VDD are dedicated to the optional MC100EL16 asyn-
chronous differential receivers.
Table 3-2. Electrical Operating Characteristics
Parameter Symbol
Value
UnitMin Typ Max
Positive supply voltage
(dedicated to TS83102G0B ADC only)
VCC 4.75 5 5.25 V
VPLUSD –ECL: -0.8
LVDS: 1.6 –V V
VEEA -5.25 -5 -4.75 V
VEED -5.25 -5 -4.75 V
Positive supply current
(dedicated to TS83102G0B ADC only)
ICC – 144 205 mA
IPLUSD –164–mA
IEEA – 514 630 mA
IEED – 170 180 mA
Positive supply voltage not used by default – installed
(dedicated to MC100EL16 differential receivers) VEET -5.25 -5 -4.75 V
VDD -2.15 -2 -185 V
Positive supply current not used by default – installed
(dedicated to MC100EL16 differential receivers) IEET –180–mA
IDD –480–mA
Nominal power dissipation (without receivers) PD – 4.6 5.1
(TJ= 125°C) W
Analog input impedance ZIN –50–Ω
Full power analog input bandwidth (-3 dB) – – 3.0 – GHz
Analog input voltage range (differential mode) VIN -125 – 125 mV
Clock input impedance – – 50 – Ω
Clock input voltage compatibility (single-ended or
differential) (See Application Notes) – ECL levels or 4 dBm (typ) into 50Ω–
Clock input power level into 50Ωtermination resistor – -2 2 4 dBm

TSEV83102G0B - Evaluation Board User Guide 4-1
Rev. 2166B–BDC–04/03
Section 4
Application Information
4.1 Introduction For this section, also refer to the product "Main features" (TS83102G0B Datasheet).
More particularly, refer to sections related to single-ended and differential input
configurations.
4.2 Analog Inputs The analog inputs can be entered in differential or single-ended mode without any high
speed performance degradation.
The board digitizes single-ended signals by choosing either input and leaving the other
input open, as the latter is on-board 50Ωterminated. The nominal in-phase inputs are
VIN (See Section 3).
4.3 Clock Inputs The clock inputs can be entered in differential or single-ended mode without any perfor-
mance degradation for a clock frequency up to 500 MHz. At higher rates, it is
recommended to drive the clock inputs differentially. Moreover, the typical in phase
clock input amplitude is 1V peak to peak, centered on 0V (Ground), or -1.3V (ECL) on
common mode.
As for the analog input, either clock input can be chosen (if the single-ended output
mode is used), leaving the other input open, as both clock inputs are on-chip 50Ωtermi-
nated. The nominal in-phase clock input is CLK (Section 3).
4.4 Setting the
Digital Output
Data Format
For this section, refer to the Evaluation Board Electrical schematic and to the compo-
nents placement document (respectively Figure 6-1 on page -2 and Figure 6-6 on page
-3).
Refer also to the TS83102G0B specification about digital output coding.
The TS83102G0B delivers data in natural binary code or in Gray code. If the B/GB input
is left floating or tied to GND the data format selected will be natural binary, if this input
is tied to VEE the data will follow the Gray code.
Use the jumper denoted B/GB to select the output data port format:
If B/GB is left floating or tied to GND, the data output format is true binary.
If B/GB is tied to VEE or driven with ECL low level, the data outputs are in the Gray
format.

Application Information
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The VPLUSD positive supply voltage allows the adjustment of the output common mode
level from -1.05V (VPLUSD = -0.8V for ECL output compatibility) to +1.35V (VPLUSD = 1.6V
for LVDS output compatibility).
Each output voltage varies between -0.9V and -1.2V (respectively +1.2V and +1.5V),
leading to ±0.3V = 660 mV in differential for VPLUSD = -0.8V (respectively 1.6V).
4.5 ADC Gain Adjust The ADC gain is adjustable by the means of pin R9 (pad input impedance is 1 MΩin
parallel with 2 pF). A jumper denoted GAIN has been foreseen in order to have access
to the ADC gain adjust pin.
The GAIN potentiometer is dedicated to adjusting the ADC gain from approximately
0.85 up to 1.15.
The gain adjust transfer function is given below.
Figure 4-1. ADC Gain Adjust
4.6 SMA Connectors
and Microstrip
Lines De-
embedding
Fixture
Attenuation in microstrip lines can be found by taking the difference in the log magni-
tudes of the S21 scattering parameters measured on two different lengths of
meandering transmission lines.
Such a measurement also removes common losses such as those due to transitions
and connectors.
The S21 scattering parameter corresponds to the amount of power transmitted through
a two-port network.
The characteristic impedance of the microstrip meander lines must be close to 50Ωto
minimize impedance mismatch with the 50Ωnetwork analyzer test ports.
Impedance mismatch will cause ripples in the S21 parameter as a function of both the
degree of mismatch and the length of the line.
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-600 -400 -200 0 200 400 600
Vgain (command voltage) (mV)
ADC Gain

Application Information
TSEV83102G0B - Evaluation Board User Guide 4-3
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4.7 Die Junction
Temperature
Monitoring
Figure 4-2 and Figure 4-3 illustrate the recommanded implementation of the die junction
temperature monitoring function for the Revision B of the 10-bit 2 Gsps ADC.
The user has the choice between two possible configurations:
1. The ADC decimation test mode is NOT ALLOWED.
Because of the use of 1 internal diode-mounted transistors, the user has to implement
2 x 2 head-to-tail protection diodes to avoid potential reverse current flows to damage
the diode pin.
Note that Atmel usually recommends the use of 2 x 3 head-to-tail protection diodes but
in this particular case, it is necessary to have exactly 2 diodes in the A10 to ground
direction of conduction.
Figure 4-2. Recommended Die Junction Temperature Monitoring Function Implemen-
tation, Test Mode Not Allowed
2. The ADC test mode can be allowed
In case the user wants to still be able to switch from the normal mode to the test mode or
to the die junction temperature monitoring, the protection diode configuration is slightly
different and takes into account the fact that the test mode can be activated by applying
VEE = -5V to the diode pin.
This explains why 7 protection diodes are needed in the other direction, as described in
Figure 4-3.
Figure 4-3. Recommended Diode Pin Implementation Allowing for Both Die Junction
Temperature Monitoring Function and Test Mode
A10
GND
Idiode
IGND
ADC Pin 1 mA
Vdiode
VGND
V
A10
GND
Idiode
IGND
ADC Pin 1 mA
Vdiode
VGND
V

Application Information
4-4 TSEV83102G0B - Evaluation Board User Guide
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For Revision B, the VDIODE characteristic corresponds to a single diode characteristic
over temperature, thus starting at 0.9V, as illustrated in Figure 4-4, which is only an
interpolated VDIODE characteristic (to be confirmed by future measurements).
This modification in Revision B devices implies the modification of the processing of the
VDIODE characteristic if any but above all, it allows the user to implement a digital temper-
ature sensor to be interfaced with the ASIC (DSP, FPGA, etc...) loading the ADC.
Figure 4-4. Diode Pin Implementation in Test Mode
A typical configuration with a standard digital temperature sensor is depicted in
Figure 4-5.
Figure 4-5. Typical Configuration with a Digital Temperature Sensor
A10
GND
ADC Pin VEE = -5V
A10
GND
DXT
DXN
Temperature
Sensor

Application Information
TSEV83102G0B - Evaluation Board User Guide 4-5
2166B–BDC–04/03
The expected diode mounted transistors VDIODE value (including chip parasitic resis-
tance) versus junction temperature is given in Figure 4-6 (IDIODE = 1 mA).
Figure 4-6. Junction Temperature Versus Diode Voltage for I = 1 mA
Note: The operating die junction temperature must be kept below 125°C; therefore, an ade-
quate cooling system has to be set up.
4.8 Decimation
Function The decimation function can be used for debug of the ADC at initial stages. This function
indeed allows to reduce the ADC output rate by 32, thus allowing for a quick debug
phase of the ADC at maximum speed rate.
When active, this fuction makes the ADC output only 1 out of 32 data, thus resulting in a
data rate which is 32 times slower than the clock rate.
4.9 Pattern
Generator
Enable
The TS83102G0B is able to generate by itself (without any analog input signal) a serie
of patterns. If the TEST input is left floating or tied to GND the TS83102G0B will digitize
the analog input signal according to B/GB. If this input is driven with ECL low level or
tied to VEE, TS83102G0B will generate Checker Board patterns.
Use the jumper denoted TEST for enabling the pattern generator.
790 0-10 2010 4030 6050 8070 10090 110
810
830
850
870
890
910
930
800
820
840
860
880
900
920
940
Diode Voltage (mV)
Junction Temperature (°C)

Application Information
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4.10 Data Ready
Output Signal
Reset
A sub-screw connector is provided for the DRRB command.
The Data Ready signal is reset on the falling edge of the DRRB input command, on ECL
logical low level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output sig-
nal master reset. As long as DRRB remains at a logical low level, (or tied to VEE = -5V),
the Data Ready output remains at logical zero and is independent of the external free
running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps
typically.
TRDR is measured between the -1.3V point of the falling edge of the DRRB input com-
mand and the zero crossing point of the differential Data Ready output signal (DR,
DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
The Data Ready output signal restarts on the DRRB command rising edge, ECL logical
high levels (-0.8V).
DRRB may also be grounded, or is allowed to float, for normal free running of the Data
Ready output signal.
4.11 Sampling Delay
Adjusting One delay adjust, controlled by SDA potentiometer, is available in order to add a delay
to the input clock of the ADC. This allows the user to tune the instant of the internal sam-
pling. To enable this delay adjustment there is an SDAEN pin on the chip. In the current
revision, the SDAEN function corresponds to the OA labels (OA jumper and OA
potentiometer).
The OA potentiometer has been removed and short-circuited to VEE.
Use the jumper denoted OA to enable the sampling delay adjustment:
If OA is left floating or tied to GND, the SDA is disabled
If OA is tied to VEE, the SDA is enabled
The SDA input varies from -0.5 to 0.5V, according to the SDA potentiometer position.
The variation of the delay around its nominal value as a function of the SDA voltage is
more or less linear, as shown in Figure 4-7 (simulation results).
Figure 4-7. Sampling Delay Adjust
Note: The variation of the delay as a function of temperature is insignificant.
400p
300p
200p
100p
-500m -400m -300m -200m -100m 100m
SDAVAL
Delay
200m 300m 400m 500m0m
Delay in the variable delay cell at 60°C
: (cross(clip((VT("delop") - VT("delon")) 4e-10 2e-09) 0 2 "rising") - cross(clip((VT("delip") - VT("delin")) 2.5e-10 2e-09) 0 2 "rising")) (60°C)

Application Information
TSEV83102G0B - Evaluation Board User Guide 4-7
2166B–BDC–04/03
4.12 Test Bench
Description Figure 4-8. Differential Analog and Clock Input Configuration
Figure 4-9. Single-ended Analog and Clock Input Configuration
RF Generator
RF Generator
-121 dBc/Hz at 1 KHz
offset from fc
0 −180°
Hybrid
0 −180°
Hybrid
BPF
Data Acquisition
System TS83102G0B
ADC
-117 dBc/Hz at 20 KHz
offset from fc
PC
GPIB
CLKB CLK
DR
10 Data
Tunable delay line
VINB
VIN
Synchro 10 MHz
BPF
Data Acquisition
System TS83102G0B
ADC
PC
GPIB
(50Ω) CLKB CLK
DR
10 Data
Tunable delay line
VINB (50Ω)
VIN
Synchro 10 MHz
RF Generator
RF Generator