Atmel ATA3741 Series User manual

Features
•Minimal External Circuitry Requirements, No RF Components on the PC Board Except
Matching to the Receiver Antenna
•High Sensitivity, Especially at Low Data Rates
•Sensitivity Reduction Possible Even While Receiving
•Fully Integrated VCO
•Low Power Consumption Due to Configurable Self Polling with a Programmable Time
Frame Check
•Supply Voltage 4.5V to 5.5V
•Operating Temperature Range –40°C to +105°C
•Single-ended RF Input for Easy Adaptation to λ/ 4 Antenna or Printed Antenna on PCB
•Low-cost Solution Due to High Integration Level
•ESD Protection According to MIL-STD. 883 (4 KV HBM) Except Pin POUT (2 KV HBM)
•High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW
Front-end Filter
– Up to 40 dB is Thereby Achievable with Newer SAWs
•Programmable Output Port for Sensitivity Selection or for Controlling External
Periphery
•Communication to the Microcontroller Possible via a Single, Bi-directional Data Line
•Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
•2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)
1. Description
The ATA3741 is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel's PLL
RF transmitter U2741B. Its main applications are in the areas of telemetering, security
technology, and keyless-entry systems. It can be used in the frequency receiving
range of f0= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-
ments made below refer to 433.92-MHz and 315-MHz applications.
UHF ASK
Receiver IC
ATA3741
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ATA3741
Figure 1-1. System Block Diagram
Figure 1-2. Block Diagram
Demod Control
ATR3741 1...3
U2741B
Antenna
Antenna
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
Keys
Microcontroller
PLL XTO
VCO
LNA
PLL
VCO
XTO
Encoder
ATARx9x
Power
amp.
FSK/ASK
Demodulator
and data filter
IF Amp
4
th
Order
LPF
3 MHz
DEMOD_OUT
Limiter out
RSSI
Sensitivity
reduction
Standby logic
Polling circuit
and
control logic
FE CLK
VCO XTO
÷ 64
f
50 kΩ
V
S
FSK/ASK
CDEM
AVCC
SENS
AGND
DGND
MIXVCC
LNAGND
LNA_IN
DATA
ENABLE
TEST
POUT
MODE
LFGND
LFVCC
XTO
LF
DVCC
LNA
LPF
3 MHz
IF Amp

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ATA3741
2. Pin Configuration
Figure 2-1. Pinning SO20
SENS
FSK/ASK
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
DATA
ENABLE
TEST
POUT
MODE
DVCC
XTO
LFGND
LF
LFVCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Table 2-1. Pin Description
Pin Symbol Function
1 SENS Sensitivity-control resistor
2 FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK
3 CDEM Lower cut-off frequency data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer
9 LNA_IN RF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply
16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)
17 POUT Programmable output port
18 TEST Test pin, during operation at GND
19 ENABLE
Enables the polling mode
Low: polling mode off (sleep mode)
High: polling mode on (active mode)
20 DATA Data output/configuration input

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3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal into
a 1-MHz IF signal. As seen in the block diagram, the front end consists of an LNA (low noise
amplifier), LO (local oscillator), a mixer, and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) gen-
erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO
is divided by a factor of 64. The divided frequency is compared to fXTO by the phase frequency
detector. The current output of the phase frequency detector is connected to a passive loop filter
and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF
is controlled in a way that fLO / 64 is equal to fXTO. If fLO is determined, fXTO can be calculated
using the following formula:
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The
crystal should be connected to GND via a capacitor CL according to Figure 3-1. The value of the
capacitor is recommended by the crystal supplier. The value of CL should be optimized for the
individual board layout to achieve the exact value of fXTO and thereby of fLO. When designing the
system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be
considered.
Figure 3-1. PLL Peripherals
The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz.
This value for BLoop exhibits the best possible noise performance of the LO. Figure 3-1 shows
the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo-
nents are changed for any reason, please note that the maximum capacitive load at pin LF is
limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO can-
not settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling
also will not work .
fXTO
fLO
64
--------=
DVCC
XTO
LF
LFVCC
LFGND
V
S
C
L
C10
R1
C9
R1 = 820Ω
C9 = 4.7 n
F
C10 = 1 nF
V
S

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fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following for-
mula:
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF
frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter
is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and
fLO that depends on the logic level at pin mode. This is described by the following formulas:
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applica-
tions. For applications where fRF = 315 MHz, MODE must be set to “0”. In the case of
fRF = 433.92 MHz, MODE must be set to ”1”. For other RF frequencies, fIF is not equal to 1 MHz.
fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the dif-
ferent conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of LNA_IN is specified in “Electrical Characteristics” on page
23. The parasitic board inductances and capacitances also influence the input matching. The RF
receiver ATA3741 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA.
Hence, noise matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef =40dB
can be achieved. There are SAWs available that exhibit a notch at ∆f=2MHz.TheseSAWs
work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also
improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 3-2 on page 6 shows a typical input matching network for fRF = 315 MHz and
fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50Ωwith-
out a SAW. The input matching networks shown in Figure 3-3 are the reference networks for the
parameters given in the “Electrical Characteristics” on page 23.
fLO fRF fIF –=
MODE 0 (USA) fIF
fLO
314
----------==
MODE 1 (Europe) fIF
fLO
432.92
------------------==
Table 3-1. Calculation of LO and IF Frequency
Conditions Local Oscillator Frequency Intermediate Frequency
fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz
fRF = 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz
300 MHz < fRF < 365 MHz, MODE = 0
365 MHz < fRF < 450 MHz, MODE = 1
fLO
fRF
11
314
----------+
-------------------=fIF
fLO
314
----------=
fLO
fRF
11
432.92
------------------+
----------------------------=
fIF
fLO
432.92
------------------=

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Figure 3-2. Input Matching Network With SAW Filter
Figure 3-3. Input Matching Network Without SAW Filter
Please note that for all coupling conditions (Figure 3-2 and Figure 3-3), the bond wire inductivity
of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond
wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large
enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily
printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to
2dB.
IN
IN_GND
OUT
OUT_GND
CASE_GND
B3555
ATA3741
C3
22p
L
25n
C16
100p
C17
8.2p
L3
27n TOKO LL2012
27NJ
C2
8.2 pF
L2
TOKO LL2012
F33NJ
33n
1
2
3, 4 7, 8
5
6
8
9
RF
IN
f
RF
= 433.92 MHz
LNAGND
LNA_IN
IN
IN_GND
OUT
OUT_GND
CASE_GND
B3551
ATA3741
C3
47p
L
25n
C16
100p
C17
22p
L3
47n TOKO LL2012
F47NJ
C2
10 pF
L2
TOKO LL2012
F82NJ
82n
1
2
3, 4 7, 8
5
6
8
9
RF
IN
f
RF
= 315 MHz
LNAGND
LNA_IN
ATA3741
15p 25n
3.3p 100p
22n TOKO LL2012
F22NJ
8
9
RF
IN
f
RF
= 433.92 MHz
LNAGND
LNA_IN
ATA3741
33p 25n
3.3p 100p
39n TOKO LL2012
F39NJ
8
9
RF
IN
f
RF
= 315 MHz
LNAGND
LNA_IN

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4. Analog Signal Processing
4.1 IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter.
The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF =433.92MHz
is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center
frequency.
The ATA3741 is available with 2 different IF bandwidths. ATA3741-M2, the version with
BIF = 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter U2741B is used.
The receiver ATA3741-M3 employs an IF bandwidth of BIF = 600 kHz. This version can be used
together with the U2741B in FSK and ASK mode. If used in ASK applications, it allows higher
tolerances for the receiver and PLL transmitter crystals. SAW transmitters exhibit much higher
transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use
BIF = 600 kHz together with such transmitters.
4.2 RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into
the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is
operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode.
If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the
maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic
range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to
the RF input signal at full sensitivity.
In FSK mode, the SNR is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red.
VTh_red is determined by the value of the external resistor RSense. RSense is connected between
pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. This
makes it possible to operate the receiver at lower sensitivity.
If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity
is defined by the value of RSense, the maximum sensitivity by the SNR of the LNA input. The
reduced sensitivity is dependent on the signal strength at the output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sen-
sitivity values given in the electrical characteristics refer to a specific input matching. This
matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity.
RSense can be connected to VS or GND via a microcontroller or by the digital output port POUT of
the ATA3741 receiver IC. The receiver can be switched from full sensitivity to reduced sensitivity
or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal
does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin
DATA will disappear when the input signal is lower than defined by the reduced sensitivity.
Instead of the data stream, the pattern shown in Figure 4-1 is issued at pin DATA to indicate that
the receiver is still active.
Figure 4-1. Steady L State Limited DATA Output Pattern
DATA t
DATA_L_max
t
min2

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ATA3741
4.3 FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK
demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic “L” sets the
demodulator to FSK, Logic “H” sets it into ASK mode.
In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection refer-
ence voltage to a value where a good SNR is achieved. This circuit also implies the effective
suppression of any kind of in-band noise signals or competing transmitters. If the SNR exceeds
10 dB, the data signal can be detected properly.
The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥20 kHz. Lower values
may be used, but the sensitivity of the receiver will be reduced. The minimum usable deviation is
dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are
available. In FSK mode, the data signal can be detected if the SNR exceeds 2 dB.
The output signal of the demodulator is filtered by the data filter before it is fed into the digital
signal processing circuit. The data filter improves the SNR as its bandpass can be adopted to
the characteristics of the data signal. The data filter consists of a 1st-order high-pass filter and a
1st-order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to pin
CDEM. The cut-off frequency of the high-pass filter is defined by the following formula:
In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption.
Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other
hand, CDEM must be large enough to meet the data filter requirements according to the data
signal. Recommended values for CDEM are given in the “Electrical Characteristics” on page 23.
The values are slightly different for ASK and FSK mode.
The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (Section “Configuration of the
Receiver” on page 17). BR_Range must be set in accordance to the used baud rate.
The ATA3741 is designed to operate with data coding where the DC level of the data signal is
50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used,
the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%.
The sensitivity may be reduced by up to 1.5 dB in that condition.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig).
These limits are defined in the “Electrical Characteristics” on page 23. They should not be
exceeded to maintain full sensitivity of the receiver.
4.4 Receiving Characteristics
The RF receiver ATA3741 can be operated with and without a SAW front-end filter. In a typical
automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and
without a SAW front-end filter is illustrated in Figure 4-2 on page 9. This example relates to ASK
mode and the 300-kHz bandwidth version of the ATA3741. FSK mode and the 600-kHz version
of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB. The
plots are printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of
about 4 dB must be considered.
fcu_DF 1
2π× 30 kΩ× CDEM×
-------------------------------------------------------------=

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ATA3741
When designing the system in terms of receiving bandwidth, the LO deviation must be consid-
ered as it also determines the IF center frequency. The total LO deviation is calculated to be the
sum of the deviation of the crystal and the XTO deviation of the ATA3741. Low-cost crystals are
specified to be within ±100 ppm. The XTO deviation of the ATA3741 is an additional deviation
due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is
used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the
IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.
Figure 4-2. Receiving Frequency Response
5. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected does the receiver remain active and
transfer the data to the connected microcontroller. If there is no valid signal present, the receiver
is in sleep mode most of the time, resulting in low current consumption. This condition is called
polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line to save ports to the connected microcontrol-
ler, or it can be operated by up to three uni-directional ports.
5.1 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. As
seen in Figure 5-1 on page 10, this clock cycle TClk is derived from the crystal oscillator (XTO) in
combination with a divider. The division factor is controlled by the logical state at pin MODE. The
frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also
defines the operating frequency of the local oscillator (fLO) (See “RF Front End” on page 4).
-100.0
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
df (MHz)
dP (dB)
without SAW
with SAW

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ATA3741
Figure 5-1. Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the fol-
lowing application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of analog and digital signal processing
• Timing of register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly
used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent
parameters, the electrical characteristics display three conditions for each parameter.
• USA Applications
(fXTO = 4.90625 MHz, MODE = 0, TClk = 2.0383 µs)
• Europe Applications
(fXTO = 6.76438 MHz, MODE = 1, TClk = 2.0697 µs)
• Other applications
(TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic
is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud rate range (BR_Range)
which is defined in the OPMODE register. This clock cycle TXClk is defined by the following for-
mulas for further reference:
BR_Range = BR_Range0: TXClk = 8 ×TClk
BR_Range1: TXClk = 4 ×TClk
BR_Range2: TXClk = 2 ×TClk
BR_Range3: TXClk = 1 ×TClk
DVCC
XTO
MODE
T
Clk
f
XTO
16
15
14
XTO
Divider
:14/:10 L : USA (:10)
H: Europe (:14)

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5.2 Polling Mode
As shown in Figure 3-2 on page 6, the receiver stays in polling mode in a continuous cycle of
three different modes. In sleep mode, the signal processing circuitry is disabled for the time
period TSleep while consuming a low current of IS=I
Soff. During the start-up period, TStartup, all sig-
nal processing circuits are enabled and settled. In the following bit-check mode, the incoming
data stream is analyzed bit by bit against a valid transmitter signal. If no valid signal is present,
the receiver is set back to sleep mode after the period TBitcheck. This period varies check by
check as it is a statistical process. An average value for TBitcheck is given in “Electrical Character-
istics” on page 23. During TStartup and TBitcheck the current consumption is IS=I
Son. The average
current consumption in polling mode is dependent on the duty cycle of the active mode and can
be calculated as:
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the
reception of a transmitted command, the transmitter must start the telegram with an adequate
preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStar-
tup, TBitcheck, and the startup time of a connected microcontroller (TStart_µC). TBitcheck thus depends
on the actual bit rate and the number of bits (NBitcheck) to be tested.
The following formula indicates how to calculate the preburst length.
TPreburst ≥TSleep + TStartup + TBitcheck + TStart_µC
5.2.1 Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, on the
extension factor XSleep according to Figure 5-4 on page 13,and on the basic clock cycle TClk. It is
calculated to be:
In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1.
The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a
second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp, resulting in
a different mode of action as described below:
XSleepStd = 1 implies the standard extension factor. The sleep time is always extended.
XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long
as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically, result-
ing in a regular sleep time. This functionality can be used to save current in the presence of a
modulated disturber similar to an expected transmitter signal. The connected microcontroller is
rarely activated in that condition. If the disturber disappears, the receiver switches back to regu-
lar polling and is again sensitive to appropriate transmitter signals.
As seen in Table 5-6 on page 19, the highest register value of Sleep sets the receiver to a per-
manent sleep condition. The receiver remains in that condition until another value for Sleep is
programmed into the OPMODE register. This function is desirable where several devices share
a single data line.
ISpoll
ISoff TSleep ISon TStartup TBitcheck +()×+×
TSleep TStartup TBitcheck
++
------------------------------------------------------------------------------------------------------------=
TSleep Sleep XSleep ×1024×TClk ×=

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Figure 5-2. Polling Mode Flow Chart
Figure 5-3. Timing Diagram for a Completely Successful Bit Check
Bit-check
OK?
Sleep: 5-bit word defined by Sleep0 to Sleep4 in
OPMODE register
NO
YES
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and polling logic is
enabled.
Output level on pin IC_ACTIVE => low
I
S
= I
SON
T
Sleep
= Sleep ×X
Sleep
×1024 ×T
Clk
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (T
Startup
)
all circuits are in stable condition and
ready to receive.
I
S
= I
SON
T
Startup
Bit-check Mode:
The incoming data stream is analyzed.
If the timing indicates a valid transmitter
signal, the receiver is set to receiving
mode. Otherwise is set to Sleep mode.
I
S
= I
Son
T
Bitcheck
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF command
via pin DATA or ENABLE
I
S
= I
SON
OFF command
X
Sleep
:Extension factor defined by X
SleepTemp
according to Table 5-7
T
Clk
: Basic clock cycle defined by f
XTO
and pin
MODE
T
Startup
:Is defined by the selected baud rate range
and T
Clk
. The baud rate range is defined
by Baud0 and Baud1 in the OPMODE
register.
T
Bitcheck
: Depends on the result of the bit check.
If the bit check is ok, T
Bitcheck
depends
on the number of bits to be checked
(N
Bitchecked
) and on the utilized data rate.
If the bit check fails, the average time
period for that check depends on the
selected baud rate range on T
Clk
. The
baud rate range is defined by Baud0 and
Baud1 in the OPMODE register.
Bit check
Enable IC
DATA
1/2 Bit
Polling mode
Number of Checked Bits: 3
Bit check ok
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Receiving mode
Dem_out

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5.3 Bit-check Mode
In bit-check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge test, before the receiver
switches to receiving mode, is also programmable.
5.3.1 Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the OPMODE
register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBitcheck is set to a
higher value, the receiver is less likely to switch to the receiving mode due to noise. In the pres-
ence of a valid transmitter signal, the bit check takes less time if NBitcheck is set to a lower value.
In polling mode, the bit-check time is not dependent on NBitcheck. Figure 5-3 on page 12 shows an
example where 3 bits are tested successfully and the data signal is transferred to pin DATA.
Figure 5-4 shows how the time window for the bit check is defined by two separate time limits. If
the edge-to-edge time tee is in between the lower bit check limit TLim_min and the upper bit check
limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max,
the bit check will be terminated and the receiver will switch to sleep mode.
Figure 5-4. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between TLim_min and TLim_max.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard. A
good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time tee. Using preburst patterns that contain vari-
ous edge-to-edge time periods, the bit check limits must be programmed according to the
required span.
The bit-check limits are determined by means of the formula below:
TLim_min = Lim_min ×TXClk
TLim_max = (Lim_max –1) ×TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is TXClk. The
minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined in Section “Receiving Mode”
on page 15. Due to this, the lower limit should be set to Lim_min ≥10. The maximum value of
the upper limit is Lim_max = 63.
Dem_out t
ee
Tlim_min
1/fSig
Tlim_max

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ATA3741
Figure 5-5, Figure 5-6 and Figure 5-7 illustrate the bit check for the default bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
TXClk.
Figure 5-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-6, the bit
check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim
reaches Lim_max. This is illustrated in Figure 5-7.
Figure 5-5. Timing Diagram During Bit Check
Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥Lim_max)
Bit check
Enable IC
Dem_out
Bit check
counter 023456 2 451781367891112131410
1/2 Bit
15161718 1 2 3 4 5 6
(Lim_min = 14, Lim_max = 24)
789101112131415
1234
1/2 Bit 1/2 Bit
Bit check ok Bit check ok
T
Startup
T
XClk
Bit check
Enable IC
Bit check
counter 023456 2 451 3 6 7 8 9 111210
1/2 Bit
Startup Mode
0
(Lim_min = 14, Lim_max = 24)
Sleep Mode
Bit check failed ( CV_Lim < Lim_min )
Dem_out
Bit check Mode
1
Bit check
Enable IC
Bit check
counter 023456 2 451736789111210
1/2 Bit
Startup Mode
20
(Lim_min = 14, Lim_max = 24)
Sleep Mode
Bit check failed (CV_Lim = Lim_max)
13141516171819 21222324 01
Dem_out
Bit check Mode

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ATA3741
5.3.2 Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and TBitcheck varies for each check.
Therefore, an average value for TBitcheck is given in “Electrical Characteristics”. TBitcheck depends
on the selected baud rate range and on TClk. A higher baud rate range causes a lower value for
TBitcheck, resulting in lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBitcheck is dependent on the frequency of that sig-
nal, on fSig, and on the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby
results in a longer period for TBitcheck, requiring a higher value for the transmitter preburst
TPreburst.
5.4 Receiving Mode
If the bit check is successful for all bits specified by NBitcheck, the receiver switches to receiving
mode. As seen in Figure 5-3 on page 12, the internal data signal is then switched to pin DATA. A
connected microcontroller can be woken up by the negative edge at pin DATA. The receiver
stays in that condition until it is explicitly switched back to polling mode.
5.4.1 Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range). Figure 5-8 illustrates how Dem_out is synchronized by the extended
clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only
after TXClk elapsed. The edge-to-edge time period tee of the Data signal, as a result, is always an
integral multiple of TXClk.
The minimum time period between two edges of the data signal is limited to tee ≥TDATA_min. This
implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval
tee as illustrated in Figure 5-9 on page 16. If tee is in between the specified bit-check limits, the
following level is frozen for the time period TDATA_min =tmin1;ift
ee is outside that bit check limit,
TDATA_min = tmin2 is the relevant stable time period.
The maximum time period for DATA to be low is limited to TDATA_L_max. This function ensures a
finite response time during programming or switching off the receiver via pin DATA. TDATA_L_max
is thereby longer than the maximum time period indicated by the transmitter data stream. Figure
5-10 on page 16 gives an example where Dem_out remains low after the receiver has switched
to receiving mode.
Figure 5-8. Synchronization of the Demodulator Output
Clock bit check
counter
DATA
T
XClk
Dem_out
t
ee

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ATA3741
Figure 5-9. Debouncing of the Demodulator Output
Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission
After the end of a data transmission, the receiver remains active and random noise pulses
appear at pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is
equal to or slightly higher than TDATA_min.
5.4.2 Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1. Figure 5-11 on page 17 illustrates the timing of the OFF command (see also Figure
5-15 on page 22). The minimum value of t1 depends on the BR_Range. The maximum value for
t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the
reset marker. This item is explained in more detail in Section “Configuration of the Receiver” on
page 17. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the
OPMODE register to 1. Only one sync pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF
command, the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited.
The resulting time constant τtogether with an optional external pull-up resistor may not be
exceeded to ensure proper operation.
If the receiver is set to polling mode via pin ENABLE, an “L” pulse (TDoze) must be issued at that
pin. Figure 5-12 on page 17 illustrates the timing of that command. After the positive edge of this
pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is
held to “L”. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to
“0” to enable an instantaneous response time. This command is the faster option than via pin
DATA, but at the cost of an additional connection to the microcontroller.
DATA
tmin1
Lim_min ≤CV_Lim < Lim_max
Dem_out
t
ee
tmin2
t
ee
CV_Lim < Lim_min or CV_Lim ≥Lim_max
Bit check
Enable IC
DATA
Sleep mode Receiving mode tmin2 Bit check mode t
DATA_L_max
Dem_out

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ATA3741
Figure 5-11. Timing Diagram of the OFF Command Via Pin DATA
Figure 5-12. Timing Diagram of the OFF Command Via Pin ENABLE
5.5 Configuration of the Receiver
The ATA3741 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT.
The registers can be programmed by means of the bi-directional DATA port. If the register con-
tents have changed due to a voltage drop, this condition is indicated by a certain output pattern
called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on
reset (POR), the registers are set to default mode. If the receiver is operated in default mode,
there is no need to program the registers.
Table 5-2 on page 18 shows the structure of the registers. As shown in Table 5-1, bit 1 defines if
the receiver is set back to polling mode via the OFF command, (see Section “Receiving Mode”
on page 15) or if it is programmed. Bit 2 represents the register address; it selects the appropri-
ate register to be programmed.
Out1 (microcontroller)
DATA (U3741BM)
Serial bi-directional
data line
X
Bit 1
("1")
(Start bit)
X
t1 t2 t3
t4
t5
t7
X
X
Startup mode
OFF command
Receiver
on
t10
T
Sleep
ENABLE
DATA (U3741BM)
Serial bi-directional
data line
X
X
X
T
Sleep
X
t
off
Receiver on Startup mode
T
Doze
Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers
Bit 1 Bit 2 Action
1 x The receiver is set back to polling mode (OFF command)
0 1 The OPMODE register is programmed
0 0 The LIMIT register is programmed

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ATA3741
Table 5-3 through Table 5-9 on page 20 illustrate the effect of the individual configuration words.
The default configuration is labeled for each word.
BR_Range sets the appropriate baud rate range. At the same time, it defines XLim. XLim is
used to define the bit check limits TLim_min and TLim_max as shown in Table 5-3.
POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to “1”
to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR.
Table 5-2. Effect of the Configuration Words within the Registers
Bit1 Bit2 Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14
OFF Command
1
OPMODE Register
0 1 BR_Range NBitcheck VPOUT Sleep XSleep
0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleep Std XSleep Temp
(Default)0010001 01100
LIMIT Register
0 0 Lim_min Lim_max
0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
(Default)0011100 11000
Table 5-3. Effect of the Configuration Word BR_Range
BR_Range
Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0
00
BR_Range0 (Application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)
01
BR_Range1 (Application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4
10
BR_Range2 (Application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2
11
BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1
Table 5-4. Effect of the Configuration Word NBitcheck
NBitcheck
Number of Bits to be CheckedBitChk1 BitChk0
00 0
01 3
1 0 6 (Default)
11 9

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ATA3741
Table 5-5. Effect of the Configuration Bit VPOUT
VPOUT Level of the Multi-purpose Output Port POUT
POUT
0 0 (Default)
11
Table 5-6. Effect of the Configuration Word Sleep
Sleep Start Value for Sleep Counter
(TSleep = Sleep ×XSleep ×1024 ×TClk)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0
000000(Receiverpollscontinuouslyuntilavalidsignal occurs)
000011(T
Sleep ≈2 ms for XSleep = 1 in US/European applications)
00010 2
00011 3
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0101111(USA:T
Sleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default)
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11101 29
11110 30
11111 31(Permanent sleep mode)
Table 5-7. Effect of the Configuration Word XSleep
XSleep Extension Factor for Sleep Time
(TSleep = Sleep ×XSleep ×1024 ×TClk)XSleepStd XSleepTemp
0 0 1 (Default)
018(X
Sleep is reset to 1 if bit check fails once)
10 8(X
Sleep is set permanently)
11 8(X
Sleep is set permanently)

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ATA3741
5.5.1 Conservation of the Register Information
The ATA3741 has integrated power-on reset and brown-out detection circuitry to provide a
mechanism to preserve the RAM register information.
Figure 5-13 on page 21 shows the timing of a power-on reset (POR) generated if the supply volt-
age VSdrops below the threshold voltage VThReset. The default parameters are programmed into
the configuration registers in that condition. Once VSexceeds VThReset, the POR is canceled after
the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver
is turned on.
Table 5-8. Effect of the Configuration Word Lim_min
Lim_min Lower Limit Value for Bit Check
(TLim_min = Lim_min ×XLim ×TClk)Lim_min < 10 is not applicable
001010 10
001011 11
001100 12
001101 13
001110 14 (Default)
(USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs)
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111101 61
111110 62
111111 63
Table 5-9. Effect of the Configuration Word Lim_max
Lim_max Upper Limit Value for Bit Check
Lim_max < 12 is not applicable (TLim_max = (Lim_max –1) ×XLim ×TClk)
001100 12
001101 13
001110 14
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011000 24 (Default)
(USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs)
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111101 61
111110 62
111111 63