Atmel AT49BV160D User manual

Features
•Single Voltage Read/Write Operation: 2.65V to 3.6V
•Access Time – 70 ns
•Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
•Fast Word Program Time – 10 µs
•Fast Sector Erase Time – 100 ms
•Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
•Low-power Operation
–10mAActive
– 15 µA Standby
•VPP Pin for Write Protection and Accelerated Program Operation
•WP Pin for Sector Protection
•RESET Input for Device Initialization
•Flexible Sector Protection
•TSOP and CBGA Package Options
•Top or Bottom Boot Block Configuration Available
•128-bit Protection Register
•Minimum 100,000 Erase Cycles
•Common Flash Interface (CFI)
•Green (Pb/Halide-free) Packaging
1. Description
The AT49BV160D(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 46-ball CBGA package. The device
has CE and OE control signals to avoid any bus contention. This device can be read
or reprogrammed using a single power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see “Flexible Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program
and erase functions are inhibited. When VPP is at 1.65V or above, normal program
and erase operations can be performed. With VPP at 10.0V, the program (Dual-word
Program Command) operation is accelerated.
16-megabit
(1M x 16)
3-volt Only
Flash Memory
AT49BV160D
AT49BV160DT
3591A–FLASH–12/05

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AT49BV160D(T)
2. Pin Configurations
2.1 TSOP Top View (Type 1)
2.2 CBGA Top View (Ball Down)
Pin Name Function
A0 - A19 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET Reset
VPP Write Protection
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
VCCQ Output Power Supply
WP Write Protect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
A
B
C
D
E
F
1234567
A13
A14
A15
A16
VCCQ
GND
A11
A10
A12
I/O14
I/O15
I/O7
A8
WE
A9
I/O5
I/O6
I/O13
VPP
RST
I/O11
I/O12
I/O4
WP
A18
I/O2
I/O3
VCC
A19
A17
A6
I/O8
I/O9
I/O10
A7
A5
A3
CE
I/O0
I/O1
A4
A2
A1
A0
GND
OE
8

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AT49BV160D(T)
3. Block Diagram
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be in the read mode. In order to perform other device
functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition Table” on page 15 (I/O8 - I/O15 are don’t care
inputs for the command codes). The command sequences are written by applying a low pulse
on the WE or CE input with CE or WE low (respectively) and OE high. The address and data are
latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.
The address locations used in the command sequences are not affected by entering the com-
mand sequences.
4.2 Read
When the AT49BV160D(T) is in the read mode, with CE and OE low and WE high, the data
stored at the memory location determined by the address pins are asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
INPUT
BUFFER
COMMAND
REGISTER
DATA
REGISTER
Y-GATING
WRITE STATE
MACHINE PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
WP
VPP
VCC
GND
Y-DECODER
X-DECODER
INPUT
BUFFER
ADDRESS
LATCH
I/O0 - I/O15
A0 - A19
MAIN
MEMORY

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4.3 Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device returns to the read mode, depending upon
the state of the control inputs.
4.4 Erase
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1 Sector Erase
The device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector
Erase command is a two-bus cycle operation. The sector address and the D0H Data Input com-
mand are latched on the rising edge of WE. The sector erase starts after the rising edge of WE
of the second cycle provided the given sector has not been protected. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase a sector
is tSEC. An attempt to erase a sector that has been protected will result in the operation terminat-
ing immediately.
4.5 Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus cycle
operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase opera-
tions can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. If the
program status bit is a “1”, the device was not able to verify that the program operation was per-
formed successfully. The status register indicates the programming status. While the program
sequence executes, status bit I/O7 is “0”. While programming, the only valid commands are
Read Status Register, Program Suspend and Program Resume.
4.6 VPP Pin
The circuitry of the AT49BV160D(T) is designed so that the device cannot be programmed or
erased if the VPP voltage is less that 0.4V. When VPP is at 1.65V or above, normal program and
erase operations can be performed. The VPP pin cannot be left floating.

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4.7 Read Status Register
The status register indicates the status of device operations and the success/failure of that oper-
ation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see Table 4-1).
Note: 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Table 4-1. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS SLS R
76543210
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS (SLS)
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out
when polling the status register.

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AT49BV160D(T)
4.7.1 Clear Status Register
The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM
cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error con-
ditions, these bits can be cleared only through the Clear Status Register command. By allowing
the system software to control the resetting of these bits, several operations may be performed
(such as cumulatively programming several addresses or erasing multiple sectors in sequence)
before reading the status register to determine if an error occurred during those operations. The
status register should be cleared before beginning another operation. The Read command must
be issued before data can be read from the memory array. The status register can also be
cleared by resetting the device.
4.8 Flexible Sector Protection
The AT49BV160D(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
4.8.1 Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
4.8.2 Hardlock and Write Protect
The Hardlock sector protection mode operates in conjunction with the Write Protect (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock Soft-
ware command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.

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AT49BV160D(T)
Figure 4-1. Sector Locking State Diagram
Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
Table 4-2. Hardlock and Softlock Protection Configurations in Conjunction with WP
VPP WP
Hard-
lock
Soft-
lock
Erase/
Prog
Allowed? Comments
VCC/5V 0 0 0 Yes No sector is locked
VCC/5V 0 0 1 No Sector is Softlocked. The Unlock command can
unlock the sector.
VCC/5V 0 1 1 No Hardlock protection mode is enabled. The sector
cannot be unlocked.
VCC/5V 1 0 0 Yes No sector is locked.
VCC/5V 1 0 1 No Sector is Softlocked. The Unlock command can
unlock the sector.
VCC/5V 1 1 0 Yes Hardlock protection mode is overridden and the
sector is not locked.
VCC/5V 1 1 1 No Hardlock protection mode is overridden and the
sector can be unlocked via the Unlock command.
VIL xxx No
Erase and Program Operations cannot be
performed.
[000] [001]
[011]
[111]
[101]
[110]
[100]
60h/
D0h 60h/01h
60h/
2Fh
60h/2Fh
60h/D0h 60h/
01h
60h/
D0h
60h/
01h
60h/
2Fh 60h/
2Fh
UNLOCKED LOCKED
WP = VIL =0
WP = VIH =1
Power-Up/Reset
Default
Power-Up/Reset
Default
Hardlocked is disabled by
WP = VIH
60h/D0h = Unlock Command
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Hardlocked

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AT49BV160D(T)
4.8.3 Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features
are enabled. When the device is in the software product identification mode, a read from the
I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, soft-
locked, or hardlocked.
4.9 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the memory. After the Erase Suspend com-
mand is given, the device requires a maximum time of 15 µs to suspend the erase operation.
After the erase operation has been suspended, the system can then read data or program data
to any other sector within the device. An address is not required during the Erase Suspend com-
mand. During a sector erase suspend, another sector cannot be erased. To resume the sector
erase operation, the system must write the Erase Resume command. The Erase Resume com-
mand is a one-bus cycle command. The only valid commands while erase is suspended are
Read Status Register, Product ID Entry, CFI Query, Program, Program Resume, Erase
Resume, Sector Softlock/Hardlock, Sector Unlock.
4.10 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read data from any other
word within the device. An address is not required during the program suspend operation. To
resume the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same and the command sequence for the erase
resume and program resume are the same. The only other valid commands while program is
suspended are Read Status Register, Product ID Entry, CFI Query and Program Resume.
4.11 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed a software operation. For details, see “Operating Modes” on page 19.
Table 4-3. Sector Protection Status
I/O1 I/O0 Sector Protection Status
0 0 Sector Not Locked
0 1 Softlock Enabled
1 0 Hardlock Enabled
1 1 Both Hardlock and Softlock Enabled

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AT49BV160D(T)
4.12 128-bit Protection Register
The AT49BV160D(T) contains a 128-bit register that can be used for security purposes in sys-
tem design. The protection register is divided into two 64-bit sectors. The two sectors are
designated as sector A and sector B. The data in sector A is non-changeable and is pro-
grammed at the factory with a unique number. The data in sector B is programmed by the user
and can be locked out such that data in the sector cannot be reprogrammed. To program sector
B in the protection register, the two-bus cycle Program Protection Register command must be
used as shown in the “Command Definition Table” on page 15. To lock out sector B, the two-bus
cycle Lock Protection Register command must be used as shown in the “Command Definition
Table” . Data bit D1 must be zero during the second bus cycle. All other data bits during the sec-
ond bus cycle are don’t cares. To determine whether sector B is locked out, use the status of
sector B protection command. If data bit D1 is zero, sector B is locked. If data bit D1 is one, sec-
tor B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 16
for the address locations in the protection register. To read the protection register, the Product
ID Entry command is given followed by a normal read operation from an address within the pro-
tection register. After determining whether sector B is protected or not, or reading the protection
register, the Read command must be given to return to the read mode.
4.13 Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters and functions supported by the device. CFI is used to allow the system to
learn how to interface to the flash device most optimally. The two primary benefits of using CFI
are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to any address. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in “Common Flash Interface Definition Table” on page 24. To return
to the read mode, issue the Read command.
4.14 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the
AT49BV160D(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program
function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Program inhibit: VPP is less than VILPP.
4.15 Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can only be driven from 0 to VCCQ + 0.6V.
4.16 Output Levels
For the AT49BV160D(T), output high levels (VOH) are equal to VCCQ - 0.1V (not VCC). For
2.65V -3.6V output levels, VCCQ must be tied to VCC.

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AT49BV160D(T)
5. Word Program Flowchart
Program
Suspend
Loop
Start
Write 40,
Any Address
Wr ite D ata,
Wor d Addr es s
Read-Status
Register
SR7 =
Full Status
Check
(If Desired)
Program
Complete
Suspend?
1
0
No
Ye s
(Setup)
(Confirm)
6. Word Program Procedure
Bus
Operation Command Comments
Write Program
Setup
Data = 40
Addr = Any Address
Write Data Data = Data to program
Addr = Location to program
Read None
Status register data: Toggle CE
or
OE to update status register
Idle None
Check SR7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent Word Program operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to set to the Read state.
7. Full Status Check Flowchart
Read Status
Register
Progr am
Successful
SR3 =
SR1 =
0
0
SR4 =
0
1
1
1VPP Range
Error
Device
Protect Error
Progr am
Error
8. Full Status Check Procedure
Bus
Operation Command Comments
Idle None Check SR3:
1 = VPP Error
Idle None Check SR4:
1 = Data Program Error
Idle None
Check SR1:
1 = Sector locked; operation
aborted
SR3 MUST be cleared before the Write State Machine allows
further program attempts.
If an error is detected, clear the status register before
continuing operations – only the Clear Status Register
command clears the status register error bits.

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9. Program Suspend/Resume
Flowchart
Read Status
Register
SR7 =
SR2 =
Read
Data
Program
Completed
Done
Reading
Program
Resumed
Read
Data
0
No
0
Ye s
1
1
Wr i te F F (Read Array)
Wr i te D 0
Any Address
(Program Resume)
Wr i te FF
(Read
Array)
Start
Wr i te B0
Any Address
(Program Suspend)
Wr i te 70
Any Address
(Read Status)
10. Program Suspend/Resume
Procedure
Bus
Operation Command Comments
Write Program
Suspend
Data = B0
Addr = Any Address
Write Read
Status
Data = 70
Addr = Any address
Read None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle None
Check SR2
1 = Program suspended
0 = Program completed
Write Read Array Data = FF
Addr = Any address
Read None Read data from any word in the
memory
Write Program
Resume
Data = D0
Addr = Any address

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11. Sector Erase Flowchart
Start
No
Suspend
Erase
1
0Ye s
Suspend
Erase
Loop
Write 20,
Write D0,
Address
Read Status
Register
SR7 =
Full Erase
Status Check
(If Desired)
Erase
Complete
(Erase)
(Erase Confirm)
Sector
Sector
Any Address
Sector
12. Sector Erase Procedure
Bus
Operation Command Comments
Write
Sector
Erase
Setup
Data = 20
Addr = Any Address
Write Erase
Confirm
Data = D0
Addr = Sector to be erased (SA)
Read None
Status register data: Toggle CE
or
OE to update status register data
Idle None
Check SR7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase,
or after a sequence of sector erasures.
Write FF after the last operation to enter read mode.
13. Full Erase Status Check Flowchart
0
0
0
1
1,1
1
1
0
Read Status
Register
Erase
Successful
SR1 = Sector
Sector
Locked
Error
SR3 = V
PP
Range
Error
SR4, SR5
=Command
Sequence Er r or
SR5 = Erase
Error
Sector
14. Full Erase Status Check Procedure
Bus
Operation Command Comments
Idle None Check SR3:
1 = VPP Range Error
Idle None
Check SR4, SR5:
Both 1 = Command Sequence
Error
Idle None Check SR5:
1 = Sector Erase Error
Idle None
Check SR1:
1 = Attempted erase of locked
sector; erase aborted.
SR1, SR3 must be cleared before the Write State Machine
allows further erase attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4, SR5.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.

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15. Erase Suspend/Resume Flowchart
Erase
Completed
Read Array
Data
0
0
1
1
Start
Read Status
Register
SR7 =
SR6 =
Erase
Resumed
Done
Reading
Wri te 70,
Any Address (Read Status)
Wr ite B 0,
Any Address (Erase Suspend)
Wri te D 0,
Any Address
(E r ase Re su m e ) Wri te FF (Read A rray)
Read
Data
Wr i te FF
0
(Read Array)
1
16. Erase Suspend/Resume Procedure
Bus
Operation Command Comments
Write Erase
Suspend
Data = B0
Addr = Any address
Write Read
Status
Data = 70
Addr = Any address
Read None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle None
Check SR6
1 = Erase suspended
0 = Erase completed
Write Read or
Program
Data = FF or 40
Addr = Any address
Read or
Write None
Read or program data from/to
sector other than the one being
erased
Write Program
Resume
Data = D0
Addr = Any address

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17. Protection Register Programming
Flowchart
1
0
Start
Wri te C0,
Any Address
Wri te PR
Address Data
Read-Status
Register
SR7 =
Full-Status
Check
(If Desired)
Program
Complete
(Program-Setup)
(Confirm Data)
18. Protection Register Programming
Procedure
Bus
Operation Command Comments
Write Program
PR Setup
Data = C0
Addr = Any Address
Write Protection
Program
Data = Data to Program
Addr = Location to Program
Read None
Status register data: Toggle CE
or
OE to update status register data
Idle None
Check SR7
1 = WSM Ready
0 = WSM Busy
Program Protection Register operation addresses must be
within the protection register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to return to the Read mode.
19. Full Status Check Flowchart
1
1
Read Status
Register Data
Program
Successful
= V
PP
Range Error
Program Error
Register Locked;
Program Aborted
0
0
SR3, SR4
SR3, SR4
SR3, SR4
=
0
=
1
20. Full Status Check Procedure
Bus
Operation Command Comments
Idle None Check SR1, SR3, SR4:
0,1,1 = VPP Range Error
Idle None Check SR1, SR3, SR4:
0,0,1 = Programming Error
Idle None
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
SR3 must be cleared before the Write State Machine allows
further program attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.

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AT49BV160D(T)
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A19 through A8 are don’t care.
2. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 and 18
for details).
3. This fast programming option enables the user to program two words in parallel only when VPP = 9.5V. The addresses,
Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during
manufacturing purposes only.
4. During the second bus cycle, the manufacturer code is read from address 00000H, the device code is read from address
00001H, and the data in the protection register is read from addresses 00081H - 00088H.
5. The status register bits are output on I/O7 - I/O0.
6. Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis-
ter Addressing Table” on page 16.
7. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.
21. Command Definition Table
Command Sequence
Bus
Cycles
1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle
Addr Data Addr Data Addr Data
Read 1 XX FF
Sector Erase/Confirm 2 XX 20 SA(2) D0
Word Program 2 XX 40/10 Addr DIN
Dual-word Program(3) 3XXE0Addr0D
IN0 Addr1 DIN1
Erase/Program Suspend 1 XX B0
Erase/Program Resume 1 XX D0
Product ID Entry(4) 1XX90
Sector Softlock 2 XX 60 SA(2) 01
Sector Hardlock 2 XX 60 SA(2) 2F
Sector Unlock 2 XX 60 SA(2) D0
Read Status Register 2 XX 70 XX DOUT(5)
Clear Status Register 1 XX 50
Program Protection Register 2 XX C0 Addr(6) DIN
Lock Protection Register – Sector B 2 XX C0 80 FFFD
Status of Sector B Protection 2 XX 90 80 DOUT(7)
CFI Query 1 XX 98
22. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
Voltage on VPP
with Respect to Ground ...................................-0.6V to +10.0V

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Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
23. Protection Register Addressing Table
WordUseSectorA7A6A5A4A3A2A1A0
0FactoryA10000001
1FactoryA10000010
2FactoryA10000011
3FactoryA10000100
4UserB10000101
5UserB10000110
6UserB10000111
7UserB10001000

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24. AT49BV160D – Sector Address Table
Sector Size (Bytes/Words) Address Range (A19 - A0)
SA0 8K/4K 00000 - 00FFF
SA1 8K/4K 01000 - 01FFF
SA2 8K/4K 02000 - 02FFF
SA3 8K/4K 03000 - 03FFF
SA4 8K/4K 04000 - 04FFF
SA5 8K/4K 05000 - 05FFF
SA6 8K/4K 06000 - 06FFF
SA7 8K/4K 07000 - 07FFF
SA8 64K/32K 08000 - 0FFFF
SA9 64K/32K 10000 - 17FFF
SA10 64K/32K 18000 - 1FFFF
SA11 64K/32K 20000 - 27FFF
SA12 64K/32K 28000 - 2FFFF
SA13 64K/32K 30000 - 37FFF
SA14 64K/32K 38000 - 3FFFF
SA15 64K/32K 40000 - 47FFF
SA16 64K/32K 48000 - 4FFFF
SA17 64K/32K 50000 - 57FFF
SA18 64K/32K 58000 - 5FFFF
SA19 64K/32K 60000 - 67FFF
SA20 64K/32K 68000 - 6FFFF
SA21 64K/32K 70000 - 77FFF
SA22 64K/32K 78000 - 7FFFF
SA23 64K/32K 80000 - 87FFF
SA24 64K/32K 88000 - 8FFFF
SA25 64K/32K 90000 - 97FFF
SA26 64K/32K 98000 - 9FFFF
SA27 64K/32K A0000 - A7FFF
SA28 64K/32K A8000 - AFFFF
SA29 64K/32K B0000 - B7FFF
SA30 64K/32K B8000 - BFFFF
SA31 64K/32K C0000 - C7FFF
SA32 64K/32K C8000 - CFFFF
SA33 64K/32K D0000 - D7FFF
SA34 64K/32K D8000 - DFFFF
SA35 64K/32K E0000 - E7FFF
SA36 64K/32K E8000 - EFFFF
SA37 64K/32K F0000 - F7FFF
SA38 64K/32K F8000 - FFFFF

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25. AT49BV160DT – Sector Address Table
Sector Size (Bytes/Words)
x16
Address Range (A19 - A0)
SA0 64K/32K 00000 - 07FFF
SA1 64K/32K 08000 - 0FFFF
SA2 64K/32K 10000 - 17FFF
SA3 64K/32K 18000 - 1FFFF
SA4 64K/32K 20000 - 27FFF
SA5 64K/32K 28000 - 2FFFF
SA6 64K/32K 30000 - 37FFF
SA7 64K/32K 38000 - 3FFFF
SA8 64K/32K 40000 - 47FFF
SA9 64K/32K 48000 - 4FFFF
SA10 64K/32K 50000 - 57FFF
SA11 64K/32K 58000 - 5FFFF
SA12 64K/32K 60000 - 67FFF
SA13 64K/32K 68000 - 6FFFF
SA14 64K/32K 70000 - 77FFF
SA15 64K/32K 78000 - 7FFFF
SA16 64K/32K 80000 - 87FFF
SA17 64K/32K 88000 - 8FFFF
SA18 64K/32K 90000 - 97FFF
SA19 64K/32K 98000 - 9FFFF
SA20 64K/32K A0000 - A7FFF
SA21 64K/32K A8000 - AFFFF
SA22 64K/32K B0000 - B7FFF
SA23 64K/32K B8000 - BFFFF
SA24 64K/32K C0000 - C7FFF
SA25 64K/32K C8000 - CFFFF
SA26 64K/32K D0000 - D7FFF
SA27 64K/32K D8000 - DFFFF
SA28 64K/32K E0000 - E7FFF
SA29 64K/32K E8000 - EFFFF
SA30 64K/32K F0000 - F7FFF
SA31 8K/4K F8000 - F8FFF
SA32 8K/4K F9000 - F9FFF
SA33 8K/4K FA000 - FAFFF
SA34 8K/4K FB000 - FBFFF
SA35 8K/4K FC000 - FCFFF
SA36 8K/4K FD000 - FDFFF
SA37 8K/4K FE000 - FEFFF
SA38 8K/4K FF000 - FFFFF

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Notes: 1. The VPP pin can be tied to VCC for faster program operations, VPP pin can be set 9.5V ± 0.5V.
2. X can be VIL or VIH.
3. Refer to “Program Cycle Waveforms” on page 23.
4. VIHPP (min) = 1.65V.
5. VILPP (max) = 0.4V.
6. Manufacturer Code: 001FH, Device Code: 88C3H – AT49BV160D; 88C2H – AT49BV160DT.
7. Additional Device Code is read from address 0003H. Additional Device Code: 0001H – AT49BV160D(T).
Note: 1. In the erase mode, ICC is 25 mA.
26. DC and AC Operating Range
AT49BV160D(T)-70
Operating Temperature (Case) Ind. -40°C - 85°C
VCC Power Supply 2.65V to 3.6V
27. Operating Modes
Mode CE OE WE RESET VPP(1) Ai I/O
Read VIL VIL VIH VIH X(2) Ai DOUT
Program/Erase(3) VIL VIH VIL VIH VIHPP(4) Ai DIN
Standby/Program Inhibit VIH X(2) XV
IH X X High-Z
Program Inhibit
XXV
IH VIH X
XV
IL XV IH X
XXXV
IH VILPP(5)
Output Disable X VIH XV
IH X High-Z
Reset X X X VIL X X High-Z
Product Identification
Software VIH
A0 = VIL, A1 - A19 = VIL Manufacturer Code(6)
A0 = VIH, A1 - A19 = VIL Device Code(6)(7)
28. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ILI Input Load Current VIN = 0V to VCC 2µA
ILO Output Leakage Current VI/O = 0V to VCC 2µA
ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC 15 25 µA
ICC (1) VCC Active Read Current f = 5 MHz; IOUT = 0 mA 10 15 mA
ICC1 VCC Programming Current 25 mA
IPP1 VPP Input Load Current 10 µA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage VCCQ - 0.6 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH Output High Voltage IOH = -100 µA VCCQ - 0.1 V

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29. Input Test Waveforms and Measurement Level
tR, tF< 5 ns
30. Output Test Load
Note: This parameter is characterized and is not 100% tested.
1.5V
2.0V
0.6V
VCCQ
1.8
1.3 3
31. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V