AudioCodes AC4830 C-C Series Product guide

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AC4830xC-C VoPP
Voice over Packet Processor
Data ook
Revision 1.0
Catalog Number LTRT-00060

AC4830xC-C Data Book General
Revision 1.0 1 March 2000
About this Data ook
Purpose and Scope
This Data Book escribes the har ware an timing characteristics, applications an use
of the AC4830xC-C VoPP, Voice over Packet Processors, from Au ioCo es Lt . It is
esigne for rea ing by any regular User without specialist skills but familiar with the
applications, pro ucts an services of Au ioCo es Lt .
Structure of this Manual
The Data Book has the following sections, which will help you to fin the information
you nee :
For Information on: Look at Chapter:
Release Notes, Notices and Warranty General
Contents, Figures and Tables Contents
Overview and Features 1. Introduction
The Interfaces of the AC4830xC-C 2. Functional Interfaces
Specification of the AC4830xC-C. 3. Chip Data and Timing
Applications, Evaluation System and Testing 4. Application Notes
PCM Highway Interface 5. PCM Highway Interface
Full Index of the Data Book Index
Abbreviations and Terminology
Each abbreviation, unless wi ely use , is spelle out in full when first use , an only
In ustry stan ar terms are use throughout this manual. The $ symbol in icates
hexa ecimal notation.
Data ook Revision 1.0 - Release Note
This Data Book escribes the latest Hardware an timing specifications for the
AC4830xC-C. The Software specifications are escribe in “AC4830xC-C Designer’s
Manual”, Catalog Number LTRT-00066.
Acknowledgements
NetFax® an NetCo er® are registere by Au ioCo es Lt .
Au ioCo es acknowle ges that various pro ucts referre to in this manual are subject
to copyright an /or tra emark by their respective registere hol ers.

Au ioCo es Lt .
AC4830xC-C VoPP 2 Catalog Number: LTRT-00060
Notice
This Data Book escribes the AC4830xC-C VoPP (Voice over Packet Processors) from
Au ioCo es Lt .
Information containe in this ocument is believe to be accurate an reliable at the time of
printing. However, ue to ongoing pro uct improvements an revisions, Au ioCo es Lt .
cannot guarantee accuracy of printe material after the Date Publishe nor can it accept
responsibility for errors or omissions.
For Technical Support please contact:
e-mail: [e-mail]
In the US, fax [phone]
In other countries, fax [phone]
© Copyright 2000 Au ioCo es Lt .
This document is subject to change without notice.
Date Publishe : Mar-22-2000 Date Printe : Mar-22-2000
General Warranty.
Au ioCo es Lt . (hereinafter "Au ioCo es") warrants that its Pro ucts (hereinafter "Pro ucts") shall
conform to Au ioCo es’ publishe specifications for a perio of one (1) year. The foregoing warranty
oes not apply to any Pro ucts which have been subject to misuse, neglect, acci ent, or mo ification or
which have been altere an are not capable of being teste by Au ioCo es un er its normal test
con itions. Au ioCo es’ sole obligation to the Purchaser (hereinafter "Buyer") hereun er for Pro ucts
failing to meet the aforesai warranty shall be, at Au ioCo es' iscretion, to replace the non-conforming
Pro ucts or issue the Buyer cre it for the purchase price of the non-conforming Pro ucts, where within
the warranty perio : 1) Au ioCo es has receive written notice of any nonconformity; an 2) After
Au ioCo es' written authorization to o so the Buyer has returne the non-conforming Pro ucts to
Au ioCo es, freight prepai ; an 3) Au ioCo es has etermine that the Pro ucts are non-conforming
an that such nonconformity is not a result of the Buyer’s con uct. No Pro ucts may be use in a life
support application. Au ioCo es warrants that the Pro ucts sol hereun er shall at the time of shipment
be free an clear of liens an encumbrances. This warranty exten s to the Buyer only an may be invoke
by the Buyer for its customers. Au ioCo es shall not accept warranty returns irectly from the Buyer’s
customers or users of the Buyer’s pro ucts or evices. This warranty is in lieu of all other warranties
whether express, implie or statutory inclu ing implie warranties of merchantability or fitness for
particular purpose. Au ioCo es shall not be liable for amages ue to elays in eliveries or use. In no
event shall Au ioCo es be liable for any inci ental or consequential amages ue to breach of this
warranty or for any infringement action initiate by a thir party. The Buyer’s sole reme y for any breach
shall be limite to the reme ies set forth herein an shall not excee the sale price for the Pro ucts.

AC4830xC-C Data Book Contents
Revision 1.0 3 March 2000
Table of Contents
1 Introduction 7
1.1 Overview.....................................................................................................................7
1.2 Features.......................................................................................................................8
2 Functional Description 11
2.1 Overview...................................................................................................................11
2.2 Interfaces...................................................................................................................13
2.2.1 Voice Interface................................................................................................14
2.2.2 PCM Clock Generator.....................................................................................15
2.2.2.1 Examples of External Crystal Use:........................................................16
2.2.3 Host Port Interface ..........................................................................................17
2.2.4 Memory, I/O an CAS Interface......................................................................19
2.2.5 Channel Associate Signaling Port..................................................................21
2.2.6 Test Access Port..............................................................................................23
2.3 HPI on-chip Memory Map .........................................................................................24
2.4 Pin Description ..........................................................................................................25
2.4.1 Signals an Pin-out 144-pin TQFP package .....................................................25
3 Chip Data and Timing 31
3.1 General Specifications ...............................................................................................31
3.2 Electrical Characteristics an Operating Con itions.................................................... 32
3.2.1 Absolute Maximum Ratings over Specifie Temp. Range................................32
3.2.2 Electrical Characteristics.................................................................................34
3.3 Timing Characteristics ...............................................................................................35
3.3.1 Memory an I/O Interface Timing ...................................................................35
3.3.1.1 Memory Rea ....................................................................................... 35
3.3.1.2 Memory Write......................................................................................37
3.3.1.3 General I/O Rea Timing .....................................................................38
3.3.1.4 I/O Write Timing..................................................................................39
3.3.2 PCM Port Timing when External Co ec Use ................................................. 40
3.3.2.1 PCM Port Receive Timing (using Co ec) .............................................40
3.3.2.2 PCM Port Transmit Timing (using Co ec) ............................................41
3.3.3 PCM Port Timing with Clock from PCM Framer.............................................43
3.3.3.1 PCM Port Receive Timing (using PCM Framer) ...................................43
3.3.3.2 PCM Port Transmit Timing (using PCM Framer) ....................................44
3.3.4 Host Port Interface Timing ..............................................................................45
3.3.4.1 Host Port Interface Switching Characteristics........................................45
3.3.4.2 Host Port Interface Timing Requirements .............................................46
3.3.5 Reset Timing ..................................................................................................50
3.3.6 External Crystal Option ...................................................................................51
3.4 Packaging Specifications............................................................................................52
4 Applications 53

Au ioCo es Lt .
AC4830xC-C VoPP 4 Catalog Number: LTRT-00060
4.1 Interface Application Using PCM Framer/Co ec ........................................................53
54
4.2 Interface Application Using Co ec .............................................................................55
5 PCM Highway Interface 57
5.1 E1 PCM Highway ......................................................................................................57
Index....... 59

AC4830xC-C Data Book Contents
.
LIST OF FIGURES
Revision 1.0 5 March 2000
Figure 1-1: AC4830xC-C Chip.................................................................................................................... 7
Figure 2-1: AC4830xC-C Application Diagram for Each Channel .............................................................. 12
Figure 2-2: AC4830xC-C Interface Diagram.............................................................................................. 13
Figure 2-3: AC4830xC-C Voice an Signaling Interface ............................................................................14
Figure 2-4: PLLMUL Register Contents.................................................................................................... 15
Figure 2-5: AC4830xC-C Host Port Interface (HPI) Signals ....................................................................... 17
Figure 2-6: AC4830xC-C Memory & I/O Interface Signals ........................................................................ 19
Figure 2-7: AC4830xC-C CAS Port Interface ............................................................................................ 21
Figure 2-8: E&M AB Signaling ................................................................................................................. 21
Figure 2-9: AC4830xC-C Test Access Port Interface.................................................................................. 23
Figure 2-10: AC4830xC-C HPI Memory Map............................................................................................ 24
Figure 3-1: Memory Rea Timing ............................................................................................................. 36
Figure 3-2: Memory Write Timing............................................................................................................. 37
Figure 3-3: I/O Rea Timing ..................................................................................................................... 38
Figure 3-4: I/O Write Timing ....................................................................................................................39
Figure 3-5: PCM Port Receive Timing Requirements (using Co ec)........................................................... 41
Figure 3-6: PCM Port Transmit Timing Requirements (using Co ec).......................................................... 42
Figure 3-7: PCM Port Receive Timing (using PCM Framer)....................................................................... 43
Figure 3-8: PCM Port Transmit Timing (using PCM Framer) .....................................................................44
Figure 3-9: Rea /Write Access Without HRDY or HAS-............................................................................ 47
Figure 3-10: Rea /Write Access Using HAS- Without HRDY.................................................................... 48
Figure 3-11: Rea /Write Access with HRDY ............................................................................................. 49
Figure 3-12: HRDY Signal when HCS- is Always Low.............................................................................. 50
Figure 3-13: Reset Timing......................................................................................................................... 51
Figure 3-14: Internal Clock Option............................................................................................................ 51
Figure 3-15: TQFP Packaging Specifications ............................................................................................. 52
Figure 4-1: Typical Interface Application (Framer/Co ec).......................................................................... 54
Figure 4-2: Typical Interface Application (Co ec)...................................................................................... 56
Figure 5-1: E1 Timing............................................................................................................................... 57

Au ioCo es Lt .
AC4830xC-C VoPP 6 Catalog Number: LTRT-00060
List of Tables
Table 1-1: Available Features ..................................................................................................................... 9
Table 2-1: External Crystal Examples.........................................................................................................16
Table 2-2: HPI On-chip DPR Registers ......................................................................................................25
Table 2-3: AC4830xC-C Signals an Pin-out TQFP Package (continues on 6 pages) ...................................25
Table 3-1: General Specifications (continues on 2 pages)............................................................................31
Table 3-2: Characteristics over Recommen e Operating Con itions..........................................................33
Table 3-3: Electrical Characteristics...........................................................................................................34
Table 3-4: Memory Rea Timing Requirements .........................................................................................35
Table 3-5: Memory Write Timing Requirements.........................................................................................37
Table 3-6: I/O Rea Timing Parameters .....................................................................................................38
Table 3-7: I/O Write Timing Parameters.....................................................................................................39
Table 3-8: PCM Port Receive Timing Requirements (using Co ec).............................................................40
Table 3-9: PCM Port Transmit Switching Characteristics (using Co ec)......................................................41
Table 3-10: PCM Port Transmit Timing Requirements (using Co ec) .........................................................41
Table 3-11: PCM Port Receive Timing (using PCM Framer).......................................................................43
Table 3-12: PCM Port Transmit Switching Characteristics (using PCM Framer)..........................................44
Table 3-13: PCM Port Transmit Timing (using PCM Framer).....................................................................44
Table 3-14: Host Port Interface Switching Characteristics...........................................................................45
Table 3-15: Host Port Interface Timing Requirements.................................................................................46
Table 3-16: Timing Parameters for Reset....................................................................................................50
Table 3-17: TQFP Thermal Resistance Characteristics................................................................................52

AC4830xC-C Data Book Chapter 1. Intro uction
Revision 1.0 7 March 2000
1 INTRODUCTION
1.1 Overview
The AC4830xC-C Voice over Packet Processors are state-of-the-art systems on a single
chip. They provi e configurable, low-bit-rate voice compression an fax relay functions
for one or two in epen ent voice an fax channels.
There are currently two members of the AC4830xC-C family:
• AC48302C-C - ual channels for client applications
• AC48301C-C - single channel for client applications.
Figure 1-1: AC4830xC-C Chip
ADVANTAGES
• Low cost
• In epen ent channel operation
• Toll quality voice compression
• Robust ban wi th-saving fax relay
• Small footprint
• Low power consumption

Au ioCo es Lt .
AC4830xC-C VoPP 8 Catalog Number: LTRT-00060
APPLICATIONS
• Cable telephony access evices
• SOHO voice/ ata access evices
• DSL access evices
• Voice enable set-top boxes
1.2 Features
• 1 or 2 channels of G.729A, G.723.1, G.727, G.726, G.711 an NetCo er® voice
co ecs
• T.38 or FRF.11 compliant fax relay at 2.4 – 14.4 kbps
• Caller ID generation an etection
• Automatic switching to PCM or ADPCM upon fax/ ata etection
• G.168-compliant 25 ms length, a aptive Echo Canceler
• High performance Voice Activity Detector (VAD) an Comfort Noise Generator
(CNG)
• DTMF etection an generation
• Call Progress an User- efine tones etection an generation
• Clock an Frame Synchronization outputs to an external co ec
• Parallel host processor interface
• Selectable µ-law/A-law PCM co ec interface
• PCM highway interface for voice, fax an ata
• Input an output gain control
• E&M an AB signaling options

AC4830xC-C Data Book Chapter 1. Intro uction
Revision 1.0 9 March 2000
Table 1-1: Available Features
Feature AC48301C-C AC48302C-C
Number of Channels 1 2
G.711, G.726, G.727 √
√√
√
√ √√
√
G.723.1 √
√√
√
√ √√
√
G.729A √
√√
√
√ √√
√
NetCoder √
√√
√
√ √√
√
VAD and CNG √
√√
√
√ √√
√
G.168 Echo Canceler √
√√
√
√ √√
√
Echo Canceler Tail length (ms) 25 25
DTMF TIA 464 √
√√
√
√ √√
√
MF-R1, MF-R2, SS-4, SS-5, AC15 √
√√
√
√ √√
√
Call progress, User defined √
√√
√
√ √√
√
ellcore Std. Caller ID generation &
detection
√
√√
√
√ √√
√
CAS E&M signaling √
√√
√
√ √√
√
Input and output gain control √
√√
√
√ √√
√
G3 Fax relay (T.38-compliant) √
√√
√
√ √√
√
G3 Fax relay (FRF.11-compliant) √
√√
√
√ √√
√
Automatic voice/fax/data switching √
√√
√
√ √√
√
ad Frame Interpolation ( FI) √
√√
√
√ √√
√
µ/A-Law - PCM companding √
√√
√
√ √√
√
Parallel Host Interface (8-bit) √
√√
√
√ √√
√
Power supply - core (V) 1.8 1.8
Power supply - I/O (V) 3.3 3.3
ANSI-C source code driver √
√√
√
√ √√
√
TQFP Package, 144 pins √
√√
√
√ √√
√

Au ioCo es Lt .
AC4830xC-C VoPP 10 Catalog Number: LTRT-00060
Reader’s Notes

AC4830xC-C Data Book Chapter 2. Functional Description
Revision 1.0 11 March 2000
2 FUNCTIONAL DESCRIPTION
2.1 Overview
The AC4830xC-C voice processor family supports one or two low-bit-rate voice, fax or
ata transmission channels. For voice transmission, the analog input is igitize using
an external PCM co ec, input through the AC4830xC-C PCM interface, an
compresse to one of the supporte bit rates. Fax transmissions are automatically
etecte an emo ulate by the integrate NetFax® Engine. Data transmissions are
etecte an cause the AC4830xC-C to switch to PCM mo e. The AC4830xC-C
transfers the resultant bit-stream (compresse voice or emo ulate fax for all the
channels) in packets to the Host processor through the integral Host Port Interface.
The AC4830xC-C performs receive an transmit operations simultaneously. It receives
compresse , packetize speech ata from a remote AC4830xC-C unit, through the Host
Port Interface. It ecompresses speech ata an transmits it through the PCM voice
interface. It also remo ulates an transmits fax signals to the fax machine in analog
form. The fax relay process is transparent for the transmitting an the receiving fax
machines.
Many other built-in features support use of the AC4830xC-C in a wi e range of
integrate voice, fax an ata access, transmission an switching systems.
The features inclu e voice activity etector (VAD), comfort noise generator (CNG) an
a aptive Echo Canceler. A itionally, both In-ban Signaling (Detection an
Generation of: MF-R1, MF-R2, SS-4, SS-5, DTMF tones, Call Progress tones, User-
efine tones) an Channel Associate Signaling (E&M: A an AB) are provi e .
Figure
2-1 on page 12 is a simplifie Application Diagram for each of the AC4830xC-C
channels.

Au ioCo es Lt .
AC4830xC-C VoPP 12 Catalog Number: LTRT-00060
Figure 2-1: AC4830xC-C Application Diagram for Each Channel
Host I/F
Codec/
PCM Highway
Interface
Voice/Fax/Data
Packetizer/
MUX
Voice/Fax/Data
Discriminator/
MUX
G3 FAX Relay
@2400-14400
bps
Baseband Processing
Voice Compression
Voice
· NetCoder @ 6.4-9.6 kbps
· G.711 PCM @ 64 kbps
· G.727 E-ADPCM @ 16-40 kbps
· G.726 ADPCM @ 16-40 kbps
· G.723.1 MP-MLQ @ 6.3/5.3 kbps
· G.729A CS-ACELP @ 8.0 kbps
Host
Processor
· VAD/CNG
· G.168 Echo Cancellation
· DTMF Detection/Generation
· Bad Frame Interpolation
· IBS / CAS / TAP
· User-defined Tones
· Call Progress
Data ByPass

AC4830xC-C Data Book Chapter 2. Functional Description
Revision 1.0 13 March 2000
2.2 Interfaces
The various interfaces are shown below in Figure 2-2, an are escribe in ivi ually in
the following pages.
Figure 2-2: AC4830xC-C Interface Diagram
Host Port Interface
HOST
Memory &
I/O Interface
R/W-
MS-
Data
Address
16-bit
16-bit
8-bit
IOS-
Control
SIGEN-
PCM
Test I/F
Test
Access
Port
Voice
Interface
AC4830xC-C
PCM Clock
Generator
Crystal

Au ioCo es Lt .
AC4830xC-C VoPP 14 Catalog Number: LTRT-00060
2.2.1 Voice Interface
The AC4830xC-C uses the Voice Interface for input an output of uncompresse voice,
ata an fax. It performs voice input an output as a 64 kbps compan e A-Law or µ-
Law PCM.
The voice input is receive through PCMIN, an the voice output is sent through
PCMOUT.
PCMCLK is a 2.048 MHz clock that can be generate internally from the AC4830xC-
C, or externally from a co ec.
PCMFS is the PCM Frame Sync, that is generate every 125 µsec to comply with the
E1 transmission rate of 8,000 frames per sec. PCMFS can be generate internally from
the AC4830xC-C, or externally from a co ec.
The User can attach the AC4830xC-C irectly to a PCM highway.
Figure 2-3: AC4830xC-C Voice and Signaling Interface
HPI
Memory
& I/O
Interface
TAP
PCM OUT
PCM IN
PCMFS
PCMCLK
Voice
Interface
AC4830xC-C
PCM Clock
Generator

AC4830xC-C Data Book Chapter 2. Functional Description
Revision 1.0 15 March 2000
2.2.2 PCM Clock Generator
A built-in PCM Clock Generator enables the sourcing of an external co ec evice, with
the PCM Clock an PCM Frame Sync from the AC4830xC-C. The operation of the
PCM Clock Generator is fully controlle by the PCM Comman Sequence, using the
PCMCLK control.
The PCM Clock Generator can use a wi e range of CLKIN-Crystal clock inputs,
provi ing the User with a cost-effective solution. See Table 2-1 for some examples of
external crystals. The internal circuitry erives the AC4830xC-C working clock
(CLKOUT) from the AC4830xC-C clock input, an also the PCM Clock an the Frame
Sync characteristics.
The setting of the AC4830xC-C working clock is ma e by mo ifying the PLLMUL
fiel of the last wor of the Kernel File, which is the PLLMUL Register, as shown in
Figure 2-4. The PLLMUL range is $00 to $0E. The working clock is in icate by the
CLKOUT signal.
Figure 2-4: PLLMUL Register Contents
it Number 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0
Contents PLLMUL $0 $FE
Special care must be taken while mo ifying the file to avoi amaging its content an to
follow up the require working clock. The working clock range must be in the limits
98.304 to 100.00 MHz. The following section shows some examples of the use of
external crystals, base on the formula:
CLKOUT [98.304 to 100.00] = CLKIN[MHz] x (PLLMUL+1)
Please refer to AC4830xC-C Designer’s Manual, Catalog Number LTRT-00066, for
etails of the PCM Comman sequence.

Au ioCo es Lt .
AC4830xC-C VoPP 16 Catalog Number: LTRT-00060
2.2.2.1 Examples of External Crystal Use:
Table 2-1: External Crystal Examples
Crystal
Frequency MHz
PLLMUL CLKOUT
MHz
Source for
2.048 MHz
Notes
20 4 100 Do Not Use Default Value in Kernel File
25 3 100 Do Not Use See Section
3.3.1 on page 35
16.384 5 98.304 Yes -
12.288 98.304 Yes -
8.192 11 98.304 Yes -
2.048 4 98.304 Do Not Use PLLMUL must be <15

AC4830xC-C Data Book Chapter 2. Functional Description
Revision 1.0 17 March 2000
2.2.3 Host Port Interface
The Host Port Interface (HPI) is an 8-bit parallel port use for communications between
the Host processor an AC4830xC-C. Both the Host processor an AC4830xC-C can
access an exchange information through the on-chip share memory of the
AC4830xC-C. Please refer to the HPI on-chip Memory Map in Figure
2-10 on page 24.
An 8-bit ata bus (HD0 to HD7) exchanges information with the Host. Because of its
16-bit wor structure, the AC4830xC-C expects all transfers to consist of two
consecutive bytes. A e icate pin (HI/LO) in icates whether the first or secon byte is
being transferre .
Two control pins, HRS0 an HRS1, control Host access to the HPI. The Host can
access the internal control register an a ress the internal memory.
The Host can also interrupt the AC4830xC-C by writing to its internal control register.
Conversely, the AC4830xC-C can interrupt the Host with the HINT- signal, which the
Host can acknowle ge an clear.
Figure
2-5 illustrates the signals of the Host Port Interface.
Figure 2-5: AC4830xC-C Host Port Interface (HPI) Signals
VOICE
Interface
Host Port Interface
HOST
MEMORY & I/O
Interface
HD0-HD
AC4830xC-C
HI/LO-
HWR-
HAS-
HRS0-1
HRD-
HR/W-
HRDY
HINT-
HPISEL-
CS-
TAP

Au ioCo es Lt .
AC4830xC-C VoPP 18 Catalog Number: LTRT-00060
The AC4830xC-C has 2 ata strobes (HRD- an HWR-), a rea /write strobe (HR/W-),
an an a ress strobe (HAS-). These strobes establish a “glueless” interface with a
variety of in ustry-stan ar Host processors. The HPI is easily connecte to the Host
with a multiplexe a ress/ ata bus, in ivi ual a ress/ ata buses, a ata strobe, an
either one rea /write strobe or two separate strobes for rea an write.
An HPI rea y pin (HRDY) is provi e for Hosts that support an asynchronous input to
insert wait states. This is useful if the Host is capable of accessing ata at a faster rate
than the maximum HPI access rate. The HRDY pin provi es a convenient way to
automatically a just the Host access rate (no software han shake is necessary).
Note: uring Kernel ownload, access timing to HPI is very different from the
access timing in other modes of operation.