VersaLogic VL-486-4 User manual

Reference
ReferenceReference
Reference
Manual
ManualManual
Manual
VL-486-4
Industrial CPU Card
for the STD 32 Bus

VL-486-4
Industrial CPU Card
for the STD 32 Bus
TM
M486-4

VL-486-4
486SXLC Industrial Computer
for the STD 32 Bus
REFERENCE MANUAL
Doc. Rev. 01/97
VERSALOGIC CORPORATION
WWW.VERSALOGIC.COM
3888 Stewart Road
Eugene, OR 97402
[phone]
Fax [phone]
Contents Copyright ©1997
All Rights Reserved
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied
warranties of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time
without obligation to notify anyone of such changes.
PC/104 and the PC/104 logo are trademarks of the PC/104 Consortium.

iii
Table of Contents
Other References ..............................................................................................................vii
1. Overview...................................................................................................................................1
Using This Manual .............................................................................................................1
Introduction ........................................................................................................................1
PC/AT Compatibility.............................................................................................1
STD BUS Compatibility........................................................................................1
On-Board Memory ................................................................................................2
Hard Disk and Floppy Disk Interface.................................................................... 2
Digital I/O (Opto 22) Interface..............................................................................2
COM Ports.............................................................................................................2
Parallel Port ...........................................................................................................2
Counters/Timers ....................................................................................................2
Real Time Clock with CMOS RAM .....................................................................3
Interrupt Controllers..............................................................................................3
DMA Controllers...................................................................................................3
Watchdog Timer....................................................................................................3
Technical Specifications..................................................................................................... 4
Technical Support...............................................................................................................5
2. DOS Based Quick Start.........................................................................................................7
Introduction ........................................................................................................................7
Installation..........................................................................................................................8
Activating the Battery.........................................................................................................8
Jumper Locations................................................................................................................9
Card Installation ...............................................................................................................10
Monitor and Keyboard Installation ..................................................................................11
Cable Installation..............................................................................................................12
CMOS RAM Setup...........................................................................................................12
CMOS Setup Options.......................................................................................................13
Main CMOS Setup Menu....................................................................................13
Basic CMOS Configuration.................................................................................13
Advanced CMOS Configuration .........................................................................13
Reset CMOS to Last Known Values...................................................................13
Reset CMOS to Factory Defaults........................................................................14
Write to CMOS and Exit.....................................................................................14
Exit Without Changing CMOS............................................................................14
Clearing the CMOS RAM................................................................................................15
3. Configuration.........................................................................................................................17
Hardware Jumper Summary.............................................................................................17
Jumper Block Locations......................................................................................18
Memory Configuration.....................................................................................................21
ROM Configuration.............................................................................................21
Compatible ROM Devices...................................................................................21

Table of Contents
iv
RAM Configuration.............................................................................................22
Compatible RAM Devices...................................................................................22
CMOS RAM Configuration ................................................................................23
Memory Mapping................................................................................................24
I/O Configuration .............................................................................................................25
Using 8-Bit I/O Cards..........................................................................................25
Using 10-Bit I/O Cards........................................................................................25
Using 16-Bit I/O Cards........................................................................................26
COM2 Configuration........................................................................................................ 27
RS-232 Operation................................................................................................27
RS-422 Operation................................................................................................27
RS-485 Operation................................................................................................27
Opto 22 Rack Configuration.............................................................................................29
Rack Power Control.............................................................................................29
Multiprocessor Configuration ..........................................................................................30
Multiprocessor Jumper Configuration.................................................................30
Resistor Pack Configuration................................................................................31
Multiprocessor CPU Reset ..................................................................................31
Interrupt Configuration..................................................................................................... 32
Interrupt Configuration Jumpers .........................................................................33
STD Bus Interrupt Signals...................................................................................34
CPU Interrupt Request Inputs..............................................................................35
Interprocessor Communications Interrupt Configuration ...................................37
Non-maskable Interrupt Configuration ...............................................................37
DMA Configuration..........................................................................................................38
DMA Channel Allocation................................................................................................. 39
Board Initialization...........................................................................................................40
82C836 Initialization...........................................................................................41
82C721 Initialization...........................................................................................42
486SXLC Initialization........................................................................................42
RAM Refresh Initialization.................................................................................43
4. Installation.............................................................................................................................. 45
Introduction ......................................................................................................................45
Activating the Battery.......................................................................................................45
Card Insertion and Extraction........................................................................................... 45
Card Installation ..................................................................................................46
Card Placement....................................................................................................46
STD 32 Bus Installation Guidelines....................................................................46
External Connections........................................................................................................47
Connector Functions............................................................................................47
Connector Locations............................................................................................47
Mating Connectors and Cable Assemblies..........................................................48
Cable Assembly Diagrams ..................................................................................49
J1, J4 – Serial Port Connectors............................................................................50
J2 – Digital I/O Connector...................................................................................51
J3 – LPT1 Parallel Port Connector......................................................................52
J5 – Counter/Timer - Digital I/O - Interrupt Connector...................................... 53

vii.
J6 – DMA Control Signals Connector.................................................................54
L1 – Speaker Connector ......................................................................................55
5. Register Descriptions.......................................................................................................... 57
Introduction ......................................................................................................................57
Register Summary ............................................................................................................57
Direct Memory Access — Channel 1..................................................................58
Direct Memory Access — Channel 2..................................................................59
Direct Memory Access — Page Registers ..........................................................59
COM1 Serial Port................................................................................................60
COM2 Serial Port...............................................................................................60
LPT1 Parallel Port..............................................................................................61
Chipset Registers.................................................................................................61
Floppy Disk Drive Controller.............................................................................. 62
IDE Hard Disk Drive Controller .........................................................................62
Interrupt Controller — Master.............................................................................63
Interrupt Controller — Slave...............................................................................63
Counter/Timers.................................................................................................... 64
Miscellaneous......................................................................................................64
CIO Chip..............................................................................................................64
Special Control Register......................................................................................65
Watchdog Timer Hold-Off Register....................................................................66
Map and Paging Control Register .......................................................................67
6. CIO Chip..................................................................................................................................69
Introduction ......................................................................................................................69
Features................................................................................................................70
Overview..............................................................................................................70
I/O Ports...............................................................................................................70
Ports A and B.......................................................................................................70
Port C...................................................................................................................71
Counter/Timers.................................................................................................... 71
Interrupt Control Logic........................................................................................71
Register Description.........................................................................................................71
Introduction .........................................................................................................71
CIO Registers ......................................................................................................72
Register Access....................................................................................................73
State 0 ..................................................................................................................73
State 1 ..................................................................................................................73
Master Control Registers..................................................................................................74
Master Interrupt Control Register .......................................................................74
Master Configuration Control Register...............................................................76
Port Mode Specification Register........................................................................78
Port Handshake Specification Registers...........................................................................79
Port A/B Handshake Specification Registers......................................................79
Port Command and Status Registers ...................................................................79
Bit Path Definition Registers............................................................................................81
Data Path Polarity Registers................................................................................81
Data Direction Registers......................................................................................81

Table of Contents
vi
Special I/O Control Registers..............................................................................82
Pattern Definition Registers .............................................................................................83
Pattern Polarity Register......................................................................................83
Pattern Transition Register..................................................................................83
Pattern Mask Register..........................................................................................83
Port A and B Data Registers................................................................................84
Port C Data Register............................................................................................85
Counter/Timer Control Registers........................................................................85
Counter/Timer Mode Specification Registers.....................................................85
Counter/Timer Command Status Registers.........................................................87
Counter/Timer Time Constant Registers............................................................. 89
Counter/Timer Current Count Registers .............................................................90
Interrupt Related Registers...............................................................................................90
Interrupt Vector Registers ...................................................................................90
Current Vector Register....................................................................................... 91
I/O Port Operation ............................................................................................................92
Overview..............................................................................................................92
Pattern-Recognition Logic Operation..................................................................92
Bit Port Operation................................................................................................92
Bit Port Simple Operation ...................................................................................92
Bit Port Pattern-Recognition Operation ..............................................................93
Counter/Timer Operation ................................................................................................. 94
Counter/Timer Architecture ................................................................................94
Counter/Timer Sequence Of Events....................................................................95
Initializing the Counter/Timer.............................................................................95
Starting the Counter/Timer..................................................................................96
Countdown Sequence ..........................................................................................96
Ending Condition.................................................................................................97
Counter/Timer Output .........................................................................................98
Linked Sequence..................................................................................................98
Interrupt Operation...........................................................................................................99
Overview..............................................................................................................99
Priority Handling and the CIO.............................................................................99
The Four Interrupt Logic Functions ....................................................................99
Generating the Interrupt Request.........................................................................99
Identification of the Highest-Priority Interrupt Request...................................100
Interrupt Operation............................................................................................101
CIO Initialization............................................................................................................ 101
Introduction .......................................................................................................101
Enable Bits Operation........................................................................................102
Programming ..................................................................................................................102
Interrupt Code Example.....................................................................................103
Appendix A — Schematic.....................................................................................................107
Index...........................................................................................................................................111

vii.
Other References
Chips and Technologies, Inc., [phone],
82C836 Chipset Data Book
Chips and Technologies, Inc., [phone],
82C721 Universal Peripheral Controller II Data Book
Zilog, Inc., [phone],
Z8036 Z-CIO/Z8536 CIO Counter/Timer and Parallel I/O Unit Technical Manual
STD Manufacturers Group, [phone],
STD 32 Bus Specification and Designer’s Guide
Texas Instruments [phone],
TI486SXLC2 Data Book
Microsoft Press, [phone],
The Programmer’s PC Sourcebook
Addison-Wesley, [phone],
The Undocumented PC

VL-486-4 Reference Manual Overview – 1
Overview
This chapter introduces the VL-486-4 CPU card, lists its features and specifications, and
provides a brief overview of the installation and configuration process.
Using This Manual
Each chapter in this manual corresponds to a step in the installation process:
• Chapter 1, “Overview,” lists basic information about the CPU card, specifications, and
system requirements. Use this chapter to familiarize yourself with the card and it’s
capabilities.
• Chapter 2, “DOS Based Quick Start,” describes how to quickly get your DOS based system
set up and running using a VL-486-4 CPU card.
• Chapter 3, “Configuration” describes how to jumper and initialize the CPU card.
• Chapter 4, “Installation,” describes how to install the VL-486-4. It also provides details on
the external connections.
• Chapter 5, “Register Descriptions,” lists all the user-programmable registers on the CPU
card.
• Chapter 6, CIO Chip
• Appendix A, “Schematics” shows the circuit diagrams on the CPU card.
Introduction
The VL-486-4 CPU card features a 32-bit, 50 MHz, clock doubled 486SXLC microprocessor, up
to 4MB RAM, up to 1MB Flash EEPROM or EPROM, two COM ports, one LPT port, digital
I/O and Opto 22 interface, and real time clock. The card can be used as a DOS or non-DOS
computer in either STD 80 or STD 32 Bus systems.
PC/AT COMPATIBILITY
Standard I/O and peripheral interfaces and optional onboard firmware, containing BIOS, self
tests, and a setup utility, bring a diskless PC/AT compatible computer to the STD Bus form
factor.
STD BUS COMPATIBILITY
The VL-486-4 CPU card complies with certain subsets of the STD 32 Bus specification that
allow it to communicate with STD 80 compatible 8-bit and STD 32 compatible 16-bit I/O and
memory cards. In addition, the card fully complies with the STD 80 Bus specification using a
bus speed of 8.33 MHz. The CPU card is compatible with all I/O and memory cards that adhere
to STD 80 specifications.
1

Introduction
2– Overview VL-486-4 Reference Manual
ON-BOARD MEMORY
RAM Two 42-pin SOJ JEDEC compatible sockets accept up to two 1M x 16 dynamic RAM chips
to provide a total of 2M or 4M of 16-bit system memory. The use of 1M x 18 RAM chips will
provide parity error detection if desired.
ROM Two 32-pin PLCC JEDEC compatible sockets accept one or two high density memory
components including 128K x 8, 256K x 8, and 512K x 8 EPROMs and Flash EPROMs. You can
start out with one device, and add a second one when your storage requirements grow. A Flash
File System is available to make the Flash device(s) appear as a bootable disk drive.
HARD DISK AND FLOPPY DISK INTERFACE
The VL-486-4 does not have hard disk or floppy disk interfaces. A Flash File System is included
which allows the CPU to boot from Drive A. Software is pre-installed on the FFS to network the
CPU with a desktop IBM PC using RS-232.
DIGITAL I/O (OPTO 22) INTERFACE
A 34-pin Opto 22 compatible interface is included on the VL-486-4 card for connection to
industry standard Opto 22 I/O racks. The interface can also be used for general TTL interfacing.
A rack power output provides up to 1A at +5V (typical). The power supply line is protected by a
self resetting circuit breaker.
COM PORTS
The two on-board COM ports are hardware and software compatible with the PC/AT
architecture. Baud rates are programmable from 50 baud to 115K baud. COM1 is a standard RS-
232 interface, COM2 can be jumpered for RS-232, RS-422, or RS-485 operation.
PARALLEL PORT
The bi-directional parallel port can be used as a standard PS2 compatible LPT port or as 17
general purpose TTL I/O signals. Each output line has a 24 ma current sink rating. Eight of the
signals are programmable as a group for input or output, three are dedicated output, and five are
dedicated inputs. A strobe signal, which produces a 50 µs pulse under program control, is also
available as an output.
COUNTERS/TIMERS
The VL-486-4 card includes three 8254 type 16-bit counter/timers. One channel provides timing
for dynamic RAM refresh, one channel generates an 18.2 ms DOS interrupt, and another channel
is used to drive the speaker. All channels are available for general purpose timing and periodic
interrupt sources if they are not being used by an operating system.
Also included are three 16-bit counter/timers embedded within the Zilog 8536 Digital I/O chip.
Four control signals for each of these counter/timers are available on an external connector.

Introduction
VL-486-4 Reference Manual Overview – 3
REAL TIME CLOCK WITH CMOS RAM
A battery-backed 146818 compatible real time clock (RTC) provides accurate date and time
functions. This PC/AT compatible RTC also contains 128 bytes of battery-backed CMOS RAM
with 114 bytes available as a system resource to store standard DOS setup parameters. Normally,
DOS requires 51 bytes, leaving 63 bytes for general purpose use.
INTERRUPT CONTROLLERS
Two PC AT compatible 8259 type programmable interrupt controllers (PICs) are provided for
full MS-DOS functionality. Interrupt sources and destinations can be configured with jumper
blocks. Interrupt lines connect to on-card sources, STD Bus sources, and to a user connector.
DMA CONTROLLERS
The VL-486-4 has two DMA controllers which provide a total of eight DMA channels (four 8-bit
channels and four 16-bit channels.) One 8-bit or 16-bit channel (jumper selectable) is available
for general purpose use through a front-plane DMA connector. The remaining channels are
accessible only by software.
WATCHDOG TIMER
A 1232 type watchdog timer provides a degree of protection against hardware and software
failures. When the watchdog timer is enabled, it must be periodically updated by software at
least every 250 ms. A system failure which prevents updating will reset the CPU.

Technical Specifications
4– Overview VL-486-4 Reference Manual
Technical Specifications
Size: Meets all STD 80 and STD 32 Bus mechanical specifications
Storage Temperature:
-40 °C to 85 °C
Free Air Operating Temperature:
0 °C to 65 °C
Power Requirements: (with 8 MB RAM and 1 MB Flash installed)
5V ±5% @ 800 ma
System Reset:
Vcc sensing, resets below 4.7V
Watchdog reset (jumper option)
LPT1/Parallel Interface:
IBM AT and PS/2 Compatible (Bi-directional)
Data Lines:
Output low voltage: 0.5V @ 24 ma
Output high voltage: 2.4V @ -12 ma
Control Lines:
Output low voltage: 0.5V @ 24 ma
Output high voltage: 2.4V @ -150 µA
COM1 & COM2 Interfaces:
IBM AT and PS/2 Compatible
COM2 configurable as RS-232/422/485
Digital I/O (Opto 22) Interface:
16 lines of bi-directional TTL compatible I/O with Rack Power output
Data Lines:
Input high voltage: 2.0V min., 5.3V max.
Input low voltage: -0.3V min., 0.8V max.
Output low voltage: 0.5V @ 3.2 ma
Output high voltage: 2.4V @ -250 µA
Rack Power:
+5V @ 1A Max. (protected with self resettable polyfuse)
Floppy Disk Drive Interface:
None
Hard Disk Drive Interface:
None
Software provided to network CPU with desktop IBM PC via RS-232
Memory Sockets:
RAM:
Two sockets (sequentially addressed):
42-pin SOJ JEDEC; 1Mx16, or 1Mx18 Dynamic RAM
ROM:
Two sockets (64K paged):
32-pin PLCC JEDEC; 128x8, 256x8, 512x8 KB EPROMs or Flash EEPROMs
Memory Speed: (on-board):
RAM: 70 ns
EPROM and Flash EEPROM: 200 ns or faster
Bus Compatibility:
STD 80: Full compliance, 8.33 MHz bus speed
STD 32: Permanent Master; SA16, SA8-I, MB, MX
STD 32: Temporary Master; SA16, SA8-I, MB, {MX}
Specifications are subject to change without notice.

Technical Support
VL-486-4 Reference Manual Overview – 5
Technical Support
If you have problems that this manual can’t help you solve, contact VersaLogic for technical
support at 1-800-824-3163. You can also reach VersaLogic by e-mail at [email protected].

VL-486-4 Reference Manual DOS Based Quick Start – 7
DOS Based Quick Start
This chapter describes how to quickly get your DOS-based system set up and running using the
VL-486-4 CPU card
Introduction
A minimum DOS based run time system requires the CPU card, a BIOS, and a boot device (the
flash file system is the only boot device available on the VL-486-4) containing an operating
system and an application program. In many cases a video card, keyboard and monitor are added
to this list, however, the VL-486-4 does not demand their presence in order to boot.
The flash file system options available from VersaLogic for the 486-4 card (the “h” and “i”
options) contain a bootable version of DOS. The CMOS RAM information is shipped in its
default condition, and will need to be configured for your particular system. The most
convenient method of setting up this information is by using a keyboard and monitor (requires
addition of a video card), however, a method is available to use COM2 to interact with the setup
program.
Typical components of a VL-486-4 DOS based system include:
• VL-486-4 CPU Card
• STD or STD 32 Card Cage
• Standard PC/AT keyboard
• Video/Keyboard Card
• Video Monitor
• Power Supply
Once the cards are jumpered and installed, the console cables connected, the CMOS RAM
correctly configured, and power is applied, the system will boot to the DOS prompt.
2

Installation
8– DOS Based Quick Start VL-486-4 Reference Manual
Installation
Before installing the VL-486-4 CPU card in a card cage, you must confirm that the on-card
battery is activated.
Caution Electrostatic discharge (ESD) can damage cards, disk drives, and other
components. Do the installation procedures described in this chapter only at an
ESD workstation. If such a station is not available, you can provide some ESD
protection by wearing an antistatic wrist strap and attaching it to a metal part on
the card cage.
Cards can be extremely sensitive to ESD and always require careful handling.
After removing the card from its protective wrapper or from the card cage, place
the card on a grounded, static-free surface, component side up. Use an anti-static
foam pad if available, but not the card wrapper. Do not slide the card over any
surface.
The card should also protected during shipment or storage with anti-static foam or
bubble wrap. To prevent damage to the lithium battery, do not use black
conductive foam or metal foil.
Warning! The lithium battery may explode if mistreated. Do not recharge, disassemble, or
dispose of in fire. Dispose of used batteries promptly.
Activating the Battery
The VL-486-4 CPU card is shipped with the battery disconnected. Since the battery provides
backup power to the CMOS RAM and the real time clock circuits when the card is powered
down, the battery must be activated before putting the card in service.
To activate the battery, move jumper V5 to position [2-3] (bottom position) as shown on page
24.