Avago ACPL-P346 User manual

ACPL-P346/W346
Isolated Power MOSFET Gate Driver Evaluation Board
User's Manual
Quick Start
Visual inspection is needed to ensure that the evaluation board is received in good condition.
All part references are designated with sux‘a’and ‘b’ to indicate the lower and the upper inverter arms, respectively. If
part references are made without suxes, then they are valid for both upper and lower inverter arms (except R6, which
is shared).
Figure 1 shows the default connections of the evaluation board:
1. Q1 and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q1 (for TO-220 package) or Q2 (for TO-
247 package) or connected to the driver board through short wire connections from the holes provided at Q1 or Q2.
2. D4 and R7 are not mounted (on solder side). A 12 V Zener diode footprint at D4 is provided to allow for a single DC
power supply of 15 V ~25 V to be applied across VCC2 and VEE if needed. A virtual ground VE(at Source pin of Q1 or
Q2) can then be generated and it acts as the reference point at the source pin of each power MOSFET. VCC2 will then
stay at 12 V above the virtual ground VE. R7 is needed to generate the bias current across D4.
3. S2 and S3 jumpers are shorted by default to connect VEto VEE, assuming that a negative supply is not needed. Note:
If a negative supply is needed, then S2 and S3 jumpers must be removed.
4. Bootstrap diode D3b and resistor R6 are connected by default. These two components are provided to help generate
VCC2b supply through bootstrapping assuming that VCC2a supply is available. Note: Bootstrapping supply works
only when Q1 or Q2 are mounted in a half-bridge conguration and turned on and o through proper PWM driving
signals.
5. S1 is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when VCC1 is supplied. This short can be
removed if IN- cannot be grounded.
6. Upper and lower arms of the inverter will have common VCC1 (and GND1), a provision is made to allow VCC1 to be
connected by solder between upper and lower inverter PCB portions (and GND1 on the solder side).
7. Provisions are also made to allow VCC2 (and VEE) to be generated from VCC1 through a DC/DC converter at IC2. When
this DC/DC converter is used, S2, S3 (and R6) should be disconnected.
Figure 1. Actual ACPL-P346/W346 evaluation board showing default connections
VCC1a and VCC1b (shorted)
GNDa and GNDb on solder side (also shorted)
S1 (shorted) S2 (shorted) S3 on solder side (also shorted)
R6 mounted (shorted)
VCC1b
VCC1a

2
Once inspection is done, the evaluation board can be powered up in ve simple steps. Figure 2 shows you how to test
the top or the bottom half-bridge inverter arms in simulation mode without the need for an actual power MOSFET.
Testing both arms of the half-bridge inverter driver (without a power MOSFET)
1. Solder a 10 nF capacitor across the gate and emitter terminals of Q1 or Q2. This is to simulate actual gate capacitance
of a power MOSFET.
2. Connect a +5 V DC supply (DC supply 1) across the +5V and GND terminals of CON1.
3. Connect another DC supply (DC Supply 2 with voltage range from 12 V ~ 20 V) across VCC2 (pin 7 of IC2) and VEE (pin
5 of IC2) terminals of IC2a, respectively. This can be non-isolated for testing purposes.
4. Connect drive signals:
a. A 10 kHz 5 V DC pulse (at slightly < 50% duty) from a dual-output signal generator across IN1+ and IN1- pins of
CON1a to simulate microcontroller output to drive the lower arm of the half-bridge Inverter.
b. Another 10 kHz 5V DC pulse (at 180°out of phase to the signal in 4a) from the dual-output signal generator across
IN2+ and IN2- pins of CON1b to simulate microcontroller output to drive the upper arm of the half-bridge inverter.
5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:
a. LED signal at the IN1+ pin with reference to (w.r.t.) GND.
b. LED signal at the IN2+ pin w.r.t. GND.
Note: The VCC2b supply of voltage close to VCC2a should then be successfully generated through the built-in bootstrap
components D3b and R6.
c. VGa representing the output voltage of ACPL-P346/W346 (IC1a) at the gate pin of Q1a (or Q2a) w.r.t. VEa.
d. VGb (through an isolated probe) representing the output voltage of ACPL-P346/W346 (IC1b) at the gate pin of Q1b
(or Q2b) w.r.t. VEB.
10nF
In1+
In1-
Signal Input
+5V
Gnd DC Supply 1
12~20 V
+-
10nF
VCC2b
+-
In2+
In2-
Signal Input
5a
5b
5c
5d
VEa
VEb
DC Supply 2
1
2
4a
3
1
4b
Figure 2. Simple Simulation Test Setup of Evaluation Board

3
Schematics
Figure 3 shows the schematics of the evaluation board:
NM
1ACPL-P346
NM
NM
NM
NM
VCC2b
VEEb
34
5
6
1
VCC2a
VEEa
34
5
6
249R
130R
249R
130R
4R7 1W
4R7 1W
LEDa+
LEDa-
VCC1a
GNDa
LEDb+
LEDb-
VCC1b
GNDb
0.1 µF
0.1µF
SS32
SS32
BYM26F
10 µF Ta
R05P212D/R8
1
25
6
7
1
25
6
7
10µF Ta
10µF Ta
TP2b
TP3b
TP4b
TP1b
TP2a
TP3a
TP4a
TP1a
S1a
S2a
S1b
S2b
CON1a
CON1b
IC1a
IC1b
IC2a
IC2b
R1a
R2a
R3a
R4a
R5a
R6
C1a
C2a
C3a
D1a D2a
R1b
R2b
R3b
R4b
R5b
C1b
C2b
C3b
D1b D2b
D3b
VEa
VEb
BYM26F
D3a
10 µF Ta
D4b
R7b
NM
NM
D4a
R7a
NM
NM
NM
TO220/TO247
G
D
SQ1b/Q2b
NM
TO220/TO247
G
D
SQ1a/Q2a
S3b
S3a
ACPL-P346
VCC2b
VEEb
VCC2a
VEEa
4R7 1W
SMBJ11CA
SMBJ11CA
Figure 3. Schematics of ACPL-P346/W346 evaluation board

4
Practical connections of the evaluation board using a power MOSFET for an actual inverter test
1. Solder actual power MOSFETs at Q1 (or Q2) for the top and bottom arms of the half-bridge inverter isolated drivers.
2. Connect a +5V DC isolated supply1 across +5V and GND terminals of CON1 for both arms of the isolated drivers.
3. Connect another isolated DC supply2 (voltage range from 12 V ~ 20 V) across VCC2a and VEEa at pin 7 and pin 5 of IC2a
respectively for the bottom arm.
4. Connect the signal output (meant to drive the bottom arm of the half-bridge inverter) from the microcontroller to
Signal Input 1 across pin IN1+ and IN1- of CON1a of the bottom inverter arm isolated driver.
5. Connect the signal output (meant to drive the top arm of the half-bridge inverter) from the microcontroller to Signal
Input 2 across pin IN2+ and IN2- of CON1b of the top inverter arm isolated driver. Note: Signal Input 2 should be
180°out of phase w.r.t. Signal Input 1. Check that VCC2b (voltage close to VCC2a) is generated through the bootstrap
components D3b and R6.
6. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:
a. LED signal at IN1+ pin w.r.t. GND for the bottom arm.
b. LED signal at IN2+ pin w.r.t. GND for the top arm.
c. Vga for the gate driving voltage of Q1a (or Q2a) w.r.t. VEa of the bottom inverter arm (dierential probe needed).
d. Vgb for the gate driving voltage of Q1b (or Q2b) w.r.t. VEb of the top inverter arm (dierential probe needed).
7. Connect a power cable from the output pin (marked Load) to the inverter load.
8. Connect the high voltage cables from the top arm power MOSFET drain pin to HVDC+ and from the bottom arm
power MOSFET source pin to HVDC-, respectively, as shown. (Note: It is recommended that you enable the current-
limiting function of the HV power source supplying the high voltage DC bus voltage during this test to protect the
inverter and its driver circuitries).
Microcontroller
IN1+
IN1- Signal Input 1
+5V
GND DC Supply1
IN2+
IN2- Signal Input 2
Power MOSFET
mounted
1
1
2
3
12~20 V
+
DC Supply2
4
5
12~20V
+
5
6a
6b
6c
6d
Load
7
HVDC+
HVDC–
8
8
–
–
Power MOSFET
mounted
Figure 4. Connection of evaluation board in actual applications

5
Application Circuit Description
The ACPL-P346/ACPL-W346 is an isolated gate driver that provides 2.5 A output current. The voltage and high peak
output current supplied by this optocoupler make it ideally suited for direct driving of MOSFET with ratings up to 1000
V/100 W. It is also designed to drive dierent sizes of buer stage that will make the class of power MOSFET scalable.
ACPL-P346 (and ACPL-W346) provides a single isolation solution suitable for both low and high power ratings of motor
control and inverter applications.
Each of the ACPL-P346/ACPL-W346 evaluation boards, as shown in Figure 5, accommodates two ACPL-P346/ACPL-W346
ICs. Therefore, each board is enough to drive the top and the bottom arms of the half-bridge inverter. It allows the de-
signer to easily test the performance of a gate driver in an actual application under real-life operating conditions. Opera-
tion of the evaluation board requires merely the inclusion of a common 5 V DC isolated Supply1 on the input side and
an isolated DC Supply2 (range from 12 V ~ 20 V) for the bottom arm of the inverter power MOSFET, while the DC supply
needed for the top arm is easily generated through bootstrapping included in the evaluation board.
Note: As can be seen on the board, the isolation circuitry (at the far left) is easily contained within a small area while
maintaining adequate spacing for good voltage isolation and easy assembly.
Figure 5. Top and bottom views of ACPL-P346/W346 evaluation board

6
Using the Board
It is easy to prepare the evaluation board for use. You just need to solder cables for DC supplies, have proper cables for
HVDC+/HVDC- high voltage bus, and load connections. The evaluation board has a default connection as shown in
Table 1 when it is shipped to the customer. We oer several power supply schemes from which you can choose.
Power Supply Schemes
The evaluation board is built with DC supply exibility in mind; choose a power supply scheme from the seven available.
Table 1 shows all the possible power supply schemes that work for the evaluation board. A description of each scheme
is given; you are encouraged to explore each scheme and decide which one works best for your needs:
1. Scheme 1 is the simplest and possibly the cheapest scheme. A +5 V isolated DC supply is supplied externally to
power the low voltage Vcc1 circuit. Another external supply (+12 V~20 V for Vcc2a) is needed for the gate driver driving
the power MOSFET at the bottom inverter arm. Vcc2b supply is obtained from Vcc2a by bootstrapping. For this to
work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative
supply of Vee is allowed, and the Signal Input 2 is at 180°out of phase to Signal Input 1. All S2 jumpers are shorted to
connect Vee to Veso that there are no negative supplies. S3 jumpers are shorted by default but this has no eect on
actual operation of the board. Contact Avago Technologies if bootstrapping operation works are required.
2. Scheme 2 is similar to Scheme 1: it has Vcc1 and Vcc2a supplies. However, as the power MOSFET used gets bigger,
so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not
suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nC). A third external supply (+12 V~ 20
V for Vcc2b) will be needed.
3. Scheme 3 is similar to Scheme 2 in that it uses three external supplies at Vcc1, Vcc2a and Vcc2b. Scheme 3, however, has
the advantage of getting negative supplies for Vee (or Veea and Veeb) by introducing a 12 V Zener diode at D4 and R7
of around 1 kΩto provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be
open while the external supplies (+15 V ~ 24 V) on the high voltage driver side are to be connected acrossVcc2 and Vee
pins only, not the Vepin. As the external supply changes from +15 V to +24 V, Vcc2 will stay at +12V, but Vee changes
from -3 V to -12 V, all w.r.t. virtual ground at Ve.
4. Scheme 4 is another simple scheme; an alternative to Scheme 1. Here, only one external supply for Vcc1 is needed.
Vcc2a is obtained by a lower power DC/DC converter at IC2a, with Vcc1 as Vin and +12 V output at Vcc2a w.r.t. Vea. Vcc2b
supply is obtained from Vcc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be
connected, all S2 jumpers must be shorted so that no negative supply of Vee is allowed, and the Signal Input 2 should
be 180°out of phase to Signal input 1. S2 is shorted to connect Vee to Veso that there is no negative supply. S3
jumpers are shorted by default but this has no eect on actual operation of the board.
5. Scheme 5 is similar to Scheme 4: it has Vcc1 and a DC/DC converter for Vcc2a. However, as the power MOSFET used
gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power,
it is not suitable for use when Qg of power MOSFET rises above 200 nanocoulombs (nC). A second DC/DC converter at
IC2b with Vcc1 as Vin and +12 V output at Vcc2b w.r.t .Veb. All S2 jumpers are shorted to connect Vee to Veso that there
are no negative supplies. S3 jumpers are shorted by default but this has no eect on actual operation of the board.
6. Scheme 6 is similar to Scheme 5 with the use of Vcc1 and two DC/DC converters. Each DC/DC converter, however, has
dual outputs set at ±12 V to allow for the availability of negative Vee (at Veea and Veeb). Therefore, all S2 jumpers must
be open, while all S3 jumpers must be shorted.
7. Use Scheme 7 if dual-output ±12 V DC/DC converters are not available or dual-output ±9 V DC/DC converters are
preferred. 12 V Vcc2 can still be obtained using ±9 V DC/DC converters by introducing a 12V Zener diode at D4 and R7
of around 1kΩto provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be
open. As the total voltage across Vcc2 w.r.t. Vee stays at 18V (=9V+9V), Vcc2 of 12 V will be obtained through the 12 V
D4 Zener diode, and -6V at Vee, all w.r.t. virtual ground at Ve.

7
Table 1. Power Supply Schemes
Vcc1 Vcc2a Veea S2a S3a
D4a/
R7a Vcc2b Veeb S2b S3b
D4b/
R7b Remarks
1+5 V
External
+12V~20V
External
0 V s/c s/c NM Bootstrapped
from Vcc2a
(+12V~20V)
0 V s/c s/c NM Default (simplest)
- Two external supplies needed
for Vcc1 and Vcc2a
2+5 V
External
+12V~20V
External
0 V s/c s/c NM +12V~20V
External
0 V s/c s/c NM Higher Power
- Three external supplies needed
for Vcc1, Vcc2a and Vcc2b
3+5 V
External
+15V~24V External open open 12V/
1k
+15V~24V External open open 12V/1k Vee available
- Three external supplies needed
for Vcc1, Vcc2a and Vcc2b
- Virtual gnds Vea and Veb
generated through D4 and R7
12V -3V~-12V 12V -3V~-12V
4+5 V
External
DC/DC
(=Vcc1/+12V)
0 V s/c s/c NM Bootstrapped
from Vcc2a
(+12V)
0 V s/c s/c NM Cheap
- One single output DC/DC
converter for Vcc2a
- Only one external supply is
needed (Vcc1)
5+5 V
External
DC/DC
(=Vcc1/+12V)
0V s/c s/c NM DC/DC
(=Vcc1/+12V)
0 V s/c s/c NM Higher Power
- Two single output DC/DC
converters for Vcc2a and Vcc2b
- Only one external supply is
needed (Vcc1)
6+5 V
External
DC/±DC (=Vcc1/±12V) open s/c NM DC/±DC (=Vcc1/±12V) open s/c NM Vee available
- Two dual output DC/DC
converters for Vcc2a,Vcc2b, Veea
and Veeb
- Only one external supply is
needed (Vcc1)
+12V -12V +12V -12V
7+5 V
External
DC/±DC (=Vcc1/±9V) open open 12V/
1k
DC/±DC (=Vcc1/±9V) open open 12V/1k Vee available
- Dual output DC/DC converters
for Vcc2a and Vcc2b
- only 1 external supply is
needed (Vcc1)
- Virtual gnds Vea and Veb
generated through D4 and R7
+12V -6V +12V -6V
Note: As TVS D2 voltage is selected at a breakdown voltage of 12.2 V, it is not advised to set both Vcc2 and Vee voltage at a voltage beyond ±12 V.
To use a voltage higher than 12 V, please replace D2 with a bigger clamping voltage.

8
Figure 7. Turn-o and Turn-on Gate waveforms of Q1a and Q1b
Figure 6. Input LED signal and Power MOSFET Gate Voltage Waveforms
Figure 6 also shows that, once a bootstrap supply is adopted, the amplitude of the output voltage at the top inverter arm
will be slightly smaller than that of the bottom inverter arm, at 180°out of phase. (IN1+ is set at 49% duty ratio, while
IN2+ (not shown) is also set with 49% duty ratio, plus a turn-on delay of 100 ns with respect to IN1+).
Figure 7 shows the turn-o signal of IN1+, the turn-o signal at gate of Q1a, and the turn-on signal at gate of Q1b.
Output Measurement
A sample of input LED and various output waveforms are captured and shown in Figure 6. The default setup connection
is adopted, except with Q1a and Q1b power MOSFETs are mounted. The power MOSFETs used have a gate capacitance
equivalent to 10 nF.

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Avago, Avago Technologies, and the A logo are trademarks of AvagoTechnologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 AvagoTechnologies. All rights reserved.
AV02-4051EN - May 2, 2013
As can be seen from Figure 7 and Figure 8, the turn-o speed of the power MOSFET will be slow, due to the capacitive
eects of D2 and the gate capacitance of Q1. To improve the turn-o speed, the board is provided with a diode resis-
tor pair footprints at D1 and R5 (not mounted NM) to increase the gate current during turn-o. Another way to further
improve the turn-on and turn-o speed is by reducing the gate resistance of R4, but make sure the gate drive current is
not more than 2.5 A.
Figure 8 shows the turn-on signal of IN1+, the turn-on signal at gate of Q1a and the turn-o signal at gate of Q1b.
Figure 8. Turn-on and Turn-o Gate waveforms of Q1a and Q1b