Bluetrum Technology AB53 Series User manual

Bluetrum Technology
AB53XX
Audio Player Microcontroller User Manual
Versions: 0.0.7
2018/09/27
Declaration
Copyright © 2018, www. bluetrum.com.
All Rights Reserved. No Unauthorized Distribution.
Bluetrum reserves the right to make changes without further notice to any products herein
to improve reliability, function or design.
For further information on the technology, product and business term, please contact
Bluetrum Company.
For sales or technical support, please send email to the address:
Sales: [e-mail]
Technical: [e-mail]
Bluetooth Speaker
ARG-SP-3016BK

Bluetrum Technology
Appendix I Revision History
Date
Version
Comments
Revised by
2018-07-03
0.0.1
First draft
Leo
2018-07-12
0.0.2
Add PWM
Hugo
2018-08-13
0.0.3
Add RTC
Hugo
2018-08-24
0.0.5
Add QDID
Hugo
2018-09-11
0.0.6
Update uart0baud description
Leo
2018-09-27
0.0.7
Remove package
Leo

Table of content 3
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3
Table of Contents
TABLE OF CONTENTS............................................................................................................................................. 3
1PRODUCT OVERVIEW.................................................................................................................................... 5
1.1 INTRODUCE..........................................................................................................................................................5
1.2 FEATURES ............................................................................................................................................................6
2INTERRUPTS ................................................................................................................................................. 7
2.1 INTERRUPTS SPECIAL REGISTERS...............................................................................................................................8
3GPIO MANAGEMENT .................................................................................................................................. 10
3.1 FEATURES ..........................................................................................................................................................10
3.2 GPIO GENERAL CONTROL REGISTER ........................................................................................................................10
3.3 GPIO FUNCTION MAPPING ...................................................................................................................................11
3.4 EXTERNAL PORT INTERRUPT WAKE UP .....................................................................................................................13
4TIMER......................................................................................................................................................... 15
4.1 FEATURES ..........................................................................................................................................................15
4.2 TIMER0/1/2 SPECIAL FUNCTION REGISTERS ............................................................................................................15
4.3 TIMER3/4/5 SPECIAL FUNCTION REGISTERS ............................................................................................................16
5PWM .......................................................................................................................................................... 18
5.1 FEATURES ..........................................................................................................................................................18
5.2 SPECIAL FUNCTION REGISTERS...............................................................................................................................18
6RTC ............................................................................................................................................................. 20
6.1 FEATURES ..........................................................................................................................................................20
6.2 SPECIAL FUNCTION REGISTERS...............................................................................................................................20
6.3 INDEPENDENT POWER RTC REGISTERS....................................................................................................................21
7UART0 ........................................................................................................................................................ 25
7.1 FEATURES ..........................................................................................................................................................25
7.2 UART0 SPECIAL FUNCTION REGISTERS ...................................................................................................................25
7.3 USER GUIDE ......................................................................................................................................................26
8SPI1 ............................................................................................................................................................ 27
8.1 FEATURES ..........................................................................................................................................................27
8.2 SPI1 SPECIAL FUNCTION REGISTERS .......................................................................................................................27
8.3 USER GUIDE ......................................................................................................................................................29
9CHARACTERISTICS....................................................................................................................................... 31
9.1 PMU PARAMETERS.............................................................................................................................................31

Table of content 4
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9.2 IO PARAMETERS .................................................................................................................................................31
9.3 AUDIO DAC PARAMETERS ....................................................................................................................................32
9.4 AUDIO ADC PARAMETERS ....................................................................................................................................32
9.5 BT PARAMETERS.................................................................................................................................................32
9.6 CURRENT PARAMETERS ........................................................................................................................................33

1Product Overview 5
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5
1Product Overview
1.1Introduce
AB53XX is a 32 bits RISC microcontroller. It integrates advanced digital and analog peripherals to audio player
applications.
PMU(Charger
/Buck)
CPU
Memory
Bluetooth
ADC DAC/PA
SPDIF RX
IIS
FM RX FM TX
SD/MMC
USB2.0
IR
KEY
SPI UARTGPIO/PWM
LED
PA
CODEC
Other Application
DSP ENGINE

1Product Overview 6
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6
1.2Features
CPU and Flexible IO
32bit High performance CPU with DSP
instruction
Flexible GPIO pins with Programmable pull-up and
pull-down resistors;
Support GPIO wakeup or interrupt;
Bluetooth Radio
Compliant to Bluetooth 5.0 and BLE
specification (QDID: 115952);
TX output power +2db in typical;
RX Sensitivity with -90.5dBm @Basic Rate;
FM Tuner
Support frequency band 76~108MHz;
Auto search tuning;
Programable de-emphasis(50/75uS);
Receive signal strength indicator (RSSI);
Audio Interface
Audio codec with 16bit stereo DAC and two
channel 16bit ADC;
Support flexible audio EQ adjust;
Support Sample rate 8, 11.025, 12, 16, 22.05, 32,
44.1 and 48KHz;
4 channel Stereo Analog MUX;
Two channel MIC amplifier input;
High performance Stereo audio ADC with 90dB
SNR;
High performance Stereo audio DAC with 95dB
SNR, with headphone amplifier output;
Peripheral and Interfaces
Three 32-bit timers;
Three multi-function 32-bit timers, support
Capture and PWM mode;
WatchDog;
Three full-duplex UART;
Two SPI;
IR controller;
SD Card Host controller;
SPDIF receiver;
Audio interface IIS;
Full speed USB 2.0 HOST/DEVICE controller;
Sixteen Channels 10-bit SARADC;
Integrate IRTC;
Build in PMU, such as charger/buck/LDO;
Package
LQFP48;
SSOP28L;
SSOP24L;
TSSOP24;
TSSOP20;
SOP16;
Temperature
Operating temperature: -40℃to +85℃;
Storage temperature: -65℃to +150℃;

2Interrupts 7
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7
2Interrupts
Support vectorized interrupts, exceptions on illegal instructions and exceptions on load and store instructions
to invalid addresses.
Exception vectors
Interrupt
number
Address
Description
0
0x00
Reset
1
0x10
2
0x20
3
0x30
4
0x40
Low priority interrupt
5
0x50
6
0x60
7
0x70
8
0x80~0x280
High priority interrupt(see the following table)
High priority interrupt vectors
Interrupt
number
Address
Description
0
0x80
1
0x90
2
0xa0
Software interrupt
3
0xb0
Timer0 interrupt
4
0xc0
Timer1 interrupt
5
0xd0
Timer2 interrupt
Timer4 interrupt
Timer5 interrupt
6
0xe0
Timer3 interrupt
IR receiver interrupt
7
0xf0
8
0x100
9
0x110
10
0x120
11
0x130
12
0x140
13
0x150
14
0x160
UART0 interrupt
UART1 interrupt
UART2 interrupt
15
0x170
16
0x180
17
0x190
18
0x1a0
Port interrupt
19
0x1b0
20
0x1c0
21
0x1d0
22
0x1e0
23
0x1f0
24
0x200
25
0x210
26
0x220
27
0x230
28
0x240
29
0x250

2Interrupts 8
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8
Interrupt
number
Address
Description
30
0x260
31
0x270
2.1Interrupts Special Registers
Register 2-1PICCON: Peripheral interrupt control Register
Bit
Name
Mode
Default
Description
31:17
-
-
-
Unused
16
GIEM
WR
1
Global interrupt enable mask bit
0: disable interrupt
1: enable interrupt
15:8
-
-
-
Unused
7:3
-
-
-
Unused
2
HPINTEN
WR
0
High priority interrupt enable bit
0: disable
1: enable
1
LPINTEN
WR
0
Low priority interrupt enable bit
0: disable
1: enable
0
GIE
WR
0
Global interrupt enable bit
0: disable interrupt
1: enable interrupt
Register 2-2PICCONSET: Peripheral interrupt control set Register
Bit
Name
Mode
Default
Description
31:17
-
-
-
Unused
16
GIEM
W
0
Write 1 enable Global interrupt enable mask
15:8
-
-
-
Unused
7:3
-
-
-
Unused
2
HPINTEN
W
0
Write 1 enable High priority interrupt
1
LPINTEN
W
0
Write 1 enable Low priority interrupt
0
GIE
W
0
Write 1 enable Global interrupt
Register 2-3PICCONCLR: Peripheral interrupt control clear Register
Bit
Name
Mode
Default
Description
31:17
-
-
-
Unused
16
GIEMDIS
W
0
Write 1 disable Global interrupt enable mask
15:8
-
-
-
Unused
7:3
-
-
-
Unused
2
HPINTDIS
W
0
Write 1 disable High priority interrupt
1
LPINTDIS
W
0
Write 1 disable Low priority interrupt
0
GIEDIS
W
0
Write 1 disable Global interrupt
Register 2-4PICEN: Peripheral interrupt enable Register
Bit
Name
Mode
Default
Description
31:0
IntEN
WR
0x0
Interrupt 31 to 0 enable bit
0: disable
1: enable
Register 2-5PICENSET: Peripheral interrupt enable set Register
Bit
Name
Mode
Default
Description
31:0
IntEN
W
0x0
Write 1 enable Interrupt 31 to 0
Register 2-6PICENCLR: Peripheral interrupt enable clear Register

0 9
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9
Bit
Name
Mode
Default
Description
31:0
IntDIS
W
0x0
Write 1 disable Interrupt 31 to 0
Register 2-7PICPR: Peripheral high priority interrupt selection Register
Bit
Name
Mode
Default
Description
31:0
IntPR
WR
0x0
Interrupt 31 to 0 priority selection bit
0: low priority interrupt
1: high priority interrupt
Register 2-8PICADR: Peripheral interrupt address Register
Bit
Name
Mode
Default
Description
31:10
BADR
WR
0x40
Interrupt entry address
9:0
-
-
0x0
Register 2-9PICPND: Peripheral interrupt pending Register
Bit
Name
Mode
Default
Description
31:3
IntPND[31:4]
R
0x0
Interrupt 31 to 4 pending bit
0: no interrupt pending
1: interrupt pending
2
SWIPND
WR
0
Software interrupt pending. Write 1 will clear software interrupt pending
1:0
IntPND[2:0]
R
0x0
Interrupt 2 to 0 pending bit
0: no interrupt pending
1: interrupt pending

3GPIO Management 10
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10
3GPIO Management
3.1Features
1. Control GPIO input/output direction by using direction register;
2. Internal pull-up/pull-down resistor by using pull-up/pull-down resistor control register;
3. Select suitable output driving current capability;
3.2GPIO general control register
Register 3-1GPIOA: Port A data Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOA
WR
0x00
PAx data. Valid when PAx is used as GPIO
0: PAx is input low state when read and output low at PAx when write;
1:PAx is input high state when read and output high at PAx when write
Register 3-2GPIOASET: Port A Set output data Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOASET
WO
X
Set Pax output data. Write 1 set output data. Write 0 affect nothing.
Register 3-3GPIOACLR: Port A clear output data Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOACLR
WO
X
Clear Pax output data. Write 1 clear output data. Write 0 affect nothing.
Register 3-4GPIOADIR: Port A direction Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOADIR
WR
0xFF
PAx direction control
0: Output
1: Input
Register 3-5GPIOAPU: Port A pull-up Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPU
WR
0x0
PAx 10KΩpull-up resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-6GPIOAPD: Port A pull-down resister Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPD
WR
0x0
PAx 10KΩpull-down resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-7GPIOAPU200K: Port A pull-up resister Register

3GPIO Management 11
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11
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPU
WR
0x0
PAx 200KΩpull-up resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-8GPIOAPD200K: Port A pull-down resister Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPD
WR
0x0
PAx 200KΩpull-down resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-9GPIOAPU300: Port A pull-up resister Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPU
WR
0x0
PAx 300Ωpull-up resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-10GPIOAPD300: Port A pull-down resister Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAPD
WR
0x0
PAx 300Ωpull-down resister control. Valid when PAx is used as input
0: disable
1: enable
Register 3-11GPIOADE: Port A digital function enable register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOADE
WR
0xFF
PAx digital function enable
0: Port used as analog IO
1: Port used as digital IO
Register 3-12GPIOAFEN: Port A function mapping enable register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOAFEN
WR
0xFF
PAx function mapping enable
0: Port used as GPIO
1: Port used as function IO
Register 3-13GPIOADRV: Port A output driving select Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
7:0
GPIOADRV
WR
0x0
PAx output driving select
0: 8mA
1: 32mA
3.3GPIO function mapping
Register 3-14FUNCMCON0: Port function mapping control Register 0
Bit
Name
Mode
Default
Description
31:28
UT1RXMAP
WR
0x0
UART1 RX mapping
0000: no affect
0001: map to G1
0010: map to G2

3GPIO Management 12
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12
Bit
Name
Mode
Default
Description
0011: map to TX pin by UT1TXMAP select
1111: Clear these bits
Others is reserved
27:24
UT1TXMAP
WR
0x0
UART1 TX mapping
0000: no affect
0001: map to G1
0010: map to G2
1111: Clear these bits
Others is reserved
23:20
19:16
15:12
UT0RXMAP
WR
0x0
UART0 RX mapping
0000: no affect
0001: map to G1
0010: map to G2
0011: map to G3
0100: map to G4
0101: map to G5
0110: map to G6
0111: map to TX pin by UT0TXMAP select
1111: Clear these bits
Others is reserved
11:8
UT0TXMAP
WR
0x0
UART0 TX mapping
0000: no affect
0001: map to G1
0010: map to G2
0011: map to G3
0100: map to G4
0101: map to G5
0110: map to G6
0111: map to G7
1111: Clear these bits
Others is reserved
7:4
SPI0MAP
WR
0x0
SPI0 mapping
0000: no affect
0001: map to G1
0010: map to G2
0011: map to G3
1111: Clear these bits
Others is reserved
3:0
SD0MAP
WR
0x0
SD0 mapping
0000: no affect
0001: map to G1
0010: map to G2
0011: map to G3
0100: map to G4
0101: map to G5
0110: map to G6
1111: Clear these bits
Others is reserved
Register 3-15FUNCMCON1: Port function mapping control Register 1
Bit
Name
Mode
Default
Description
31:28
27:24
23:20
19:16
15:12
11:8
UT2RXMAP
WR
0x0
UART2 RX mapping
0000: no affect

3GPIO Management 13
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13
Bit
Name
Mode
Default
Description
0001: map to G1
0010: map to G2
0011: map to TX pin by UT2TXMAP select
1111: Clear these bits
Others is reserved
7:4
UT2TXMAP
WR
0x0
UART2 TX mapping
0000: no affect
0001: map to G1
0010: map to G2
1111: Clear these bits
Others is reserved
3:0
Register 3-16FUNCMCON2: Port function mapping control Register 2
Bit
Name
Mode
Default
Description
31:24
-
-
-
Unused
23:20
19:16
TMR5MAP
WR
0x0
Timer5 PWM mapping
0000: no affect
0001: map to G1
1111: Clear these bits
Others is reserved
15:12
TMR4MAP
WR
0x0
Timer4 PWM mapping
0000: no affect
0001: map to G1
1111: Clear these bits
Others is reserved
11:8
TMR3MAP
WR
0x0
Timer3 PWM mapping
0000: no affect
0001: map to G1
1111: Clear these bits
Others is reserved
7:4
TMR3CPTMAP
WR
0x0
Timer3 capture Pin mapping
0000: no affect
0001: map to G1
0010: map to G2
0011: map to G3
0100: map to G4
0101: map to G5
0110: map to G6
0111: map to G7
1111: Clear these bits
Others is reserved
3:0
3.4External Port interrupt wake up
Support eight wakeup source input, as the following table.
Wakeup source
Wakeup circuit
PA7
Wakeup circuit 0
PB1
Wakeup circuit 1
PB2
Wakeup circuit 2
PB3
Wakeup circuit 3
PB4
Wakeup circuit 4
WKO
Wakeup circuit 5
PORT_INT_FALL
Wakeup circuit 6
PORT_INT_RISE
Wakeup circuit 7

3GPIO Management 14
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14
Register 3-17WKUPCON: Wake up control Register
Bit
Name
Mode
Default
Description
31:17
-
-
-
Unused
16
WKIE
WR
0
Wake up interrupt enable
0: disable
1: enable
15:8
-
-
-
Unused
7:0
WKEN
WR
0x0
Wake up input 7~0 enable
0: disable
1: enable
Register 3-18WKUPEDG: Wake up edge select Register
Bit
Name
Mode
Default
Description
31:24
-
-
-
Unused
23:16
WKPND
R
0x0
Wake up input 7~0 pending
0: no pending
1: wake up pending
15:8
-
-
-
Unused
7:0
WKEDG
WR
0x0
Wake up input 7~0 wakeup edge select
0: rising edge
1: falling edge
Register 3-19WKUPCPND: Wake up clear pending Register
Bit
Name
Mode
Default
Description
31:8
-
-
-
Unused
23:16
WKCPND
W
0x0
Wake up input 7~0 clear pending
0: no affect
1: clear wake up pending
15:0
-
-
-
Unused
Register 3-20PORTINTEN: Port interrupt enable Register
Bit
Name
Mode
Default
Description
31:0
PORTINTEN
WR
0x0
Port interrupt 0~31 enable bit
0: disable
1: enable
Register 3-21PORTINTEDG: Port interrupt edge select Register
Bit
Name
Mode
Default
Description
31:0
PORTINTEDG
WR
0x0
Port interrupt 0~31 edge select bit
0: rise edge
1: fall edge

4Timer 15
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15
4Timer
4.1Features
1. Timer0/1/2, only support 32bit timer function
2. Timer3/4/5, can be configured to Timer-mode, Counter-mode, Capture-mode and PWM-mode
4.2Timer0/1/2 Special Function Registers
Register 4-1TMR0CON/TMR1CON/TMR2CON: Timer0/1/2 Control Register
Bit
Name
Mode
Default
Description
31:10
-
-
-
Unused
9
TPND
WR
0
Timer overflow pending
0: not overflow
1: overflow
8
-
-
-
Unused
7
TIE
WR
0
Timer overflow interrupt enable
0: disable
1: enable
6
INCSRC
WR
0
Increase source select
0: select TMR_INC
1: select external PIN
5:4
-
-
-
Unused
3:2
INCSEL
WR
0x0
Increase clock selection
00: System Clock
01: Counter input rising
10: Counter input falling
11: Counter input edge
1
-
-
-
Unused
0
TMREN
WR
0
Timer Enable Bit
0: Disable
1: Enable
Register 4-2TMR0CPND/TMR1CPND/TMR2CPND: Timer0/1/2 clear pending Register
Bit
Name
Mode
Default
Description
31:16
-
-
-
Unused
9
TPCLR
W
0
Timer overflow pending clear bit
0: inactive
1: clear pending
8:0
-
-
-
Unused
Register 4-3TMR0CNT/TMR1CNT/TMR2CNT: Timer0/1/2 counter Register
Bit
Name
Mode
Default
Description
31:0
TMRCNT
WR
0x0
Timer counter.
TMRCNT will increase when timer is enabled. It overflows when TMRCNT =
TMRPR, TMRCNT will be clear to 0x0000 when overflow, and the interrupt
flag will be set ‘1’.
Register 4-4TMR0PR/TMR1PR/TMR2PR: Timer0/1/2 period Register
Bit
Name
Mode
Default
Description
31:0
TMRPR
WR
0xffffffff
Timer period = TMRPR + 1

4Timer 16
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16
4.3Timer3/4/5 Special Function Registers
Register 4-5TMR3CON/TMR4CON/TMR5CON: Timer3/4/5 Control Register
Bit
Name
Mode
Default
Description
31:18
-
-
-
Unused
17
CPND
WR
0
Timer capture pending
0: not capture
1: capture
16
TPND
WR
0
Timer overflow pending
0: not overflow
1: overflow
15:12
-
-
-
Unused
11
PWM2EN
WR
0
Timer pwm2 enable bit
0: disable
1: enable
10
PWM1EN
WR
0
Timer pwm1 enable bit
0: disable
1: enable
9
PWM0EN
WR
0
Timer pwm0 enable bit
0: disable
1: enable
8
CIE
WR
0
Timer capture interrupt enable
0: disable
1: enable
7
TIE
WR
0
Timer overflow interrupt enable
0: disable
1: enable
6
INCSRC
WR
0
Increase source select
0: select TMR_INC
1: select external PIN
5:4
CPTEDSEL
WR
0x0
Timer Capture edge select
00: No Capture
01:Capture PIN rising edge
10: Capture PIN falling edge
11: Capture PIN edge
3:2
INCSEL
WR
0x0
Increase clock selection
00: System Clock
01: Counter input rising
10: Counter input falling
11: Counter input edge
1
CPTEN
WR
0
Timer capture Enable Bit
0: Disable
1: Enable
0
TMREN
WR
0
Timer Enable Bit
0: Disable
1: Enable
Register 4-6TMR3CPND/TMR4CPND/TMR5CPND: Timer3/4/5 clear pending Register
Bit
Name
Mode
Default
Description
31:18
-
-
-
Unused
17
CPCLR
W
0
Capture pending clear bit
0: inactive
1: clear pending
16
TPCLR
W
0
Timer overflow pending clear bit
0: inactive
1: clear pending
15:0
-
-
-
Unused
Register 4-7TMR3CNT/TMR4CNT/TMR5CNT: Timer3/4/5 counter Register

4Timer 17
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17
Bit
Name
Mode
Default
Description
31:0
TMRCNT
WR
0x0
Timer counter.
TMRCNT will increase when timer is enabled. It overflows when TMRCNT =
TMRPR, TMRCNT will be clear to 0x0000 when overflow, and the interrupt
flag will be set ‘1’.
Register 4-8TMR3PR/TMR4PR/TMR5PR: Timer3/4/5 period Register
Bit
Name
Mode
Default
Description
31:0
TMRPR
WR
0xffffffff
Timer period = TMRPR + 1
Register 4-9TMR3CPT/TMR4CPT/TMR5CPT: Timer3/4/5 capture value Register
Bit
Name
Mode
Default
Description
31:0
TMRCPT
R
x
Timer capture value
Register 4-10TMR3DUTY0/TMR4DUTY0/TMR5DUTY0: Timer3/4/5 pwm0 duty Register
Bit
Name
Mode
Default
Description
31:16
-
-
-
Unused
15:0
TMRDUTY0
W
x
Timer pwm0 duty
PWM0 low level length is TMRDUTY0+1
PWM 0 high level length is TMRPR-TMRDUTY0+1
Register 4-11TMR3DUTY1/TMR4DUTY1/TMR5DUTY1: Timer3/4/5 pwm1 duty Register
Bit
Name
Mode
Default
Description
31:16
-
-
-
Unused
15:0
TMRDUTY1
W
x
Timer pwm1 duty
PWM1 low level length is TMRDUTY1+1
PWM1 high level length is TMRPR-TMRDUTY1+1
Register 4-12TMR3DUTY2/TMR4DUTY2/TMR5DUTY2: Timer3/4/5 pwm2 duty Register
Bit
Name
Mode
Default
Description
31:16
-
-
-
Unused
15:0
TMRDUTY2
W
x
Timer pwm2 duty
PWM2 low level length is TMRDUTY2+1
PWM2 high level length is TMRPR-TMRDUTY2+1

5PWM 18
Copyright © 2018, www. bluetrum.com. All Rights Reserved
18
5PWM
5.1Features
Four channel PWM for Breathing-lamp
5.2Special Function Registers
Register 5-1 PWMCON: PMW Configure Register
Bit
Name
Mode
Default
Description
31:5
5
PWMIVN
WR
0
PWM invert enable
0: duty is high level 1: duty is low level
4
AUTOADJUST
WR
0
PWM Auto Adjust enable
0: disable 1: enable
3
PWM3EN
WR
0
PWM3 enable
0: disable 1: enable
2
PWM2EN
WR
0
PWM2 enable
0: disable 1: enable
1
PWM1EN
WR
0
PWM1 enable
0: disable 1: enable
0
PWM0EN
WR
0
PWM0 enable
0: disable 1: enable
Register 5-2 PWMPR: PMW period Register
Bit
Name
Mode
Default
Description
31:16
15:0
PWMPR
WR
0xffff
PWM period = (PWMPR+1) * Tpwmclk
Register 5-3 PWM01DUT: PWM0/1 duty registers
Bit
Name
Mode
Default
Description
31:16
PWM1DUT
WR
0x0
PWM1 duty register ; Duty = PWM1DUT/ PWMPR
15:0
PWM0DUT
WR
0x0
PWM0 duty register ; Duty = PWM0DUT/ PWMPR
Register 5-4 PWM23DUT: PWM2/3 duty registers
Bit
Name
Mode
Default
Description
31:16
PWM3DUT
WR
0x0
PWM3 duty register ; Duty = PWM3DUT/ PWMPR
15:0
PWM2DUT
WR
0x0
PWM2 duty register ; Duty = PWM2DUT/ PWMPR
Register 5-5 PWMCYCNUM: PWM adjust cycle number register
Bit
Name
Mode
Default
Description
31:24
PWM3CYCNUM
WR
0x0
PWM3 Duty adjust cycle num
When AUTOADJUST = 1, each PWM3CYCNUM Duty add
(PWM3STEP/ PWMPR)
23:16
PWM2CYCNUM
WR
0x0
PWM2 Duty adjust cycle num
When AUTOADJUST = 1, each PWM2CYCNUM Duty add
(PWM2STEP/ PWMPR)
15:8
PWM1CYCNUM
WR
0x0
PWM1 Duty adjust cycle num
When AUTOADJUST = 1, each PWM1CYCNUM Duty add
(PWM1STEP/ PWMPR)
7:0
PWM0CYCNUM
WR
0x0
PWM0 Duty adjust cycle num
When AUTOADJUST = 1, each PWM0CYCNUM Duty add

5PWM 19
Copyright © 2018, www. bluetrum.com. All Rights Reserved
19
Bit
Name
Mode
Default
Description
(PWM0STEP/ PWMPR)
Register 5-6 PWMSTEP: PWM Step register
Bit
Name
Mode
Default
Description
31:24
PWM3STEP
WR
0x0
PWM3 Duty adjust step
23:16
PWM2STEP
WR
0x0
PWM2 Duty adjust step
15:8
PWM1STEP
WR
0x0
PWM1 Duty adjust step
7:0
PWM0STEP
WR
0x0
PWM0 Duty adjust step

6RTC 20
Copyright © 2018, www. bluetrum.com. All Rights Reserved
20
6RTC
6.1Features
1. Support 32bit Independent power supply real time counter
2. Support alarm interrupt and second interrupt
6.2Special Function Registers
Register 6-1RTCCON: RTC Control Register
Bit
Name
Mode
Default
Description
31:13
-
-
-
Unused
20
VUSBONLINE
R
0
VUSB online state
0: not online
1: online
19
RTCWKP
R
0
RTC WK pin state
0: WK pin state is 0
1: WK pin state is 1
18
RTC1SPND
R
0
RTC 1s pending
0: no pending
1: 1s pending
17
ALMPND
R
0
RTC alarm pending
0: no pending
1: alarm pending
16
RTCPND
R
0
RTC trans done
0: done
1:not done
15:9
-
-
-
Unused
8
ALM_WKEN
WR
0
RTC alarm wakeup enable
0: disable
1: enable
7
RTC1S_WKEN
WR
0
RTC 1S wakeup enable
0: disable
1: enable
6
VUSBRSTEN
WR
0
VUSB insert reset system enable
0: disable
1: enable
5
WKUPRSTEN
WR
0
RTC wake up power down mode reset system enable
0: disable
1: enable
4
ALMIE
WR
0
RTC alarm interrupt enable
0: disable
1: enable
3
RTC1SIE
WR
0
RTC 1S interrupt enable
0: disable
1: enable
2:1
BAUDSEL
WR
0x0
Increase clock selection
00: System Clock divide 4
01: System Clock divide 8
10: System Clock divide 16
11: System Clock divide 32
0
RTCCS
WR
0
RTC cs
0:disabled