ST ST7260 Series User manual

Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution
of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business
relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components
to meet their specific needs.
With the principle of “Quality Parts,Customers Priority,Honest Operation,and Considerate Service”,our business
mainly focus on the distribution of electronic components. Line cards we deal with include
Microchip,ALPS,ROHM,Xilinx,Pulse,ON,Everlight and Freescale. Main products comprise
IC,Modules,Potentiometer,IC Socket,Relay,Connector.Our parts cover such applications as commercial,industrial,
and automotives areas.
We are looking forward to setting up business relationship with you and hope to provide you with the best service
and solution. Let us make a better world for our industry!
Contact us
Tel: [phone] Fax: [phone]
Email & Skype: [email protected]om Web: www.chipsmall.com
Address: A1208, Overseas Decoration Building, #122 Zhenhua RD., Futian, Shenzhen, China
  

February 2009 Rev 3 1/139
139
ST7260xx
Low speed USB 8-bit MCU family with up to 8K Flash
and serial communications interface
Features
■Memories
– 4 or 8 Kbytes program memory: high
density Flash (HDFlash), or FastROM with
readout and write protection
– In-application programming (IAP) and in-
circuit programming (ICP)
– 384 bytes RAM memory (128-byte stack)
■Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
– RAM Retention mode
– Optional low voltage detector (LVD)
■USB (Universal Serial Bus) interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID
specifications (version 1.0)
– Integrated 3.3 V voltage regulator and
transceivers
– Supports USB DFU class specification
– Suspend and Resume operations
– 3 Endpoints with programmable In/Out
configuration
■Up to 19 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os (25
mA at 1.5 V)
– Up to 8 lines with interrupt capability
■2 timers
– Programmable Watchdog
– 16-bit Timer with 2 Input Captures, 2
Output Compares, PWM output and clock
input
■Communications interface
– Asynchronous serial communications
interface (SCI)
■Instruction set
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■Development tools
– Versatile development tools including ,
software library, hardware emulator,
programming boards, HID and DFU
software layer
SO24 QFN40
(6x6)
Table 1. Device summary
Features ST7260K2 ST7260K1 ST7260E2 ST7260E1
Flash program memory -
bytes 8K4K8K4K
RAM (stack) - bytes 384 (128)
Peripherals Watchdog timer, 16-bit timer, USB, SCI
Operating supply 4.0 V to 5.5 V
CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating temperature 0 °C to +70 °C
Packages QFN40 (6x6) SO24
www.st.com

Contents ST7260xx
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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7.3 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.0.1 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.2.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.2.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.2.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.5 Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2.6 Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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12.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.2.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.3.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.3.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.3.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13.3.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.3.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113
16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
16.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118
16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118
16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119
16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
16.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
16.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
16.9.2 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
16.9.3 SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128
17 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
17.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
17.1.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
18 Device configuration and ordering information . . . . . . . . . . . . . . . . . 131
18.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
18.2 Device ordering information and transfer of customer code . . . . . . . . . . 132
18.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
19 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

ST7260xx Description
7/139
1 Description
The ST7260xx devices are members of the ST7 microcontroller family designed for USB
applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash program memory. The ST7 family architecture
offers both power and flexibility to software developers, enabling the design of highly
efficient and compact application code.
The on-chip peripherals include a low speed USB interface and an asynchronous SCI
interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait,
Active Halt or Halt mode when the application is in idle or stand-by state.
Typical applications include consumer, home, office and industrial products.

Block diagram ST7260xx
8/139
2 Block diagram
Figure 1. General block diagram
8-BIT CORE
ALU
ADDRESS AND DATA BUS
OSCIN
OSCOUT
RESET
PORT B
16-bit TIMER
PORT A
PORT C
PB[7:0]
(8 bits)
PC[2:0]
(3 bits)
OSCILLATOR
INTERNAL
CLOCK
CONTROL
RAM
(384 bytes)
PA[7:0]
(8 bits)
VSS
VDD POWER
SUPPLY
SCI
PROGRAM
(8 Kbytes)
MEMORY
(UART)
USB SIE
OSC/3
LVD
WATCHDOG
VSSA
VDDA
VPP/TEST
USB DMA
USBDP
USBDM
USBVCC
OSC/4 or OSC/2
for USB1)
1) 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.

ST7260xx Pin description
9/139
3 Pin description
Figure 2. 40-lead QFN package pinout
Figure 3. 24-pin SO package pinout
4
3
5
6
7
8
9
10
11 12 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
3132333437383940
2
1
3536
13 14
VDDA
VDD
OSCOUT
OSCIN
VSS
USBOE/PC2
VSSA
USBDP
USBDM
USBVCC
NC
IT8/PB7(10 mA)
IT7/PB6(10 mA)
TDO/PC1
RDI/PC0
RESET
NC
IT6/PB5(10 mA)
VPP/TEST
PA7/OCMP2/IT4
PB0(10 mA)
PB1(10 mA)
PB2(10 mA)
PB3(10 mA)
PB4(10 mA)/IT5
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
NC NC NC NC NC NC PA2(25 mA)/ICCCLK PA1(25 mA)/ICCDATA NC NC
PA0/MCO
Note: NC=Do not connect
14
13
11
12
15
16
17
18 PA2(25 mA)/ICCCLK
PA1(25 mA)/ICCDATA
PA0/MCO
VSSA
PA7/OCMP2/IT4
PA5/ICAP2/IT2
PA4/ICAP1/IT1
1
2
3
4
5
6
7
8
9
10
VDD
RDI/PC0
TDO/PC1
VSS
PA3/EXTCLK
IT7/PB6(10mA)
19
20
VPP/TEST
PB3(10 mA)
PB2(10 mA)
USBDP
RESET/
OSCOUT
USBOE/PB1(10 mA) PB0(10 mA)
OSCIN
21
22
23
24
USBDM
USBVcc

Pin description ST7260xx
10/139
RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU.
This event is the top priority non maskable interrupt. This pin is switched low when the
Watchdog is triggered or the VDD is low. It can be used to reset external peripherals.
OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant
crystal, or an external source, to the on-chip oscillator.
VDD/VSS (see Note 2): Main power supply and ground voltages.
VDDA/VSSA (see Note 2): Power supply and ground voltages for analog peripherals.
Alternate functions: Several pins of the I/O ports assume software programmable
alternate functions as shown in the pin description.
Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected
to VDD and VSS) will significantly improve product electromagnetic susceptibility
performance.
2 To enhance the reliability of operation, it is recommended that VDDA and VDD be connected
together on the application board. This also applies to VSSA and VSS.
3 The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it
is mapped on Port B1.
4 The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24
devices it is not available.
Legend / abbreviations for Figure 2, Figure 3 and Ta b l e 2 , Ta bl e 3 :
Type: I = input, O = output, S = supply
In/Output level: CT = CMOS 0.3 VDD / 0.7 VDD with input trigger
Output level: 10 mA = 10 mA high sink (Fn N-buffer only)
25 mA = 25 mA very high sink (on N-buffer only)
Port and control configuration:
●Input: float = floating, wpu = weak pull-up, int = interrupt
●Output: OD = open drain, PP = push-pull, T = True open drain
The RESET configuration of each pin is shown in bold. This configuration is kept as long as
the device is under reset state.

ST7260xx Pin description
11/139
)
Table 2. Device pin description (QFN40)
Pin n° Pin name
Type
Level Port / control Main
function
(after
reset)
Alternate function
Input
Output
Input Output
float
wpu
int
OD
PP
1 PA0/MCO I/O CT X X Port A0 Main Clock Output
2V
SSA SAnalog ground
3 USBDP I/O USB bidirectional data (data +)
4 USBDM I/O USB bidirectional data (data -)
5 USBVCC O USB power supply
6V
DDA SAnalog supply voltage
7V
DD SPower supply voltage (4V - 5.5V)
8 OSCOUT O Oscillator output
9 OSCIN I Oscillator input
10 VSS SDigital ground
11 PC2/USBOE I/O CT X X Port C2 USB Output Enable
12 PC1/TDO I/O CT X X Port C1 SCI Transmit Data
Output
13 PC0/RDI I/O CT X X Port C0 SCI Receive Data
Input
14 RESET I/O X X Reset
15 NC -- Not connected
16 NC -- Not connected
17 PB7/IT8 I/O CT 10 mA X X X Port B7
18 PB6/IT7 I/O CT 10 mA X X X Port B6
19 VPP/TEST S Programming supply
20 PB5/IT6 I/O CT 10 mA X X X Port B5
21 PB4/IT5 I/O CT 10 mA X X X Port B4
22 PB3 I/O CT 10 mA X X Port B3
23 PB2 I/O CT 10 mA X X Port B2
24 PB1 I/O CT 10 mA X X Port B1
25 PB0 I/O CT 10 mA X X Port B0
26 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer Output Compare
2
27 PA6/OCMP1/IT3 I/O CT X X X Port A6 Timer Output Compare
1
28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2
29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1

Pin description ST7260xx
12/139
30 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock
31 PA2/ICCCLK I/O CT25 mA X T Port A2 ICC Clock
32 NC -- Do not connect
33 NC -- Do not connect
34 NC -- Do not connect
35 NC -- Do not connect
36 NC -- Do not connect
37 NC -- Do not connect
38 NC -- Do not connect
39 NC -- Do not connect
40 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data
Table 2. Device pin description (QFN40) (continued)
Pin n° Pin name
Type
Level Port / control Main
function
(after
reset)
Alternate function
Input
Output
Input Output
float
wpu
int
OD
PP

ST7260xx Pin description
13/139
Table 3. Device pin description (SO24)
Pin n° Pin name
Type
Level Port / control Main
function
(after
reset)
Alternate function
Input
Output
Input Output
float
wpu
int
OD
PP
1V
DD SPower supply voltage
(4 V - 5.5 V)
2 OSCOUT O Oscillator output
3 OSCIN I Oscillator input
4V
SS SDigital ground
5 PC1/TDO I/O CT X X Port C1 SCI Transmit Data
Output
6 PC0/RDI I/O CT X X Port C0 SCI Receive Data
Input
7 RESET I/O X X Reset
8 PB6/IT7 I/O CT 10 mA X X X Port B6
9V
PP/TEST S Programming supply
10 PB3 I/O CT 10 mA X X Port B3
11 PB2 I/O CT 10 mA X X Port B2
12 PB1/USBOE I/O CT 10 mA X X Port B1 USB Output Enable
13 PB0 I/O CT 10 mA X X Port B0
14 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer Output
Compare 2
15 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture
2
16 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture
1
17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock
18 PA2/ICCCLK I/O CT25 mA X T Port A2 ICC Clock
19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data
20 PA0/MCO I/O CT X X Port A0 Main Clock Output
21 VSSA SAnalog ground
22 USBDP I/O USB bidirectional data (data +)
23 USBDM I/O USB bidirectional data (data -)
24 USBVCC O USB power supply

Register & memory map ST7260xx
14/139
4 Register & memory map
As shown in Figure 4, the MCU is capable of addressing 8 Kbytes of memories and I/O
registers.
The available memory locations consist of up to 384 bytes of RAM including 64 bytes of
register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes
are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.
The highest address bytes contain the user reset and interrupt vectors.
Note: Important: memory locations noted “Reserved” must never be accessed. Accessing a
reserved area can have unpredictable effects on the device.
Figure 4. Memory map
0000h
RAM
Program memory
(4 / 8 KBytes)
Interrupt & reset vectors
HW registers
0040h
003Fh
FFDFh
FFE0h
FFFFh
Reserved
Stack
(128 Bytes)
0100h
017Fh
01C0h
00FFh
0040h
0180h
01BFh
Short addressing
RAM (192 bytes)
16-bit addressing
RAM
8000h
7FFFh
(384 Bytes)
FFDFh
F000h
E000h 8 KBytes
4 KBytes
01BFh
(See Table 5)
(See Table 4)

ST7260xx Register & memory map
15/139
.
Table 4. Interrupt vector map
Vector address Description Masked by Remarks Exit from Halt
mode
FFE0h-FFEDh
FFEEh-FFEFh
FFF0h-FFF1h
FFF2h-FFF3h
FFF4h-FFF5h
FFF6h-FFF7h
FFF8h-FFF9h
FFFAh-FFFBh
FFFCh-FFFDh
FFFEh-FFFFh
Reserved area
USB interrupt vector
SCI interrupt vector
Reserved area
TIMER interrupt vector
IT1 to IT8 interrupt vector
USB end suspend mode interrupt vector
Flash start programming interrupt vector
TRAP (software) interrupt vector
RESET vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
None
None
Internal interrupt
Internal interrupt
Internal interrupt
External interrupt
External interrupts
Internal interrupt
CPU interrupt
No
No
No
Ye s
Ye s
Ye s
No
Ye s
Table 5. Hardware register memory map
Address Block Register label Register name Reset
status Remarks
0000h
0001h Port A PA D R
PA D D R
Port A Data Register
Port A Data Direction Register
00h
00h
R/W
R/W
0002h
0003h Port B PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
00h
00h
R/W
R/W
0004h
0005h Port C PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
1111 x000b
1111 x000b
R/W
R/W
0006h
to
0007h
Reserved (2 bytes)
0008h ITC ITIFRE Interrupt Register 00h R/W
0009h MISC MISCR Miscellaneous Register 00h R/W
000Ah
to
000Bh
Reserved (2 bytes)
000Ch WDG WDGCR Watchdog Control Register 7Fh R/W
000Dh to
0010h Reserved (4 bytes)

Register & memory map ST7260xx
16/139
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
TIM
TCR2
TCR1
TCSR
TIC1HR
TIC1LR
TOC1HR
TOC1LR
TCHR
TCLR
TACHR
TAC L R
TIC2HR
TIC2LR
TOC2HR
TOC2LR
Timer Control Register 2
Timer Control Register 1
Timer Control/Status Register
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
R/W
Read only
R/W
Read only
Read only
R/W
R/W
0020h
0021h
0022h
0023h
0024h
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
C0h
xxh
00h
x000 0000b
00h
Read only
R/W
R/W
R/W
R/W
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
USB
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
USB PID Register
USB DMA address Register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
x0h
xxh
x0h
00h
00h
06h
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0032h
0036h Reserved (5 Bytes)
0037h Flash FCSR Flash Control /Status Register 00h R/W
0038h
to
003Fh
Reserved (8 bytes)
Table 5. Hardware register memory map (continued)
Address Block Register label Register name Reset
status Remarks

ST7260xx Flash program memory
17/139
5 Flash program memory
5.1 Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
5.2 Main features
●3 Flash programming modes:
– Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
– ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
– IAP (in-application programming). In this mode, all sectors, except Sector 0, can
be programmed or erased without removing the device from the application board
and while the application is running.
●ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●Readout protection
●Register Access Security System (RASS) to prevent accidental programming or
erasing
5.3 Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (seeTa b l e 6 ). Each of these sectors can be erased independently to avoid
unnecessary erasing of the whole Flash memory when only a partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 6. Sectors available in Flash devices
Flash size (bytes) Available sectors
4K Sector 0
8K Sectors 0, 1
>8K Sectors 0, 1, 2

Flash program memory ST7260xx
18/139
5.3.1 Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased.
Readout protection is enabled and removed through the FMP_R bit in the option byte.
Figure 5. Memory map and sector address
4Kbytes
4Kbytes Sector 1
Sector 0
Sector 2
8K 16K 32K Flash
FFFFh
EFFFh
DFFFh
7FFFh
24 Kbytes
memory size
8Kbytes
BFFFh

ST7260xx Flash program memory
19/139
5.4 ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
– RESET: device reset
–V
SS: device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/VPP: programming voltage
– OSC1 (or OSCIN): main clock input for external source (optional)
–V
DD: application board power supply (see Figure 6, Note 3).
Figure 6. Typical ICC interface
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to be implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(PUSH-pull output or pull-up resistor <1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R>1K or a reset management IC with open
drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-
oscillator capability need to have OSC2 grounded in this case.
ICC connector
ICCDATA
ICCCLK
RESET
VDD
HE10 connector type
Application
power supply
1
246810
975 3
Programming tool
ICC connector
Application board
ICC cable
(See note 3)
10kΩ
VSS
ICCSEL/VPP
ST7
OSC1
OSC2
See note 1
See note 2
Application
reset source
Application
I/O
(see note 4)
Optional