Epson S1C17W15 User manual

Rev. 1.3
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17W15
Technical Manual

©
SEIKO EPSON CORPORATION 2021 , All rights reserved.
Evaluation board/kit and Development tool important notice
1. This evaluation board/kit or development tool is designed for use with engineering evaluation, demonstration, or develop-
ment purposes only. Do not use it for other purposes. It is not intended to meet the design requirements of finished products.
2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind
of damage and/or fire caused by its use. The user should cease to use it when any abnormal issue occurs even during proper
and safe use.
3. Parts used for this evaluation board/kit or development tool may be changed without any notice.
NOTICE : PLEASE READ CAREFULLY BELOW BEFORE USING THIS DOCUMENT
The contents of this document are subject to change without notice.
1. This document may not be copied, reproduced, or used for any other purpose, in whole or in part, without the consent of the
Seiko Epson Corporation (“Epson”).
2. Before purchasing or using Epson products, please contact our sales representative for the latest information and always be
sure to check the latest information published on Epson’s official web sites and other sources.
3. Information provided in this document such as application circuits, programs, usage, etc., are for reference purposes only.
Using the application circuits, programs, usage, etc. in the design of your equipment or systems is your own responsibility.
Epson makes no guarantees against any infringements or damages to any third parties’ intellectual property rights or any
other rights resulting from the information. This document does not grant you any licenses, intellectual property rights or any
other rights with respect to Epson products owned by Epson or any third parties.
4. Epson is committed to constantly improving quality and reliability, but semiconductor products in general are subject to
malfunction and failure. By using Epson products, you shall be responsible for your hardware. Software and systems must
be designed well enough to prevent death or injury as well as any property damage even if any of the malfunctions or
failures might be caused by Epson products. When designing your products using Epson products, please be sure to check
and comply with the latest information regarding Epson products (this document, specifications, data sheets, manuals,
Epson’s web site, etc.). When using the information included above materials such as product data, charts, technical contents,
programs, algorithms and application circuit examples, you shall evaluate your products both on a stand-alone basis as well
as within your overall systems. You shall be solely responsible for deciding whether or not to adopt and use Epson products.
5. Epson has prepared this document and programs provided in this document carefully to be accurate and dependable, but
Epson does not guarantee that the information and the programs are always accurate and complete. Epson assumes no
responsibility for any damages which you incur due to misinformation in this document and the programs.
6. No dismantling, analysis, reverse engineering, modification, alteration, adaptation, reproduction, etc., of Epson products is
allowed.
7. Epson products have been designed, developed and manufactured to be used in general electronic applications (office
equipment, communications equipment, measuring instruments, home electronics, etc.) and applications individually listed
in this document (“General Purpose”). Epson products are NOT intended for any use beyond the General Purpose uses that
requires particular/higher quality or reliability in order to refrain from causing any malfunction or failure leading to death,
injury, serious property damage or severe impact on society, including, but not limited to those listed below. Therefore, you
are advised to use Epson products only for General Purpose uses. Should you desire to buy and use Epson products for a
particular purpose other than a General Purpose use, Epson makes no warranty and disclaims with respect to Epson products,
whether express or implied, including without limitation any implied warranty of merchantability or fitness for any particular
purpose. Please be sure to contact our sales representative and obtain approval in advance.
【Particular purpose】
Space equipment (artificial satellites, rockets, etc.)
Transportation vehicles and their control equipment (automobiles, aircraft, trains, ships, etc.)
Medical equipment (other than applications individually listed in this document) / Relay equipment to be placed on ocean floor
Power station control equipment / Disaster or crime prevention equipment / Traffic control equipment / Financial equipment
Other applications requiring similar levels of reliability as those listed above
8. Epson products listed in this document and our associated technologies shall not be used in any equipment or systems that
laws and regulations in Japan or any other countries prohibit to manufacture, use or sell. Furthermore, Epson products and
our associated technologies shall not be used for developing weapons of mass destruction, or any other military purposes or
applications. If exporting Epson products or our associated technologies, you shall comply with the Foreign Exchange and
Foreign Trade Control Act in Japan, Export Administration Regulations in the U.S.A. (EAR) and other export-related laws
and regulations in Japan and any other countries and follow the required procedures as provided by the relevant laws and
regulations.
9. Epson assumes no responsibility for any damages (whether direct or indirect) caused by or in relation with your non-
compliance with the terms and conditions in this document.
10. Epson assumes no responsibility for any damages (whether direct or indirect) incurred by any third party that you assign,
transfer, loan, etc., Epson products to.
11. For more details or other concerns about this document, please contact our sales representative.
12. Company names and product names listed in this document are trademarks or registered trademarks of their respective
companies.
(Rev. e1.0, 2021.9)

PREFACE
S1C17W15 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.3)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17W15. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

CONTENTS
ii Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (Package)............................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip).................................................................... 1-8
1.3.3 Pin Descriptions................................................................................................ 1-9
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG2)................................................................................................ 2-1
2.1.1 Overview........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 Operations ........................................................................................................ 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-4
2.2.1 Overview........................................................................................................... 2-4
2.2.2 Input Pin............................................................................................................ 2-4
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-5
2.3 Clock Generator (CLG).................................................................................................... 2-6
2.3.1 Overview........................................................................................................... 2-6
2.3.2 Input/Output Pins ............................................................................................. 2-7
2.3.3 Clock Sources .................................................................................................. 2-7
2.3.4 Operations ........................................................................................................ 2-9
2.4 Operating Mode ............................................................................................................. 2-14
2.4.1 Initial Boot Sequence....................................................................................... 2-14
2.4.2 Transition between Operating Modes.............................................................. 2-14
2.5 Interrupts........................................................................................................................ 2-16
2.6 Control Registers ........................................................................................................... 2-16
PWG2 Control Register............................................................................................................ 2-16
PWG2 Timing Control Register ................................................................................................ 2-17
PWG2 Interrupt Flag Register .................................................................................................. 2-17
PWG2 Interrupt Enable Register .............................................................................................. 2-17
CLG System Clock Control Register........................................................................................ 2-17
CLG Oscillation Control Register ............................................................................................. 2-19
CLG IOSC Control Register ..................................................................................................... 2-19
CLG OSC1 Control Register .................................................................................................... 2-20
CLG OSC3 Control Register .................................................................................................... 2-21
CLG Interrupt Flag Register ..................................................................................................... 2-22
CLG Interrupt Enable Register ................................................................................................. 2-23
CLG FOUT Control Register..................................................................................................... 2-24
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2

CONTENTS
S1C17W15 TECHNICAL MANUAL Seiko Epson Corporation iii
(Rev. 1.3)
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-3
3.3.3 List of debugger input/output pins ................................................................... 3-3
3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-4
3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-5
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-3
4.3.3 Flash Programming........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Display Data RAM........................................................................................................... 4-3
4.6 Peripheral Circuit Control Registers................................................................................ 4-3
4.6.1 System-Protect Function.................................................................................. 4-7
4.7 Control Registers ............................................................................................................ 4-8
MISC System Protect Register ................................................................................................. 4-8
MISC IRAM Size Register.......................................................................................................... 4-8
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-2
6.2.3 Pull-Up/Pull-Down............................................................................................ 6-2
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-3

CONTENTS
iv Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
6.4 Operations ...................................................................................................................... 6-3
6.4.1 Initialization ....................................................................................................... 6-3
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6
6.6 Control Registers ............................................................................................................ 6-6
PxPort Data Register................................................................................................................ 6-6
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-7
PxPort Interrupt Flag Register.................................................................................................. 6-8
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-8
PxPort Mode Select Register ................................................................................................... 6-8
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register........................................................................................ 6-10
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-11
6.7.1 P0 Port Group.................................................................................................. 6-11
6.7.2 P1 Port Group.................................................................................................. 6-12
6.7.3 P2 Port Group.................................................................................................. 6-12
6.7.4 P3 Port Group.................................................................................................. 6-13
6.7.5 Pd Port Group.................................................................................................. 6-14
6.7.6 Common Registers between Port Groups....................................................... 6-15
7 Universal Port Multiplexer (UPMUX)...........................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Peripheral Circuit I/O Function Assignment.................................................................... 7-1
7.3 Control Registers ............................................................................................................ 7-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 7-2
8 Watchdog Timer (WDT)................................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Clock Settings................................................................................................................. 8-1
8.2.1 WDT Operating Clock....................................................................................... 8-1
8.2.2 Clock Supply in DEBUG Mode......................................................................... 8-2
8.3 Operations ...................................................................................................................... 8-2
8.3.1 WDT Control ..................................................................................................... 8-2
8.3.2 Operations in HALT and SLEEP Modes............................................................ 8-2
8.4 Control Registers ............................................................................................................ 8-3
WDT Clock Control Register ..................................................................................................... 8-3
WDT Control Register ............................................................................................................... 8-3
9 Real-Time Clock (RTCA) ..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Output Pin and External Connection .............................................................................. 9-1
9.2.1 Output Pin......................................................................................................... 9-1
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 RTCA Operating Clock ..................................................................................... 9-2
9.3.2 Theoretical Regulation Function....................................................................... 9-2
9.4 Operations ...................................................................................................................... 9-3
9.4.1 RTCA Control ................................................................................................... 9-3
9.4.2 Real-Time Clock Counter Operations............................................................... 9-4
9.4.3 Stopwatch Control............................................................................................ 9-4
9.4.4 Stopwatch Count-up Pattern ........................................................................... 9-4
9.5 Interrupts......................................................................................................................... 9-5

CONTENTS
S1C17W15 TECHNICAL MANUAL Seiko Epson Corporation v
(Rev. 1.3)
9.6 Control Registers ............................................................................................................ 9-6
RTC Control Register ................................................................................................................ 9-6
RTC Second Alarm Register ..................................................................................................... 9-7
RTC Hour/Minute Alarm Register.............................................................................................. 9-8
RTC Stopwatch Control Register.............................................................................................. 9-8
RTC Second/1Hz Register ........................................................................................................ 9-9
RTC Hour/Minute Register ....................................................................................................... 9-10
RTC Month/Day Register ......................................................................................................... 9-11
RTC Year/Week Register .......................................................................................................... 9-11
RTC Interrupt Flag Register...................................................................................................... 9-12
RTC Interrupt Enable Register ................................................................................................. 9-13
10 Supply Voltage Detector (SVD).................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pin and External Connection .............................................................................. 10-2
10.2.1 Input Pin......................................................................................................... 10-2
10.2.2 External Connection ...................................................................................... 10-2
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 SVD Operating Clock..................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-3
10.4 Operations ................................................................................................................... 10-3
10.4.1 SVD Control ................................................................................................... 10-3
10.4.2 SVD Operations ............................................................................................. 10-4
10.5 SVD Interrupt and Reset .............................................................................................. 10-4
10.5.1 SVD Interrupt ................................................................................................. 10-4
10.5.2 SVD Reset...................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-5
SVD Clock Control Register ..................................................................................................... 10-5
SVD Control Register ............................................................................................................... 10-6
SVD Status and Interrupt Flag Register ................................................................................... 10-7
SVD Interrupt Enable Register ................................................................................................. 10-8
11 16-bit Timers (T16).....................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pin....................................................................................................................... 11-1
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 T16 Operating Clock...................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-2
11.3.4 Event Counter Clock...................................................................................... 11-2
11.4 Operations ................................................................................................................... 11-2
11.4.1 Initialization .................................................................................................... 11-2
11.4.2 Counter Underflow ........................................................................................ 11-3
11.4.3 Operations in Repeat Mode........................................................................... 11-3
11.4.4 Operations in One-shot Mode ....................................................................... 11-3
11.4.5 Counter Value Read....................................................................................... 11-4
11.5 Interrupt........................................................................................................................ 11-4
11.6 Control Registers ......................................................................................................... 11-4
T16 Ch.nClock Control Register ............................................................................................. 11-4
T16 Ch.nMode Register .......................................................................................................... 11-5
T16 Ch.nControl Register........................................................................................................ 11-5
T16 Ch.nReload Data Register................................................................................................ 11-6
T16 Ch.nCounter Data Register .............................................................................................. 11-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 11-6

CONTENTS
vi Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
T16 Ch.nInterrupt Enable Register.......................................................................................... 11-7
12 UART (UART)..............................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Input Pin Pull-Up Function............................................................................. 12-2
12.2.4 Output Pin Open-Drain Output Function ...................................................... 12-2
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 UART Operating Clock .................................................................................. 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-2
12.3.3 Clock Supply in DEBUG Mode...................................................................... 12-3
12.3.4 Baud Rate Generator..................................................................................... 12-3
12.4 Data Format ................................................................................................................. 12-3
12.5 Operations ................................................................................................................... 12-4
12.5.1 Initialization .................................................................................................... 12-4
12.5.2 Data Transmission ......................................................................................... 12-4
12.5.3 Data Reception .............................................................................................. 12-5
12.5.4 IrDA Interface................................................................................................. 12-6
12.6 Receive Errors.............................................................................................................. 12-7
12.6.1 Framing Error................................................................................................. 12-7
12.6.2 Parity Error..................................................................................................... 12-8
12.6.3 Overrun Error ................................................................................................. 12-8
12.7 Interrupts...................................................................................................................... 12-8
12.8 Control Registers ......................................................................................................... 12-8
UART Ch.nClock Control Register .......................................................................................... 12-8
UART Ch.nMode Register....................................................................................................... 12-9
UART Ch.nBaud–Rate Register ............................................................................................. 12-10
UART Ch.nControl Register ................................................................................................... 12-10
UART Ch.nTransmit Data Register ......................................................................................... 12-11
UART Ch.nReceive Data Register.......................................................................................... 12-11
UART Ch.nStatus and Interrupt Flag Register ....................................................................... 12-11
UART Ch.nInterrupt Enable Register...................................................................................... 12-12
13 Synchronous Serial Interface (SPIA)........................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Pin Functions in Master Mode and Slave Mode............................................ 13-3
13.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 13-3
13.3 Clock Settings.............................................................................................................. 13-3
13.3.1 SPIA Operating Clock.................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode...................................................................... 13-4
13.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 13-4
13.4 Data Format ................................................................................................................. 13-5
13.5 Operations ................................................................................................................... 13-5
13.5.1 Initialization .................................................................................................... 13-5
13.5.2 Data Transmission in Master Mode ............................................................... 13-5
13.5.3 Data Reception in Master Mode.................................................................... 13-7
13.5.4 Terminating Data Transfer in Master Mode.................................................... 13-8
13.5.5 Data Transfer in Slave Mode.......................................................................... 13-8
13.5.6 Terminating Data Transfer in Slave Mode ..................................................... 13-10

CONTENTS
S1C17W15 TECHNICAL MANUAL Seiko Epson Corporation vii
(Rev. 1.3)
13.6 Interrupts..................................................................................................................... 13-10
13.7 Control Registers ........................................................................................................ 13-11
SPIA Ch.nMode Register ....................................................................................................... 13-11
SPIA Ch.nControl Register..................................................................................................... 13-12
SPIA Ch.nTransmit Data Register .......................................................................................... 13-13
SPIA Ch.nReceive Data Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Flag Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Enable Register ....................................................................................... 13-14
14 I2C (I2C).......................................................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 I2C Operating Clock ...................................................................................... 14-3
14.3.2 Clock Supply in DEBUG Mode...................................................................... 14-3
14.3.3 Baud Rate Generator..................................................................................... 14-3
14.4 Operations ................................................................................................................... 14-4
14.4.1 Initialization .................................................................................................... 14-4
14.4.2 Data Transmission in Master Mode ............................................................... 14-5
14.4.3 Data Reception in Master Mode.................................................................... 14-7
14.4.4 10-bit Addressing in Master Mode ................................................................ 14-9
14.4.5 Data Transmission in Slave Mode................................................................. 14-10
14.4.6 Data Reception in Slave Mode ..................................................................... 14-12
14.4.7 Slave Operations in 10-bit Address Mode.................................................... 14-14
14.4.8 Automatic Bus Clearing Operation ............................................................... 14-14
14.4.9 Error Detection.............................................................................................. 14-15
14.5 Interrupts..................................................................................................................... 14-16
14.6 Control Registers ........................................................................................................ 14-17
I2C Ch.nClock Control Register............................................................................................. 14-17
I2C Ch.nMode Register.......................................................................................................... 14-18
I2C Ch.nBaud-Rate Register.................................................................................................. 14-18
I2C Ch.nOwn Address Register ............................................................................................. 14-18
I2C Ch.nControl Register ....................................................................................................... 14-19
I2C Ch.nTransmit Data Register............................................................................................. 14-20
I2C Ch.nReceive Data Register.............................................................................................. 14-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 14-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 14-21
15 16-bit PWM Timers (T16B) ........................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins......................................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-3
15.3.1 T16B Operating Clock ................................................................................... 15-3
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-3
15.3.3 Clock Supply in DEBUG Mode...................................................................... 15-3
15.3.4 Event Counter Clock...................................................................................... 15-3
15.4 Operations ................................................................................................................... 15-4
15.4.1 Initialization .................................................................................................... 15-4
15.4.2 Counter Block Operations ............................................................................. 15-5
15.4.3 Comparator/Capture Block Operations......................................................... 15-8
15.4.4 TOUT Output Control ................................................................................... 15-16
15.5 Interrupt....................................................................................................................... 15-22

CONTENTS
viii Seiko Epson Corporation S1C17W15 TECHNICAL MANUAL
(Rev. 1.3)
15.6 Control Registers ........................................................................................................ 15-22
T16B Ch.nClock Control Register.......................................................................................... 15-22
T16B Ch.nCounter Control Register ...................................................................................... 15-23
T16B Ch.nMax Counter Data Register................................................................................... 15-24
T16B Ch.nTimer Counter Data Register................................................................................. 15-24
T16B Ch.nCounter Status Register........................................................................................ 15-25
T16B Ch.nInterrupt Flag Register........................................................................................... 15-26
T16B Ch.nInterrupt Enable Register ...................................................................................... 15-27
T16B Ch.nComparator/Capture mControl Register.............................................................. 15-28
T16B Ch.nCompare/Capture mData Register....................................................................... 15-30
16 Sound Generator (SNDA) ..........................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Output Pins and External Connections........................................................................ 16-2
16.2.1 List of Output Pins......................................................................................... 16-2
16.2.2 Output Pin Drive Mode .................................................................................. 16-2
16.2.3 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 SNDA Operating Clock.................................................................................. 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Buzzer Output in Normal Buzzer Mode......................................................... 16-3
16.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 16-6
16.4.4 Output in Melody Mode................................................................................. 16-7
16.5 Interrupts...................................................................................................................... 16-9
16.6 Control Registers ......................................................................................................... 16-9
SNDA Clock Control Register .................................................................................................. 16-9
SNDA Select Register ............................................................................................................. 16-10
SNDA Control Register............................................................................................................ 16-11
SNDA Data Register................................................................................................................ 16-11
SNDA Interrupt Flag Register.................................................................................................. 16-12
SNDA Interrupt Enable Register.............................................................................................. 16-13
17 LCD Driver (LCD8B)...................................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Output Pins and External Connections........................................................................ 17-2
17.2.1 List of Output Pins......................................................................................... 17-2
17.2.2 External Connections .................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-2
17.3.1 LCD8B Operating Clock ................................................................................ 17-2
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-3
17.3.3 Clock Supply in DEBUG Mode...................................................................... 17-3
17.3.4 Frame Frequency........................................................................................... 17-3
17.4 LCD Power Supply....................................................................................................... 17-4
17.4.1 Internal Generation Mode .............................................................................. 17-4
17.4.2 External Voltage Application Mode 1............................................................. 17-4
17.4.3 External Voltage Application Mode 2............................................................. 17-4
17.4.4 LCD Voltage Regulator Settings .................................................................... 17-5
17.4.5 LCD Voltage Booster Setting......................................................................... 17-5
17.4.6 LCD Contrast Adjustment.............................................................................. 17-5
17.5 Operations ................................................................................................................... 17-5
17.5.1 Initialization .................................................................................................... 17-5
17.5.2 Display On/Off ............................................................................................... 17-6