Brandywine PMC-SYNCCLOCK32-UNIV Manual

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PMC-SYNCCLOCK32-UNIV
Synchronized Clock with 32 bit PCI
3.3V or 5V Signaling Interface
Operation & Maintenance Manual
13 JUNE 2005
Document No. 8004200
Module S/N ALA H/W Rev Level:B6
Options: -TAG3IRS422-HQ-10OPPSPW422-
PTTIIN-NORDEN2-1TR-CONFCOAT
jxi2, Inc.
10432 Brian Mooney Ave.
El Paso
TX 79935
USA
phone: [phone]
fax: [phone]

Manual Addendum for -HQ -10OPPSPW422-PTTIIN-NORDEN2 options
The PMC-SYNCCLOCK32 module shipped with this manual has the -HQ, -100PPSPW422, -PTTIIN, and—
NORDEN2 options installed.
The -HQRS422 option provides for use of Havequick II serial and 1 PPS time reference per ICD-GPS-060A,
The input pin assignments are:
1PPS /GND: 1PPS: J3 pin 14 /GND: J3 pin 32
serial Havequickll /GND: HQII: J3 pin 17 /GND J3 pin 35
The —100PPSPW422 output option provides 2 100PPS RS422 outputs. The pulse asserts (+ side goes high, - side
goes low) on 10 millisecond boundaries of the on-board clock. The pulse de-asserts when the digits programmed
by the user into the Match_Usec1O_Used_Port register and the Match_Msed_Usec100_Port register match the
1millisecond through 1 microsecond digits of the on-board clock. So, the pulse width may be varied by changing
the match times from Match_Msed_Usec100_Port=00, Match_Usec10_Used_Port=0x01 for a pulse width of 1
microsecond to from Match_Msed_Usec100_Port=0x99, Match_Usec1O_Used_Port=0x99 for a pulse width of 1
microsecond for a pulse width of 9999 microseconds. The 100PPS pin assignments are:
100PPS +1- side output 1 +:J3 pin 27 -: J3 pin 9
100PPS +/- side output 2 +:J3 pin 8 -: J3 pin 26
The —PTTIIN option provides for use of PTTI serial (50 bps) and 1 PPS time reference per ICD-GPS-060B, at
RS422 levels terminated on-board in 100 ohms. The input pin assignments are:
1PPS +/- side: +: J3 pin 2 -: J3 pin 20
serial PTTI (50 bps) +1- side: +: J3 pin 6 -: J3 pin 24
The —NORDEN2 option providies for selection of Havequick II or PTTI 50 bps serial messages as the time
message using dual port RAM location DP_GPS_Status (see gpsdef.h). If bit 0 is CLEARED, Havequick II input
will be used. If bit 1 is SET serial 50 pps PTTI input will be used. Default on power-on or reset is CLEARED.

-TAG3IRS422 Option Manual addendum
The —TAG3IRS422 option provides a total of 3 external event time tags with RS422 inputs level terminated in 100
ohms compared with only one single ended TTL level input on the standard PMC-SYNCCLOCK32. Each of the 3
external time tags has its' own polarity (r or edge) and its' own interrupt enable. Each external time tag has 2
individually addressable 32 time registers and a control/status register
that also contains the low order BCD digit of the captured time (100 ns digit) in bits <7:4>.
External event time tag J3 pin assignments
The J3 pin assignments for the 8 external event time tag inputs are:
External time tag 0 +/- side:
External time tag 1 +/- side:
External time tag 2 +/- side:
+: J3 pin 7
+: J3 pin 4
+: P4 pin 49
-: J3 pin 25
-: J3 pin 22
-: P4 pin 51
Programming external event data input (see t8iregs.h)
The Ext Ready and Ext_Polarity bits of the Status_Port and the Ext_Intr_Enb bit of the
Control_Port are "0" because separate byte width status/control registers are implemented with the -TAG8I .
Whenever an external time tag occurs, the Ext_Ready bit in the corresponding Ext<x>_Ctl_Sts_Port will be
set. The bit is cleared when the first of the two longwords of time tag data is read from
Ext<x>SeclO_Usecl_Port or Ext<x>Yearl Mini_Port. If the Ext_Intr_Enb bit of
Ext<x> Ctl_Sts_Port is set when an event occurs or is simulated, an interrupt request will occur.
To select rising/falling edge time tag polarity for external event input <x>:
Clear (rising edge) or set (falling edge) the Ext_Pol bit in Ext<x>_Ctl_Sts_Port.
To enable interrupts for external event input <x>:
Set (enable) or clear (disable) the Ext_Intr_Enb bit in Ext<x> Ctl_Sts_Port.
To simulate external event input <x>:
Write a 1 in Trigger_SimExt Time_Tag bit in Ext<x>_Sts_Ctl_Port.
The Trigger_Sim_Ext_Time_Tag bit is write-only. It will read back as 0.
To read the time tag data for external event <x>:
Read the two long word data words from Ext<x>_SeclO_Usecl Port and the
Ext<x>_Yearl_Minl_Port and (if desired) the 100 nsec digit from bits <7:4> of
Ext<x>_Ctl_Sts_Port.
The time tag data must be read within 90 milliseconds of the occurrence of the
external event for the data validity of the year..100msec bits to be assured.
The t8imono.c, and t3 itintr .c demo programs in the appendix demonstrate use of the —TAG3I features.

II" t8imono.c 4sep04 jck mask off hi nibl of Extn Ctl Sts Port in Rdy test
/* t8imono.c 17jul01 jck convert to TAG8I (individual data regs) */
/* t8mono.c lapr99 JCK test EXTO..EXT7 time latching by monotonicity */
/* Works with -TAG8I option ONLY. */
/* **** tie all EXTTAG inputs hi or low**** or to MAT (J3 pin 6) */
#include <i86.h>
#include <stdio.h>
#include <conio.h>
Irinclude "t8iregs.h"
union REGS regs;
unsigned long tlo,thi,oldlo,oldhi,oldestlo,oldesthi,subsys id vid;
int BASE,instance=0,any 9050 10b5,any 9030_10b5,i,j,charcnE,MAXCHANNEL=7;
char ready;
Ilmain()
/*
do
1
USE PCI BIOS CALLS TO DETERMINE MEM BASE ADDRESS */
{
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9030;
regs.w.dx=0x10b5;/* query if device id 9030/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9030/10b5 present if 0: %2x bus#: %2x dev/funct: %2x flags: %4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9030 10b5=regs.h.ah;
if Tany_030_10b5==0)
!.egs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor Id. OK if 0: %2x Subsystem ID/VID: %8x flags: %4x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys id vid=regs.x.ecx;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9030 Read PCI base address. OK if 0: %2x base addr: %8x flags: %4x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id vid, try next */
}while ((any 9030 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id vial=Ox104210b5) (any 9030 10b5!=0) )
{printY ("SYNCCLOCK with PLX PC1-9030—not detected on PCI bus\n");
instance=0;
do
{
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9050;
regs.w.dx=0x10b5;/* query if device id 9050/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9050/10b5 present if 0: %.2x bus#: %2x dev/funct: %2x flags: 95.4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9050 10b5=regs.h.ah;
if Tany_{050 —10b5==0)
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: %2x Subsystem ID/VID: %8x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys id vid=regs.x.ecx;
regs.hTahl:Ox0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9050 Read PCI base address. OK if 0: qs2x base addr: %8x flags: %
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id_vid, try next */
}while ((any_ 9050_10b5==0) && (subsys_id_vid!=0x104210b5));

if ((subsys id vid!=0x104210b5) 11 (any 9050_10b5!=0) )
{print! ("SYNCCLOCK with PLX PC19050 not detected on PCI bus \n");
return (0);}
/
oldesthi=oldhi;
II oldestlo=oldlo;
oldhi=thi;
oldlo=tlo;
}
if ((regs.x.ecx&Ox01)!=0) {printf(" IO MAPPED - SHOULD BE MEMORY MAPPED \n");return(0);}
II BASE=regs.x.ecx&Oxfffffffe;
regs.h.ah=0x08;
regs.h.a1=0x00;
regs.w.bx=(BASE»16)&0x0ffff; /*hi 16 bits of phys. addr */
regs.w.cx=BASE&OxOffff; /*lo 16 bits of phys addr */
regs.w.si=0; /* hi 16 bits of region size */
16 bits of region size */
IIint386(0x31,&regs,&reg
BASE=(((long)(regs.w.bx))«16)+(((long)regs.w.cx)&0x0ffff);/* map phys addr into cpu addr space */
printf ("mapped BASE=%08x\n",BASE);
/* IF BOARD IS FOUND, CONTINUE WITH T8IMONO */
I*(volatile unsigned char*)(BASE+Match_MseclUsec100Port)=Oxff; /* prevent match toggle */
*(volatile unsigned char*)(BASE+Match Usec10 UseclPort)=Oxff;
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
Itlo=*(volatile unsigned long*)(BASE+ExtO_SeclO_Usecl_Port+(8*i));
"while (1)
{for (i=0;i<=MAXCHANNEL;i++)
{
II ready=*(volatile unsigned char*)(BASE+ExtO_Ctl_StsPort+(4*i));
*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(4*i))=Trigger_Sim_Ext_Time Tag;
if ((ready&Ox0f)!=1)
printf("Ready flag error: Ext%02x_Ctl_Sts_Port low nibble is %02x after sim evt should
,i,ready&OxOf);
II tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i));
thi=*(volatile unsigned long*)(BASE+Ext0—Yearl—Minl Port+(8*i));
EOready=*(volatile unsigned char*)(BASE+ExCtliSts15ort+(4*i));
if ((ready&Ox0f)!=0)
II printf("Ready flag error: Ext%02x_Ctl_Sts_Port is Ps-02x after sim evt should be 0
,i,ready);
if ( (thi<oldhi) ii ((thi==oldhi) && (tlo<=oldlo) ) )
{printf ("%8x %8x old%8x %8x oldest%8x %8x ch#%01x"
II ,thi,t1o,oldhi,oldlo,oldesthi,oldestlo,i);
if ( thi > oldhi )
charcnt=0;}
{for (1=0;j<=charcnt;j++) printf ("*");
for (j=0;j<40;j++) printf("\b*"); /* force buffer flush */
Iprintf ("\r");
charcnt++;
if (charcnt >=60){ printf ("\n"); charcnt=0;}
IIprintf (" completed ");
return (0);

II//T3ITINTR.0 7JUL06 JCK evt 2 to evt 0 spacing changed to 6 msec
//T3ITINTR.0 11JUN05 JCK FOR -TAG3I (NORDEN) CHANGE MAXCHANNEL:7->2 waitcnt max 10000->100000
/* t8itintr.c 12mar03 JCK BCD version CONNECT TSTOUT<7..0> to EXT<7:0> */
/*b37t8iintr.c 26jun02 JCK. CONNECT TSTOUT<7..0> to EXT<7:0> */
Ili*
P8 <21.48,47,45,43,42,41,25> to J3 pin <26,25,24,23,22,21,19,3> */
/* TST<7..0> generate sliding 1 moving LSB to MSB, so EVTn 1 msec after EVTn-1 */
/* t8iintr.c 20jul01 JCK convert -TAG8 to -TAG8I */
/* t8intr.c 2apr99 JCK tests pci-sync32-tag8 intr generation capability */
II/* connect all ext time tag inputs hi,lo, or to mat to prevent unwanted tags */
/* THIS DEMO CODE MAY HAVE PROBLEMS WORKING WITH IRQ LEVELS 3 or 5 */
typedef unsigned char byte;
#include "t8iregs.h" /* offsets for PCI-SYNCCLOCK regs + flag definitions */
#include "picdef.h" /* addresses for host x86 interrupt ctlrs & vectors */
include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
rinclude <ctype.h>
#include <dos.h>
#include <conio.h>
#include <i86.h>
union REGS regs;
IIunsigned long intcount=0,subsys id_vid;
int BASE,instance=0,any 9050 1()E5,any_9030_10b5;
void interrupt pc intTvoidT;
void setvects(voia);
IIvoid resvects(void);
void i_enable(void);
void i disable(void);
void ( interrupt far *oldvec)()=0;
lint bin (int valueYi
volatile long int c;
volatile char readlMR;
volatile unsigned long int busec,oldbusec,oldthi,oldtlo,t1o,thi,waitcnt;
int xnsec100,1,j,ready70,charcnt,MAXCHANNEL=2,error=0,expectedchannel;
IIint errcnt=0;errchan[10000],intflag=0,passcount=0;
unsigned char Extsts(64];
char IMRMASK,IMRENB[16]={0xff,Oxff,Oxff,Oxff,Oxff,Oxff,Oxff,Oxff,
Oxfe,Oxfd,Oxfb,0xf7,0xef,0xff,Oxff,0x7f};
char VECTOR,IRQVEC[16]={0,0,0,0,0,0,0,0,0x70,0x0A,0x72,0x73,0x74,0,0,0x77};
'rain()
{/* USE PCI BIOS CALLS TO DETERMINE MEM BASE ADDRESS */
do {
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9030;
regs.w.dx=0x10b5;/* query if device id 9030/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9030/10b5 present if 0: %2x bus#: 962x dev/funct: %2x flags: %4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9030 10b5=regs.h.ah;
if Tany g030 10b5==0)
—{
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: 962x Subsystem ID/VID: %8x flags: 964x \
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys_id_vid=regs.x.ecx;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9030 Read PCI base address. OK if 0: %2x base addr: *8x flags: %4x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id_vid, try next */
}while} ((any 9030 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id via!=0x104210b5) (any_9030 10b5!=0) )
{print!. ("SYNCCLOCK with PLX PCI9030not detected on PCI bus\n");
instance.();
do
{
regs.h.ah=0x0b1;

II/
printf (" Ext evt 0-2 external event inputs have been detected \n");
setvects();
ienable();
II while (errcnt<20)
{
intcount=0;
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
{tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i));I
II /* while waiting for event 7 clear evt 0..6 ready status */—
if (MAXCHANNEL>0)
do
{for (i=0;i<=MAXCHANNEL-1;i++) tlo=*(volatile unsigned IIlong*)(BASE+ExtOSeclO_Usecl Por
/* of event 7 and init oldbusec */ _
oldtlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(MAXCHANNEL*8));
oldthi=*(volatile unsigned long*)(BASE+Ext0—YearliMinlPort +(MAXCHANNEL*8));
IIoldbusec=bin((oldthi )&0x0ff)*60000000 —
regs.h.a1=0x02;
regs.w.cx=0x9050;
regs.w.dx=0x10b5;/* query if device id 9050/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9050/10b5 present if 0: 962x bus#: %2x dev/funct: %2x flags: 964x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9050 10b5=regs.h.ah;
if Tany_-9-050 10b5==0)
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: %.2x Subsystem ID/VID: 968x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsysid_vid=regs.x.ecx;
regs.h._ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9050 Read PCI base address. OK if 0: 962x base addr: 96-8x flags: %
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys id vid, try next */
}while ((any 9050 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id vid!=0x104210b5) II (any 9050 lbb5!=0) )
{printf ("SYNCCLOCK with PLX PC19050—not detected on PCI bus \n");
return (0);}
}
IIif ((regs.x.ecx&0x01)!=0) {printf(" IO MAPPED - SHOULD BE MEMORY MAPPED \n");return(0);}
BASE=regs.x.ecx&Oxfffffffe;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
IIregs.w.di=0x3c; /* query latency,grant,interrupt pin,interrupt line */
int386(0x1a,&regs,&regs);
printf("Read PCI config reg 3C. OK if 0: 9602x config reg3c: %08x flags: %04x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
IMRMASK=IMRENB[regs.x.ecx&Ox0f];
IIVECTOR=IRQVEC[regs.x.ecx&Ox0f];
printf ("IRQLINE: 9602x IMRMASK: W02x IRQVEC[IRQLEVEL]: %02x \n",
regs.x.ecx&Ox0f,IMRMASK, IRQVEC[regs.x.ecx&Ox0f]);
regs.h.ah=0x08;
regs.h.a1=0x00;
regs.w.bx=(BASE»16)&0x0ffff; /*hi 16 bits of phys. addr */
regs.w.cx=BASE&OxOffff; /*lo 16 bits of phys addr */
regs.w.si=0; /* hi 16 bits of region size */
regs.w.di=0x20; /* lo 16 bits of region size */
IIint386(0x31,&regs,&regs); /* map phys addr into cpu addr space */
BASE=(((long)(regs.w.bx))«16)+(((long)regs.w.cx)&0x0ffff);
printf ("mapped BASE=9608x\n",BASE);
*(volatile unsigned char*)(BASE+ControlPort)=0; /* disable hb,ramfifo,mat,cmd rd
II*(volatile unsigned char*)(BASE+Match_Usec10 UseclPort)=0x00 ;
*(volatile unsigned char*)(BASE+Match_Msecl_Usec100_Port)=0x10 ; // 100pps pulse on norden2 will
sleep(1);
// POLL all MAXCHANNEL+1 event inputs to make sure they are occuring
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
{*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(j*4))=0;
printf (" check channel Wd for event input present\n",i);
tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i)); // clear Ext Ready
while ((*(volatile unsigned char*)(BASE+ExtO_Cfl_Sts:Port+(i*4)) & Ext_Ready)==0) {;}

+bin((oldtlo»24)&0x0ff)*1000000
+bin((oldtlo»16)&0x0ff)*10000
+bin((oldtlo»8 )&0x0ff)*100
11 +bin((oldtlo )&0x0ff)*1;
for (i=0;i<=MAXCHANNEL;i++) tlo=*(volatile unsigned long*)(BASE+ExtO_SeclO_Usecl_Port+(8*i));
for (j=0;j<=MAXCHANNEL;j++)
if ( (*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(j*4))&ExtReady)!=0 )
if (error) *(volatile unsigned cfiar*T(BASE+Ext0 Ctl_Sts Port+(j*4)));error=1;1
Initial Ext%Olx Ctl Sts Port= %02X should be 00 \n",j,
II
readlMR = inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
outp(IMR, readlMR)
IIwhile ( (((intcount+1)%10000)!=0) && (errcnt<20))
expectedchannel=intcount%(MAXCHANNEL+1);
for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+ExtO_Ctl_Sts Port+(j*4))=Ext_Intr_
waitcnt=0;
do {readlMR = inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
outp(IMR, readlMR)
waitcnt++;} while ((waitcnt<100000) & (intflag==0));
intflag=0;
/* && ( (*(volatile unsigned char*)(BASE+Ext0 Ctl_Sts_Port+(expectedchannel*4)
&& ( (Extsts[expectedchannel]&Ext Ready)==0)
); */
if (waitcnt>=100000)
{printf(" Ext%Olx Ctl Sts Port= %02x should be 01 \n",intcount%8,Extsts[expectedchannel]);
return(0);1
for (j=0;j<=MAXCHANNEL;j++)
{
if ( (j!=expectedchannel) && ((Extsts[j]&Ext_Ready)!=0) )errchan[errcnt++]=j;
Extsts[j]=0;
/
busec=bin((thi )&0x0ff)*60000000
+bin((tlo»24)&0x0ff)*1000000
+bin((tlo»16)&0x0ff)*10000
+bin((tlo»8 )&0x0ff)*100
+bin((tlo )&0x0ff)*1;
if
((expectedchannel!=0) && ( ( (busec-oldbusec)>1001) 11 ( (busec-oldbusec) <999 ) ) )
1
((expectedchannel==0) && ( ( (busec-oldbusec)>6001) 11 ( (busec-oldbusec)<5999 ) ))
)
{
printf ("tlo=%081x oldtlo=%08x delta:%d intcount:%d \n",t1o,oldtlo,busec-oldbusec,intcoun
return(0);
/
oldtlo=tlo;
oldbusec=busec;
IIintcount++;
for/ (i=0;i<=MAXCHANNEL;i++) *(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(i*4))=0; /* disab
printf ("intcount=%lu errcnt=%d passcount=%d \n",intcount,errcnt,passcount);
II passcount++;
if (errcnt!=0)
{
for (i=0;i<errcnt;i++) printf("%01x ",errchan[i]);
Trintf ("\n");
for (i=0;i<1000000;i++) j=*(volatile unsigned char*)(BASE+ExtO_Ctl_Sts_Port); /* delay for print
II
resvects(); /* example doesn't call resvects & i disable */
Ili disable();
urn(0); /* but user code should call them */—
}
et/* this is the actual interrupt handler code.
It is entered via a VECTORED interrupt.
IIWhen the ISA-SYNCCLOCK asserts the configured IRQ signal ,
the bus IRQ signal drives a pin on a 8259 priority interrupt controller on
the host CPU board.
II(Actually, the priority interrupt controller is probably embedded inside a
big LSI glue chip - but it still looks like an 8259 to the programmer and
the bus).
The 8259 then in turn - if the interrupt input level is enabled -
IIwill try to interrupt the host x86 processor. When the x86 accepts the
interrupt the 8259 will supply an interrupt vector (VEC9 in this example)
The x86 will then pick up a FAR pointer from the interrupt vector location
and use it as the address for entering the interrupt routine. */

"void interrupt far pc_int(void) /* Handle external event interrupts */
int—j,discard;
I/* —disable(); */ /* causes compiler to EMIT x86 "CLI" op code */ —
intflag=1; /* notify bkgnd program that pci-sync32 ext intr occured */
for (j=0;j<=MAXCHANNEL;j++) Extsts[j]=*(volatile unsigned char*)(BASE+ExtOCtl Sts Port+(j*4
tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 UseclPort+(8*expectedchannel));
thi=*(volatile unsigned long*)(BASE+Ext0 Yearl Minl_Port +(8*expectedchannel));
II for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+ExtO_Ctl Sts Port+(j*4))=0; /* d
for (j=0;j<=MAXCHANNEL;j++)
discard=*(volatile unsigned long*)(BASE+ExtOSeclO_Usecl Port+(8*j)); /* read selected
outp(ICR, EOI); /* Signal end of hardware interrupt */
outp(ICRO 7, EOI); /* Signal end of hardware interrupt */
III enable(); /* causes compiler to EMIT x86 "STI" op code */
void setvects() /* Change intr vector to point to PC-SYNCCLOCK interrrupt code */
{if ( !oldvec) {
II / oldvec = dos getvect(VECTOR); /* save old vector */
dos setvct(VECTOR, pc int); /* set new vector */
/
"void resvects(void) /* Uninstall our vectors before exiting the program */
Iif (oldvec) _dossetvect(VECTOR, oldvec);
void i enable() /* Enable PC-SYNCCLOCK interrupts */
III _disable(); /* causes compiler to EMIT x86 "CLI" op code */
c= inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
II /* outp(IMR, c); */
enable(); /* causes compiler to EMIT x86 "STI" op code */
}
void i disable(void) /* Turn off PCI-SYNCCLOCK interrupts */
{int c;
disable(); /* causes compiler to EMIT x86 "CLI" op code */
c= inp(IMR) I -IMRMASK; /* set mask bit to "1" to disable */
outp(IMR, c);
for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+Ext0 Ctl_Sts Port+(j*4))=0;
enable(); /* causes compiler to EMIT x86 "STI" op code */
int bin (int value)
II{return (((((value&Ox0f0)/16)*10) + (value&Ox0f))&0x0ff );I
1

Manual Addendum for -HQ -10OPPSPW422-PTTIIN-NORDEN2 options
The PMC-SYNCCLOCK32 module shipped with this manual has the -HQ, -10OPPSPW422, -PTTIIN, and—
NORDEN2 options installed.
The -HQRS422 option provides for use of Havequick II serial and 1 PPS time reference per ICD-GPS-060A,
The input pin assignments are:
1PPS /GND: 1PPS: J3 pin 14 /GND: J3 pin 32
serial Havequickll /GND: HQII: J3 pin 17 /GND J3 pin 35
The —10OPPSPW422 output option provides 2 100PPS RS422 outputs. The pulse asserts (+ side goes high, - side
goes low) on 10 millisecond boundaries of the on-board clock. The pulse de-asserts when the digits programmed
by the user into the Match_Usec10 Useci_Port register and the Match_Msec1 Usec100_Port register match the
1millisecond through 1 microsecond digits of the on-board clock. So, the pulse width may be varied by changing
the match times from Match_Msed_Usec100_Port=00, Match_Usec10 Used_Port=0x01 for a pulse width of 1
microsecond to from Match_Msec1 Usec100_Port=0x99, Match Usec10 Used_Port=0x99 for a pulse width of 1
microsecond for a pulse width of 9999 microseconds. The 100PPS pin assignments are:
100PPS +/- side output 1 +:J3 pin 9 -: J3 pin 27
100PPS +/- side output 2 +:J3 pin 8 -: J3 pin 26
The —PTTIIN option provides for use of PTTI serial (50 bps) and 1 PPS time reference per ICD-GPS-0606, at
RS422 levels terminated on-board in 100 ohms. The input pin assignments are:
1PPS +/- side: +: J3 pin 2 -: J3 pin 20
serial PTTI (50 bps) +/- side: +: J3 pin 6 -: J3 pin 24
The —NORDEN2 option providies for selection of Havequick II or PTTI 50 bps serial messages as the time
message using dual port RAM location DP_GPS_Status (see gpsdef.h). If bit 0 is CLEARED, Havequick II input
will be used. If bit 1 is SET serial 50 pps PTTI input will be used. Default on power-on or reset is CLEARED.

Manual Addendum —ITR-CONFCOAT options
The PMC-SYNCCLOCK32 module shipped with this manual has the —ITR and -CONFCOAT
options installed.
The —ITR option uses integrated circuits that are rated —40C to +85C.
The —CONFCOAT option is conformal coating.

INTRODUCTION 4
SPECIFICATIONS
Physical:
Inputs & Outputs (see addenda at front of manual for custom options)
Bus Interface (see addenda at front of manual for special options):
PCI Configuration Registers
5
5
5
6
7
INPUT/OUTPUT CONNECTIONS 8
Bezel J1, J2 (SMB): 8
Front Panel J3 (IEEE 1284 type jack): (see addenda at front of manual for custom options) 8
PMC Bus Connector (PI/P2): 9
PMC bus P4: (see manual front addendum for custom options) 10
CONFIGURATION, INSTALLATION & OPERATION 11
Configuration:
Modulated Code Input Termination (P6)
External Oscillator Input Termination (P7)
1PPS 50 ohm termination (P8)
Installation
PCI Address Verification (Power PC VME boards
PCI Address/IRQ Configuration Verification (X86 systems)
Determining Dual Port Ram Time Code Propagation Delay Setting
Determining Dual Port Ram 1PPS Propagation Delay Setting
Operation
Have Quick
LED Status Indication
PROGRAMMING
Introduction
PCI Configuration Registers
Accessing PMC-SYNCCLOCK in Windows environment
Program Development in Windows environment
Reading Current Time (BCD Format) (non -BIN option)
Multiple Threads Reading Current Time (BCD Format)
11
11
11
11
11
11
12
12
12
12
12
13
14
14
14
15
15
16
16
1

1
Reading Current Time (-BIN option only) 16
Reading External Time Tags (non -BIN option) 17
Reading External Binary Time Tags (-BIN option only) 18
Simulating External Time Tags 18
Heartbeat Pulses and Interrupts 19
Dual Port RAM for Supplementary Status/Control 19
Accessing Dual Port RAM 19
Sending Commands through the Dual Port RAM. 20
Setting Leap Year Control in Dual Port RAM 20
Selecting 1PPS or Time Code Reference Priority in Dual Port RAM 20
Setting Time Code Propagation Delay Polarity in Dual Port RAM 21
Setting PPS Propagation Delay in Dual Port RAM 21
Specifying Modulated Input Code Format in Dual Port RAM 21
Specifying Leap Second Day in Dual Port RAM 21
Setting Time Code Propagation Delay in Dual Port Ram 22
Non-volatile Propagation Delay Settings 22
Setting PPS Propagation Delay in Dual Port Ram 22
Setting Major Time in Dual Port RAM 22
Setting Year in Dual Port RAM 22
Changing Heartbeat, Lowrate and Rate2 23
GPS Satellite Tracking and Navigation Data (except Have-Quick receivers) 24
Differential Data Acknowlege Count (-DF option with Motorola Oncore Only) 25
GPS Satellite Data (Have-Quick receivers) 25
THEORY OF OPERATION 26
Time Code Stripping 26
Input Signal Coupling 26
Zero Crossing Detector 26
Voltage Divider 27
Peak Detector 27
Burst Decoder 27
FPGA Clock 27
200ms .. 8 Year Bits 27
Disciplining 27
Clock conditioning 28
Modulated code generation 28
Error Measurement 28
Match Times 28
3.0 MHz frequency generation 29
Heartbeat Rates 29
Microcomputer 29
D/A frequency control (DTCXO option) 29
GPS receiver serial interface 29
HAVE QUICK interface option 29
PCI Bus Interface 29
BOARD LAYOUT 31
2

SCHEMATIC DRAWINGS 32
PARTS LIST 36
PROGRAM LISTINGS 38
3

Introduction
The PMC-SYNCCLOCK32-UNIV is a digital clock with a PMC (mezzanine PCI) bus interface that will
automatically synchronize to time reference signals. The "UNIV" designates its' ability to function in systems with
3.3V or 5V PCI bus signaling levels. It is software compatible with older PMC-SYNCCLOCK32-UNIV models that
were 5V signaling only. Programs running on the PMC host can read the clock time directly from longword
registers. In many applications, no other user programming is needed. The advantages of the PMC-
SYNCCLOCK32's digital clock over the host system "real time" clock include better resolution (100 nsec vs. msec
or worse), easier access (single C statement vs. DOS system call) and - most importantly - stability and
synchronization to Universal Coordinated Time by locking to time reference signals.
The time reference signals can be standardized modulated "time code" signals (IRIG-B, IRIG-A, NASA-36, 2137
or XR3). Or, the reference can be a 1 PPS time pulse from an external GPS or LORAN receiver. Even though the
time reference occurs as slowly as once per second, the on-board clock maintains specified accuracy and
resolution by using a phase locked 10 MHz crystal oscillator. The user program can specify the propagation delay
from the time code source to the PMC or the 1 PPS source to the PMC-SYNCCLOCK32-UNIV input and the
PMC-SYNCCLOCK32-UNIV will automatically adjust the clock to compensate for the delay. A redundancy feature
allows BOTH a 1 PPS signal and a time code to be used as references. The user can specify which reference is
preferred. If the preferred reference is invalid, the secondary reference is used until the primary becomes valid
again. A user-supplied military GPS receiver ( the "Plugger" for example) with "Have Quick" output may be used
as the time reference (-HQ option)
In addition to the registers that latch the time when a user program reads the clock, a second set of time registers
is used to accurately capture the time of external "time tag" pulses (with 100 nanosecond resolution). Because
external pulses may occur at unpredictable times a PCI bus interrupt may be enabled by the user to signal the
occurrence of an external event and cause the captured time to be stored in host memory, With modern host
processor speeds, external pulse spacing as low as a few µseconds may be supported.
Two user selected pulse rates (one from 1.5 M PPS to 45.77 PPS and one configurable 50 PPS to .00153 PPS or
1.5 M PPS to 45.77 PPS) are locked to the clock frequency. The 1.5 M PPS to 45.77 PPS rate can cause
"heartbeat" interrupts to periodically wake up host processes. The user also has direct access to a comparator for
generating "match" pulses or toggles at precise times.
The PMC-SYNCCLOCK32-UNIV is designed so that the most common user applications require the least
programming. For example, reading current time can be accomplished with a single C statement. Data and
parameters that need fast access and update are assigned individual registers directly accessible over the PMC
bus, while a much larger number of infrequently (if ever) accessed status and control parameters are accessed by
aDual Port Ram occupying only two PMC bus addresses.
For Windows environments (NT 4.0, 2000, 98, XP), drivers and access for all registers is provided using a virtual
address pointer to the base address of the registers. This software links to a library provided by PLX Technology
who makes the PC19030 bridge device that sits between the PCI bus and the local bus to which the clock registers
are connected. Use of the PLX software is subject to the following restriction:
Copyright ©2001 PLX Technology, Inc. PLX Technology Inc. licenses this software
under specific terms and conditions. Use of any of the software or derivatives thereof
in any product without a PLX Technology chip is strictly prohibited.
The PMC-SYNCCLOCK32-UNIV uses a PLX Technology chip, so the licensing requirement is satisfied. Sample
"C" source Windows programs and definition files are supplied to speed programming operations. Users who
require interrupt support in Windows must purchase a development seat of Winlntr software. Winlntr includes the
PLX SDKPro software package along with sample and demo applications using interrupts in the Windows
environment.

SPECIFICATIONS
Physical:
Dimensions:
Power:
Fabrication:
Tem pe ra tu re :
Humidity:
74 mm X 149 mm ("Single CMC")
+5V ±5% .12A typ, .15A max
+3.3V±5% .12A max
+12V± 5%: .06A typ .10A max
-12V± 5%: .025A typ .05A max
1.68mm±.2mm (.062 in±008in)
FR4, 6 layer
0to 70C operating, -40C to 85C storage
-40C to +85C operating with —ITR option
0to 99% non-condensing
Inputs & Outputs (see addenda at front of manual for custom
options)
Inputs:
Multipin Input/output connector: J3 Hi Density 36 pin IEEE1284 type. Mating connector is Molex 52316-3611.
See input/output pin assignment section for recommendations on mating
pre-assembled cables
Coaxial time code input/output connectors Right angle SMB
Code input types: Modulated IRIG-A,B,NASA36.XR3,2137 and IRIG-G optional
Code input amplitude: 250 mV to 10y pk/pk
Code input modulation ratio: 2:1 to 4:1
Code input frequency error: 100PPM maximum
Code input impedance: >10K ohm
Code Sync accuracy: 1µsec
1PPS Sync accuracy: 100 nsec
External event pulse input: T or .1, edge TTL
Minimum event to event spacing
(host interrupt mode):
1PPS input:
Have Quick input:
Outputs:
Modulated IRIG-B (option) :
Match:
Status (Red LED):
Sync Indicator (Green LED):
Limited only by host speed
TTL level positive edge
per ICD-GPS-060
2.5V±10% pk/pk into 600Q
TTL pulse
Flashes coded patterns
Lights if SYNCOK status is set
5

Bus Interface (see addenda at front of manual for special
options):
Addressing:
Interrupt levels:
Register Assignments:
Offset from Bits
Base Addr Bit 0 is
LSB
PCI memory space (8 contiguous longwords)
INTA
Read Usage Write Usage
0<31:0> Zero latency Read Only
40 sec .. 1 µsec BCD time (BCD)
µsec<31:0> for -BIN option
4<31:0> Zero latency 8 year .. 1 minute BCD
time. For -BIN option:
Read Only
<31:22>=0,<21:14> binary year of
century, <13:5> binary day of year,
<4:0> = µsec<36:32>
8<31:0> External time tag 40 sec .. 1 µsec Read Only
BCD time. For -BIN option ,
µsec<31:0>
C<31:0> External time tag 8 year .. 1 minute Read Only
BCD time. For -BIN option:
<31:22>=0,<21:14> binary year of
century, <13:5> binary day of year,
<4:0> = psec<36:32>
10 01=External time tag data ready "1" simulates external time
tag
11=Command Response Ready Read Only
2n/u n/u
3Match Flag "1" clears match flag
4Heartbeat Flag Read Only
5External Event Polarity 0=T,
1=.1-edge
Same as read
6In-Sync Flag Read Only
11 0External time tag data ready interrupt
enable
1= enable, 0=disable
1CMD response ready interrupt
enable
1= enable, 0=disable
2N/U N/U
3Time Match flag interrupt enable 1= enable, 0=disable
4Heartbeat pulse interrupt enable 1= enable, 0=disable
5Time Match Extended toggle enable 1= enable, 0=disable
6n/u n/u
7n/u n/u
14 <7:0> Write Only Match Time 10 µsec, 1
µsec digits
15 <7:0> Write Only Match Time 1 msec, 100
psec digits
1A <7:0> Write Only Dual Port RAM Address
1E <7:0> Dual Port RAM Data Same as read
6

PCI Configuration Registers
PCI CFG
register
address
Bits <31:24> Bits <23:16> Bits <15:8> Bits <7:0> PCI Writeable EEPROM
Writeable
00h Device ID Vendor ID N Y
9030 10135
04h Status Command Y N
0002 0000
08h Class Code Rev. ID NY(<31:8>)
0680 0001
Och BIST Header Type Latency Timer Cache Line Y(<7:0>) N
00 00 00 00
10h PCI Base Addr 0 for Memory Mapped Local Bus Config Registers YN
00 00 00 00
14h PCI Base Address 1 for I/O Mapped Local Bus Config Registers YN
00 00 00 00
18h PCI Base Address 2 for Local Bus Address Space 0 Y N
00 00 00 00
1ch PCI Base Address 3 for Local Bus Address Space 1 (not used) YN
00 00 00 00
20h PCI Base Address 4 for Local Bus Address Space 2 (not used) YN
00 00 00 00
24h PCI Base Address 5 for Local Bus Address Space 3 (not used) YN
00 00 00 00
28h Cardbus CIS Pointer (Not Supported) NN
00 00 00 00
2ch Subsystem ID Subsystem Vendor ID N Y
1042 1065
30h PCI Base Address for Local Expansion ROM (not used) YN
00 00 00 00
34h reserved NN
38h reserved N N
3C Max Latency Min Grant Interrupt Pin Interrupt Y(<7:0>) Y(<15:8>)
Default values in italics EEPROM initialization values in bold
00 00 01 00
7

INPUT/OUTPUT CONNECTIONS
Bezel J1, J2 (SMB):
J1 is used for modulated time code input.
J2 (optional) is used for modulated time code output (option).
Front Panel J3 (IEEE 1284 type jack): (see addenda at front of
manual for custom options)
Pin 1: Time Code Input ("+" side if balanced input)
Pin 2: + Side of RS422 1 PPS input from External GPS Receiver
Pin 3: Ground
Pin 4: + Side of RS422 Serial Data Output to External GPS Receiver
Pin 5: + Side of RS422 Serial Data Input from External GPS Receiver
Pin 6: + Side of RS422 Serial RTCM104 Serial Differential Data (-DF option only)
Pin 7: + Side of RS422 DC level shift time code input (-DCCODE options only)
Pin 8: + Side of RS422 DC level shift time code output
Pin 9: + Side of Auxiliary RS422 output (special options only)
Pin 10: Time tag input
Pin 11: CLKO: Low rate (50 PPS ...00153 PPS) user programmable pulse output
Pin 12: CLK2: High rate (1.5 M PPS to 45.7 PPS) user programmable pulse output
Pin 13: CLK1: HEARTBEAT user programmable pulse output
Pin 14: Have Quick 1 PPS in. Have Quick 1 PPS in. P8 configures 50 ohm termination. Diode
clamped thru 75ohms to +5V.( If using with PLUGGER, connect to pin 6 of Plugger)
Pin 16: Optional modulated time code output
Pin 17: Have Quick Serial Data In (option). ( If using Plugger, connect to pin 7 of Plugger.)
Pin 18: External oscillator sine wave input (option)
Pin 19: Time Code Input Ground (or "2 side if balanced input)
Pin 20: - Side of RS422 1 PPS input from External GPS Receiver
Pin 21: Ground
Pin 22: - Side of RS422 Serial Data Output to External GPS Receiver
Pin 23: - Side of RS422 Serial Data Input from External GPS Receiver
Pin 24: - Side of RS422 Serial RTCM104 Serial Differential Data (-DF option only)
Pin 25: - Side of RS422 DC level shift time code input (-DCCODE options only)
Pin 26: + Side of RS422 DC level shift time code output
Pin 27: + Side of Auxiliary RS422 output (special options only)
Pin 29: "REF" unprotected TTL level 1PPS input. Use of pin 14 is recommended.
Pin 31: "MATCH" pulse output
Pin 32: Ground
Pin 34: Ground
Pin 36: Ground
Unassigned pins are reserved
Because the mating connector for J3 requires expensive tooling, most users needing J3 interface
by using prefabricated cable assemblies that mate with J3 and breaking out wire pairs for their
application.
L-COM has cable assemblies (CSM84CC series) with mating connectors at each end that may be
cut in half to make two mating cables. The pin assignments on J3 line up with CSM84CC twisted
pair assignments. Each row of the table below corresponds to one wire pair:
8