Brandywine PMC-SYNCCLOCK32-UNIV Manual

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PMC-SYNCCLOCK32-UNIV
Synchronized Clock with 32 bit PCI
3.3V or 5V Signaling Interface
Operation & Maintenance Manual
13 JUNE 2005
Document No. 8004200
Module S/N ALA H/W Rev Level:B6
Options: -TAG3IRS422-HQ-10OPPSPW422-
PTTIIN-NORDEN2-1TR-CONFCOAT
jxi2, Inc.
10432 Brian Mooney Ave.
El Paso
TX 79935
USA
phone: [phone]
fax: [phone]

Manual Addendum for -HQ -10OPPSPW422-PTTIIN-NORDEN2 options
The PMC-SYNCCLOCK32 module shipped with this manual has the -HQ, -100PPSPW422, -PTTIIN, and—
NORDEN2 options installed.
The -HQRS422 option provides for use of Havequick II serial and 1 PPS time reference per ICD-GPS-060A,
The input pin assignments are:
1PPS /GND: 1PPS: J3 pin 14 /GND: J3 pin 32
serial Havequickll /GND: HQII: J3 pin 17 /GND J3 pin 35
The —100PPSPW422 output option provides 2 100PPS RS422 outputs. The pulse asserts (+ side goes high, - side
goes low) on 10 millisecond boundaries of the on-board clock. The pulse de-asserts when the digits programmed
by the user into the Match_Usec1O_Used_Port register and the Match_Msed_Usec100_Port register match the
1millisecond through 1 microsecond digits of the on-board clock. So, the pulse width may be varied by changing
the match times from Match_Msed_Usec100_Port=00, Match_Usec10_Used_Port=0x01 for a pulse width of 1
microsecond to from Match_Msed_Usec100_Port=0x99, Match_Usec1O_Used_Port=0x99 for a pulse width of 1
microsecond for a pulse width of 9999 microseconds. The 100PPS pin assignments are:
100PPS +1- side output 1 +:J3 pin 27 -: J3 pin 9
100PPS +/- side output 2 +:J3 pin 8 -: J3 pin 26
The —PTTIIN option provides for use of PTTI serial (50 bps) and 1 PPS time reference per ICD-GPS-060B, at
RS422 levels terminated on-board in 100 ohms. The input pin assignments are:
1PPS +/- side: +: J3 pin 2 -: J3 pin 20
serial PTTI (50 bps) +1- side: +: J3 pin 6 -: J3 pin 24
The —NORDEN2 option providies for selection of Havequick II or PTTI 50 bps serial messages as the time
message using dual port RAM location DP_GPS_Status (see gpsdef.h). If bit 0 is CLEARED, Havequick II input
will be used. If bit 1 is SET serial 50 pps PTTI input will be used. Default on power-on or reset is CLEARED.

-TAG3IRS422 Option Manual addendum
The —TAG3IRS422 option provides a total of 3 external event time tags with RS422 inputs level terminated in 100
ohms compared with only one single ended TTL level input on the standard PMC-SYNCCLOCK32. Each of the 3
external time tags has its' own polarity (r or edge) and its' own interrupt enable. Each external time tag has 2
individually addressable 32 time registers and a control/status register
that also contains the low order BCD digit of the captured time (100 ns digit) in bits <7:4>.
External event time tag J3 pin assignments
The J3 pin assignments for the 8 external event time tag inputs are:
External time tag 0 +/- side:
External time tag 1 +/- side:
External time tag 2 +/- side:
+: J3 pin 7
+: J3 pin 4
+: P4 pin 49
-: J3 pin 25
-: J3 pin 22
-: P4 pin 51
Programming external event data input (see t8iregs.h)
The Ext Ready and Ext_Polarity bits of the Status_Port and the Ext_Intr_Enb bit of the
Control_Port are "0" because separate byte width status/control registers are implemented with the -TAG8I .
Whenever an external time tag occurs, the Ext_Ready bit in the corresponding Ext<x>_Ctl_Sts_Port will be
set. The bit is cleared when the first of the two longwords of time tag data is read from
Ext<x>SeclO_Usecl_Port or Ext<x>Yearl Mini_Port. If the Ext_Intr_Enb bit of
Ext<x> Ctl_Sts_Port is set when an event occurs or is simulated, an interrupt request will occur.
To select rising/falling edge time tag polarity for external event input <x>:
Clear (rising edge) or set (falling edge) the Ext_Pol bit in Ext<x>_Ctl_Sts_Port.
To enable interrupts for external event input <x>:
Set (enable) or clear (disable) the Ext_Intr_Enb bit in Ext<x> Ctl_Sts_Port.
To simulate external event input <x>:
Write a 1 in Trigger_SimExt Time_Tag bit in Ext<x>_Sts_Ctl_Port.
The Trigger_Sim_Ext_Time_Tag bit is write-only. It will read back as 0.
To read the time tag data for external event <x>:
Read the two long word data words from Ext<x>_SeclO_Usecl Port and the
Ext<x>_Yearl_Minl_Port and (if desired) the 100 nsec digit from bits <7:4> of
Ext<x>_Ctl_Sts_Port.
The time tag data must be read within 90 milliseconds of the occurrence of the
external event for the data validity of the year..100msec bits to be assured.
The t8imono.c, and t3 itintr .c demo programs in the appendix demonstrate use of the —TAG3I features.

II" t8imono.c 4sep04 jck mask off hi nibl of Extn Ctl Sts Port in Rdy test
/* t8imono.c 17jul01 jck convert to TAG8I (individual data regs) */
/* t8mono.c lapr99 JCK test EXTO..EXT7 time latching by monotonicity */
/* Works with -TAG8I option ONLY. */
/* **** tie all EXTTAG inputs hi or low**** or to MAT (J3 pin 6) */
#include <i86.h>
#include <stdio.h>
#include <conio.h>
Irinclude "t8iregs.h"
union REGS regs;
unsigned long tlo,thi,oldlo,oldhi,oldestlo,oldesthi,subsys id vid;
int BASE,instance=0,any 9050 10b5,any 9030_10b5,i,j,charcnE,MAXCHANNEL=7;
char ready;
Ilmain()
/*
do
1
USE PCI BIOS CALLS TO DETERMINE MEM BASE ADDRESS */
{
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9030;
regs.w.dx=0x10b5;/* query if device id 9030/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9030/10b5 present if 0: %2x bus#: %2x dev/funct: %2x flags: %4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9030 10b5=regs.h.ah;
if Tany_030_10b5==0)
!.egs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor Id. OK if 0: %2x Subsystem ID/VID: %8x flags: %4x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys id vid=regs.x.ecx;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9030 Read PCI base address. OK if 0: %2x base addr: %8x flags: %4x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id vid, try next */
}while ((any 9030 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id vial=Ox104210b5) (any 9030 10b5!=0) )
{printY ("SYNCCLOCK with PLX PC1-9030—not detected on PCI bus\n");
instance=0;
do
{
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9050;
regs.w.dx=0x10b5;/* query if device id 9050/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9050/10b5 present if 0: %.2x bus#: %2x dev/funct: %2x flags: 95.4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9050 10b5=regs.h.ah;
if Tany_{050 —10b5==0)
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: %2x Subsystem ID/VID: %8x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys id vid=regs.x.ecx;
regs.hTahl:Ox0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9050 Read PCI base address. OK if 0: qs2x base addr: %8x flags: %
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id_vid, try next */
}while ((any_ 9050_10b5==0) && (subsys_id_vid!=0x104210b5));

if ((subsys id vid!=0x104210b5) 11 (any 9050_10b5!=0) )
{print! ("SYNCCLOCK with PLX PC19050 not detected on PCI bus \n");
return (0);}
/
oldesthi=oldhi;
II oldestlo=oldlo;
oldhi=thi;
oldlo=tlo;
}
if ((regs.x.ecx&Ox01)!=0) {printf(" IO MAPPED - SHOULD BE MEMORY MAPPED \n");return(0);}
II BASE=regs.x.ecx&Oxfffffffe;
regs.h.ah=0x08;
regs.h.a1=0x00;
regs.w.bx=(BASE»16)&0x0ffff; /*hi 16 bits of phys. addr */
regs.w.cx=BASE&OxOffff; /*lo 16 bits of phys addr */
regs.w.si=0; /* hi 16 bits of region size */
16 bits of region size */
IIint386(0x31,&regs,&reg
BASE=(((long)(regs.w.bx))«16)+(((long)regs.w.cx)&0x0ffff);/* map phys addr into cpu addr space */
printf ("mapped BASE=%08x\n",BASE);
/* IF BOARD IS FOUND, CONTINUE WITH T8IMONO */
I*(volatile unsigned char*)(BASE+Match_MseclUsec100Port)=Oxff; /* prevent match toggle */
*(volatile unsigned char*)(BASE+Match Usec10 UseclPort)=Oxff;
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
Itlo=*(volatile unsigned long*)(BASE+ExtO_SeclO_Usecl_Port+(8*i));
"while (1)
{for (i=0;i<=MAXCHANNEL;i++)
{
II ready=*(volatile unsigned char*)(BASE+ExtO_Ctl_StsPort+(4*i));
*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(4*i))=Trigger_Sim_Ext_Time Tag;
if ((ready&Ox0f)!=1)
printf("Ready flag error: Ext%02x_Ctl_Sts_Port low nibble is %02x after sim evt should
,i,ready&OxOf);
II tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i));
thi=*(volatile unsigned long*)(BASE+Ext0—Yearl—Minl Port+(8*i));
EOready=*(volatile unsigned char*)(BASE+ExCtliSts15ort+(4*i));
if ((ready&Ox0f)!=0)
II printf("Ready flag error: Ext%02x_Ctl_Sts_Port is Ps-02x after sim evt should be 0
,i,ready);
if ( (thi<oldhi) ii ((thi==oldhi) && (tlo<=oldlo) ) )
{printf ("%8x %8x old%8x %8x oldest%8x %8x ch#%01x"
II ,thi,t1o,oldhi,oldlo,oldesthi,oldestlo,i);
if ( thi > oldhi )
charcnt=0;}
{for (1=0;j<=charcnt;j++) printf ("*");
for (j=0;j<40;j++) printf("\b*"); /* force buffer flush */
Iprintf ("\r");
charcnt++;
if (charcnt >=60){ printf ("\n"); charcnt=0;}
IIprintf (" completed ");
return (0);

II//T3ITINTR.0 7JUL06 JCK evt 2 to evt 0 spacing changed to 6 msec
//T3ITINTR.0 11JUN05 JCK FOR -TAG3I (NORDEN) CHANGE MAXCHANNEL:7->2 waitcnt max 10000->100000
/* t8itintr.c 12mar03 JCK BCD version CONNECT TSTOUT<7..0> to EXT<7:0> */
/*b37t8iintr.c 26jun02 JCK. CONNECT TSTOUT<7..0> to EXT<7:0> */
Ili*
P8 <21.48,47,45,43,42,41,25> to J3 pin <26,25,24,23,22,21,19,3> */
/* TST<7..0> generate sliding 1 moving LSB to MSB, so EVTn 1 msec after EVTn-1 */
/* t8iintr.c 20jul01 JCK convert -TAG8 to -TAG8I */
/* t8intr.c 2apr99 JCK tests pci-sync32-tag8 intr generation capability */
II/* connect all ext time tag inputs hi,lo, or to mat to prevent unwanted tags */
/* THIS DEMO CODE MAY HAVE PROBLEMS WORKING WITH IRQ LEVELS 3 or 5 */
typedef unsigned char byte;
#include "t8iregs.h" /* offsets for PCI-SYNCCLOCK regs + flag definitions */
#include "picdef.h" /* addresses for host x86 interrupt ctlrs & vectors */
include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
rinclude <ctype.h>
#include <dos.h>
#include <conio.h>
#include <i86.h>
union REGS regs;
IIunsigned long intcount=0,subsys id_vid;
int BASE,instance=0,any 9050 1()E5,any_9030_10b5;
void interrupt pc intTvoidT;
void setvects(voia);
IIvoid resvects(void);
void i_enable(void);
void i disable(void);
void ( interrupt far *oldvec)()=0;
lint bin (int valueYi
volatile long int c;
volatile char readlMR;
volatile unsigned long int busec,oldbusec,oldthi,oldtlo,t1o,thi,waitcnt;
int xnsec100,1,j,ready70,charcnt,MAXCHANNEL=2,error=0,expectedchannel;
IIint errcnt=0;errchan[10000],intflag=0,passcount=0;
unsigned char Extsts(64];
char IMRMASK,IMRENB[16]={0xff,Oxff,Oxff,Oxff,Oxff,Oxff,Oxff,Oxff,
Oxfe,Oxfd,Oxfb,0xf7,0xef,0xff,Oxff,0x7f};
char VECTOR,IRQVEC[16]={0,0,0,0,0,0,0,0,0x70,0x0A,0x72,0x73,0x74,0,0,0x77};
'rain()
{/* USE PCI BIOS CALLS TO DETERMINE MEM BASE ADDRESS */
do {
regs.h.ah=0x0b1;
regs.h.a1=0x02;
regs.w.cx=0x9030;
regs.w.dx=0x10b5;/* query if device id 9030/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9030/10b5 present if 0: %2x bus#: 962x dev/funct: %2x flags: %4x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9030 10b5=regs.h.ah;
if Tany g030 10b5==0)
—{
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: 962x Subsystem ID/VID: %8x flags: 964x \
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsys_id_vid=regs.x.ecx;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9030 Read PCI base address. OK if 0: %2x base addr: *8x flags: %4x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys_id_vid, try next */
}while} ((any 9030 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id via!=0x104210b5) (any_9030 10b5!=0) )
{print!. ("SYNCCLOCK with PLX PCI9030not detected on PCI bus\n");
instance.();
do
{
regs.h.ah=0x0b1;

II/
printf (" Ext evt 0-2 external event inputs have been detected \n");
setvects();
ienable();
II while (errcnt<20)
{
intcount=0;
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
{tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i));I
II /* while waiting for event 7 clear evt 0..6 ready status */—
if (MAXCHANNEL>0)
do
{for (i=0;i<=MAXCHANNEL-1;i++) tlo=*(volatile unsigned IIlong*)(BASE+ExtOSeclO_Usecl Por
/* of event 7 and init oldbusec */ _
oldtlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(MAXCHANNEL*8));
oldthi=*(volatile unsigned long*)(BASE+Ext0—YearliMinlPort +(MAXCHANNEL*8));
IIoldbusec=bin((oldthi )&0x0ff)*60000000 —
regs.h.a1=0x02;
regs.w.cx=0x9050;
regs.w.dx=0x10b5;/* query if device id 9050/vendor id 10b5 is present */
regs.w.si=instance; /* search for 0th, 1st etc. */
int386(0x1a,&regs,&regs);
printf("9050/10b5 present if 0: 962x bus#: %2x dev/funct: %2x flags: 964x \n",
regs.h.ah,regs.h.bh,regs.h.bl,regs.w.cflag);
any 9050 10b5=regs.h.ah;
if Tany_-9-050 10b5==0)
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x2c; /* query Subsystem ID/ Subsystem Vendor ID*/
int386(0x1a,&regs,&regs);
printf("Read Subsystem id/vendor id. OK if 0: %.2x Subsystem ID/VID: 968x
regs.h.ah,regs.x.ecx,regs.w.cflag);
subsysid_vid=regs.x.ecx;
regs.h._ah=0x0b1;
regs.h.a1=0x0a;
regs.w.di=0x18; /* query local address space 0 */
int386(0x1a,&regs,&regs);
printf("9050 Read PCI base address. OK if 0: 962x base addr: 96-8x flags: %
regs.h.ah,regs.x.ecx,regs.w.cflag);
instance++; /* if wrong subsys id vid, try next */
}while ((any 9050 10b5==0) && (subsys id vid!=0x104210b5));
if ((subsys id vid!=0x104210b5) II (any 9050 lbb5!=0) )
{printf ("SYNCCLOCK with PLX PC19050—not detected on PCI bus \n");
return (0);}
}
IIif ((regs.x.ecx&0x01)!=0) {printf(" IO MAPPED - SHOULD BE MEMORY MAPPED \n");return(0);}
BASE=regs.x.ecx&Oxfffffffe;
regs.h.ah=0x0b1;
regs.h.a1=0x0a;
IIregs.w.di=0x3c; /* query latency,grant,interrupt pin,interrupt line */
int386(0x1a,&regs,&regs);
printf("Read PCI config reg 3C. OK if 0: 9602x config reg3c: %08x flags: %04x \n",
regs.h.ah,regs.x.ecx,regs.w.cflag);
IMRMASK=IMRENB[regs.x.ecx&Ox0f];
IIVECTOR=IRQVEC[regs.x.ecx&Ox0f];
printf ("IRQLINE: 9602x IMRMASK: W02x IRQVEC[IRQLEVEL]: %02x \n",
regs.x.ecx&Ox0f,IMRMASK, IRQVEC[regs.x.ecx&Ox0f]);
regs.h.ah=0x08;
regs.h.a1=0x00;
regs.w.bx=(BASE»16)&0x0ffff; /*hi 16 bits of phys. addr */
regs.w.cx=BASE&OxOffff; /*lo 16 bits of phys addr */
regs.w.si=0; /* hi 16 bits of region size */
regs.w.di=0x20; /* lo 16 bits of region size */
IIint386(0x31,&regs,&regs); /* map phys addr into cpu addr space */
BASE=(((long)(regs.w.bx))«16)+(((long)regs.w.cx)&0x0ffff);
printf ("mapped BASE=9608x\n",BASE);
*(volatile unsigned char*)(BASE+ControlPort)=0; /* disable hb,ramfifo,mat,cmd rd
II*(volatile unsigned char*)(BASE+Match_Usec10 UseclPort)=0x00 ;
*(volatile unsigned char*)(BASE+Match_Msecl_Usec100_Port)=0x10 ; // 100pps pulse on norden2 will
sleep(1);
// POLL all MAXCHANNEL+1 event inputs to make sure they are occuring
for (i=0;i<=MAXCHANNEL;i++) /* clear ext evt ready for all 8 ext events*/
{*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(j*4))=0;
printf (" check channel Wd for event input present\n",i);
tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 Usecl Port+(8*i)); // clear Ext Ready
while ((*(volatile unsigned char*)(BASE+ExtO_Cfl_Sts:Port+(i*4)) & Ext_Ready)==0) {;}

+bin((oldtlo»24)&0x0ff)*1000000
+bin((oldtlo»16)&0x0ff)*10000
+bin((oldtlo»8 )&0x0ff)*100
11 +bin((oldtlo )&0x0ff)*1;
for (i=0;i<=MAXCHANNEL;i++) tlo=*(volatile unsigned long*)(BASE+ExtO_SeclO_Usecl_Port+(8*i));
for (j=0;j<=MAXCHANNEL;j++)
if ( (*(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(j*4))&ExtReady)!=0 )
if (error) *(volatile unsigned cfiar*T(BASE+Ext0 Ctl_Sts Port+(j*4)));error=1;1
Initial Ext%Olx Ctl Sts Port= %02X should be 00 \n",j,
II
readlMR = inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
outp(IMR, readlMR)
IIwhile ( (((intcount+1)%10000)!=0) && (errcnt<20))
expectedchannel=intcount%(MAXCHANNEL+1);
for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+ExtO_Ctl_Sts Port+(j*4))=Ext_Intr_
waitcnt=0;
do {readlMR = inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
outp(IMR, readlMR)
waitcnt++;} while ((waitcnt<100000) & (intflag==0));
intflag=0;
/* && ( (*(volatile unsigned char*)(BASE+Ext0 Ctl_Sts_Port+(expectedchannel*4)
&& ( (Extsts[expectedchannel]&Ext Ready)==0)
); */
if (waitcnt>=100000)
{printf(" Ext%Olx Ctl Sts Port= %02x should be 01 \n",intcount%8,Extsts[expectedchannel]);
return(0);1
for (j=0;j<=MAXCHANNEL;j++)
{
if ( (j!=expectedchannel) && ((Extsts[j]&Ext_Ready)!=0) )errchan[errcnt++]=j;
Extsts[j]=0;
/
busec=bin((thi )&0x0ff)*60000000
+bin((tlo»24)&0x0ff)*1000000
+bin((tlo»16)&0x0ff)*10000
+bin((tlo»8 )&0x0ff)*100
+bin((tlo )&0x0ff)*1;
if
((expectedchannel!=0) && ( ( (busec-oldbusec)>1001) 11 ( (busec-oldbusec) <999 ) ) )
1
((expectedchannel==0) && ( ( (busec-oldbusec)>6001) 11 ( (busec-oldbusec)<5999 ) ))
)
{
printf ("tlo=%081x oldtlo=%08x delta:%d intcount:%d \n",t1o,oldtlo,busec-oldbusec,intcoun
return(0);
/
oldtlo=tlo;
oldbusec=busec;
IIintcount++;
for/ (i=0;i<=MAXCHANNEL;i++) *(volatile unsigned char*)(BASE+Ext0 Ctl Sts Port+(i*4))=0; /* disab
printf ("intcount=%lu errcnt=%d passcount=%d \n",intcount,errcnt,passcount);
II passcount++;
if (errcnt!=0)
{
for (i=0;i<errcnt;i++) printf("%01x ",errchan[i]);
Trintf ("\n");
for (i=0;i<1000000;i++) j=*(volatile unsigned char*)(BASE+ExtO_Ctl_Sts_Port); /* delay for print
II
resvects(); /* example doesn't call resvects & i disable */
Ili disable();
urn(0); /* but user code should call them */—
}
et/* this is the actual interrupt handler code.
It is entered via a VECTORED interrupt.
IIWhen the ISA-SYNCCLOCK asserts the configured IRQ signal ,
the bus IRQ signal drives a pin on a 8259 priority interrupt controller on
the host CPU board.
II(Actually, the priority interrupt controller is probably embedded inside a
big LSI glue chip - but it still looks like an 8259 to the programmer and
the bus).
The 8259 then in turn - if the interrupt input level is enabled -
IIwill try to interrupt the host x86 processor. When the x86 accepts the
interrupt the 8259 will supply an interrupt vector (VEC9 in this example)
The x86 will then pick up a FAR pointer from the interrupt vector location
and use it as the address for entering the interrupt routine. */

"void interrupt far pc_int(void) /* Handle external event interrupts */
int—j,discard;
I/* —disable(); */ /* causes compiler to EMIT x86 "CLI" op code */ —
intflag=1; /* notify bkgnd program that pci-sync32 ext intr occured */
for (j=0;j<=MAXCHANNEL;j++) Extsts[j]=*(volatile unsigned char*)(BASE+ExtOCtl Sts Port+(j*4
tlo=*(volatile unsigned long*)(BASE+Ext0 Sec10 UseclPort+(8*expectedchannel));
thi=*(volatile unsigned long*)(BASE+Ext0 Yearl Minl_Port +(8*expectedchannel));
II for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+ExtO_Ctl Sts Port+(j*4))=0; /* d
for (j=0;j<=MAXCHANNEL;j++)
discard=*(volatile unsigned long*)(BASE+ExtOSeclO_Usecl Port+(8*j)); /* read selected
outp(ICR, EOI); /* Signal end of hardware interrupt */
outp(ICRO 7, EOI); /* Signal end of hardware interrupt */
III enable(); /* causes compiler to EMIT x86 "STI" op code */
void setvects() /* Change intr vector to point to PC-SYNCCLOCK interrrupt code */
{if ( !oldvec) {
II / oldvec = dos getvect(VECTOR); /* save old vector */
dos setvct(VECTOR, pc int); /* set new vector */
/
"void resvects(void) /* Uninstall our vectors before exiting the program */
Iif (oldvec) _dossetvect(VECTOR, oldvec);
void i enable() /* Enable PC-SYNCCLOCK interrupts */
III _disable(); /* causes compiler to EMIT x86 "CLI" op code */
c= inp(IMR) & IMRMASK; /* mask bit of "0" enables interrupt */
II /* outp(IMR, c); */
enable(); /* causes compiler to EMIT x86 "STI" op code */
}
void i disable(void) /* Turn off PCI-SYNCCLOCK interrupts */
{int c;
disable(); /* causes compiler to EMIT x86 "CLI" op code */
c= inp(IMR) I -IMRMASK; /* set mask bit to "1" to disable */
outp(IMR, c);
for (j=0;j<=MAXCHANNEL;j++) *(volatile unsigned char*)(BASE+Ext0 Ctl_Sts Port+(j*4))=0;
enable(); /* causes compiler to EMIT x86 "STI" op code */
int bin (int value)
II{return (((((value&Ox0f0)/16)*10) + (value&Ox0f))&0x0ff );I
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