Bridgetek FT900 User manual

Use of Bridgetek devices in life support and/or safety applications is entirely at the user’s risk, and
the user agrees to defend, indemnify and hold Bridgetek harmless from any and all damages,
claims, suits or expense resulting from such use.
Bridgetek Pte Ltd (BRT Chip)
1 Tai Seng Avenue, Tower A #03-05 Singapore 536464
Tel: [phone]
Web Site: http://www.brtchip.com
Copyright © Bridgetek Pte Ltd
Application Note
AN_324
FT900 User Manual
Version 1.3
Issue Date: 29-08-2023
This document provides details about the peripherals of the FT900 as well as
the general system registers.

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Table of Contents
1 Introduction.............................................................. 14
2 FT900 System Architecture ....................................... 15
2.1 Architecture Overview ........................................................15
2.2 Memory Organization ..........................................................16
2.3 FT900 Boot Control .............................................................16
2.4 Debugging Support .............................................................17
3 Register Map ............................................................. 18
4 Notations .................................................................. 19
5 General System Registers ......................................... 20
5.1 Register Summary...............................................................20
5.2 Register Details...................................................................22
5.2.1 CHIPID - Chip ID Register (address offset: 0x00)................................................... 22
5.2.2 EFCFG - Chip Configuration Register (address offset: 0x04) .................................... 22
5.2.3 CLKCFG - Clock Configuration Register (address offset: 0x08) ................................. 23
5.2.4 PMCFG - Power Management Register (address offset: 0x0C) .................................. 24
5.2.5 PTSTNSET - Test & Set Register (address offset: 0x10) .......................................... 25
5.2.6 PTSTNSETR - Test & Set Shadow Register (address offset: 0x14) ............................ 25
5.2.7 MSC0CFG - Miscellaneous Configuration Register (address offset: 0x18)................... 26
5.2.8 GPIO Pin Configuration Registers (address offset: 0x1C –0x5F) .............................. 28
5.2.9 GPIO Configuration Registers (address offset: 0x60 –0x83) ................................... 32
5.2.10 GPIO Value Registers (address offset: 0x84 –0x8F) ............................................. 35
5.2.11 GPIO Interrupt Enable Registers (address offset: 0x90 –0x9B) ............................. 35
5.2.12 Interrupt Pending Registers (address offset: 0x9C –0xA7).................................... 36
5.2.13 ETH_PHY_CFG - Ethernet PHY Miscellaneous Configuration Register (address offset:
0xA8) ....................................................................................................................... 36
5.2.14 ETH_PHY_ID - Ethernet PHY ID Register (address offset: 0xAC)............................. 37
5.2.15 DAC_ADC_CONF - ADC/DAC Configuration/Status Register (address offset: 0xB0) ... 37
5.2.16 DAC_ADC_CNT - ADC/DAC Count Register (address offset: 0xB4).......................... 38
5.2.17 DAC_ADC_DATA - ADC/DAC Data Register (address offset: 0xB8) ......................... 39
6 Interrupt Controller .................................................. 40
6.1 Register Summary...............................................................40

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6.2 Register Details...................................................................41
6.2.1 IRQ00-03 Assignment Register (address offset: 0x00)............................................ 41
6.2.2 IRQ04-07 Assignment Register (address offset: 0x04)............................................ 41
6.2.3 IRQ08-11 Assignment Register (address offset: 0x08)............................................ 41
6.2.4 IRQ12-15 Assignment Register (address offset: 0x0C) ........................................... 42
6.2.5 IRQ16-19 Assignment Register (address offset: 0x10)............................................ 42
6.2.6 IRQ20-23 Assignment Register (address offset: 0x14)............................................ 42
6.2.7 IRQ24-27 Assignment Register (address offset: 0x18)............................................ 42
6.2.8 IRQ28-31 Assignment Register (address offset: 0x1C) ........................................... 43
6.2.9 IRQ Control Register (address offset: 0x20) .......................................................... 43
7 EFUSE ....................................................................... 44
7.1 Introduction........................................................................44
7.2 EFUSE Operation .................................................................44
7.3 EFUSE bits...........................................................................44
8 USB Host................................................................... 46
8.1 Register Summary...............................................................46
8.2 EHCI Operational Registers.................................................47
8.2.1 HC Capability Register (address offset: 0x00)........................................................ 47
8.2.2 HCSPARAMS –HC Structural Parameters (address offset: 0x04).............................. 47
8.2.3 HCCPARAMS –HC Capability Parameters (address offset: 0x08) .............................. 47
8.2.4 USBCMD –HC USB Command Register (address offset: 0x10) ................................ 48
8.2.5 USBSTS –HC USB Status Register (address offset: 0x14)....................................... 49
8.2.6 USBINTR –HC USB Interrupt Enable Register (address offset: 0x18) ....................... 50
8.2.7 FRINDEX –HC Frame Index Register (address offset: 0x1C) ................................... 51
8.2.8 PERIODICLISTBASE –HC Periodic Frame List Base Address Register (address offset:
0x24) ....................................................................................................................... 51
8.2.9 ASYNCLISTADDR –HC Current Asynchronous List Address Register (address offset:
0x28) ....................................................................................................................... 51
8.2.10 PORTSC –HC Port Status and Control Register (address offset: 0x30) .................... 52
8.3 Configuration Registers ......................................................53
8.3.1 EOF Time & Asynchronous Schedule Sleep Timer Register (address offset: 0x34) ...... 53
8.3.2 Bus Monitor Control / Status Register (address offset: 0x40)................................... 55
8.3.3 HPROT –Master Protection Information Setting Register (address offset: 0x78) ........ 55
8.4 USB Host Testing Registers.................................................56

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8.4.1 Vendor Specific IO Control Register (address offset: 0x54) ..................................... 56
8.4.2 Vendor Specific Status Register (address offset: 0x58) ........................................... 56
8.4.3 Test Register (address offset: 0x50)..................................................................... 56
8.4.4 HC_RSRV1 - Reserved 1 Register (address offset: 0x70) ........................................ 57
8.4.5 HC_RSRV2 - Reserved 2 Register (address offset: 0x74) ........................................ 57
9 USB Peripheral .......................................................... 58
9.1 Register Summary...............................................................58
9.2 Initialization Registers........................................................60
9.2.1 DC_ADDRESS_ENABLE –Address Register (address offset: 0x18) ........................... 60
9.2.2 DC_MODE –Mode Register (address offset: 0x10) ................................................. 60
9.2.3 DC_INT_ENABLE –Interrupt Enable Register (address offset: 0x08) ........................ 61
9.2.4 DC_EP_INT_ENABLE –Endpoints Interrupt Enable Register (address offset: 0x0C) .... 61
9.3 Control Endpoint Data Flow Registers .................................61
9.3.1 DC_EP0_CONTROL –Endpoint 0 Control Register (address offset: 0x1C) .................. 61
9.3.2 DC_EP0_STATUS –Endpoint 0 Status Register (address offset: 0x20)...................... 62
9.3.3 DC_EP0_BUFFER_LENGTH –Endpoint 0 Buffer Length Register (address offset: 0x24) 62
9.3.4 DC_EP0_BUFFER –Endpoint 0 Buffer Register (address offset: 0x28)....................... 63
9.4 Other Endpoint Data Flow Registers....................................63
9.4.1 DC_EP(x)_CONTROL –Endpoint Control Registers (address offset:
0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C) ..................................................................... 63
9.4.2 DC_EP(x)_STATUS –Endpoint Status Registers (address offset:
0x30/0x40/0x50/0x60/0x70/0x80/0x90) ...................................................................... 64
9.4.3 DC_EP(x)_BUFFER_LENGTH_LSB –Endpoint Buffer Length LSB Registers (address
offset: 0x34/0x44/0x54/0x64/0x74/0x84/0x94) ............................................................ 65
9.4.4 DC_EP(x)_BUFFER_LENGTH_MSB –Endpoint Buffer Length MSB Registers (address
offset: 0x35/0x45/0x55/0x65/0x75/0x85/0x95) ............................................................ 65
9.4.5 DC_EP(x)_BUFFER –Endpoint Buffer Registers (address offset:
0x38/0x48/0x58/0x68/0x78/0x88/0x98) ...................................................................... 65
9.5 General Registers................................................................66
9.5.1 DC_INT_STATUS –Interrupt Status Register (address offset: 0x00) ........................ 66
9.5.2 DC_EP_INT_STATUS –Endpoints Interrupt Status Register (address offset: 0x04)..... 66
9.5.3 DC_FRAME_NUMBER_LSB –Frame Number LSB Register (address offset: 0x14) ....... 66
9.5.4 DC_FRAME_NUMBER_MSB –Frame Number MSB Register (address offset: 0x15)...... 66
10 Ethernet.................................................................. 67
10.1 Register Summary.............................................................67

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10.2 Register Details.................................................................68
10.2.1 ETH_INT_STATUS –Interrupt Status Register (address offset: 0x0) ....................... 68
10.2.2 ETH_INT_ENABLE –Interrupt Enable Register (address offset: 0x1)....................... 69
10.2.3 ETH_RX_CNTL –Receive Control Register (address offset: 0x02) ........................... 70
10.2.4 ETH_TX_CNTL –Transmit Control Register (address offset: 0x03).......................... 70
10.2.5 ETH_DATA_N0 –Data Register (octet n) (address offset: 0x04)............................. 71
10.2.6 ETH_DATA_N1 –Data Register (octet n+1) (address offset: 0x05)......................... 71
10.2.7 ETH_DATA_N2 –Data Register (octet n+2) (address offset: 0x06)......................... 71
10.2.8 ETH_DATA_N3 –Data Register (octet n+3) (address offset: 0x07)......................... 71
10.2.9 ETH_ADDR_1 –Address Register (octet 1) (address offset: 0x08).......................... 71
10.2.10 ETH_ADDR_2 –Address Register (octet 2) (address offset: 0x09) ........................ 71
10.2.11 ETH_ADDR_3 –Address Register (octet 3) (address offset: 0x0A)........................ 72
10.2.12 ETH_ADDR_4 –Address Register (octet 4) (address offset: 0x0B)........................ 72
10.2.13 ETH_ADDR_5 –Address Register (octet 5) (address offset: 0x0C)........................ 72
10.2.14 ETH_ADDR_6 –Address Register (octet 6) (address offset: 0x0D)........................ 72
10.2.15 ETH_THRESHOLD –Threshold Register (address offset: 0x0E)............................. 72
10.2.16 ETH_MNG_CNTL –Management Control Register (address offset: 0x0F) ............... 72
10.2.17 ETH_MNG_DIV –Management Divider Register (address offset: 0x10) ................. 73
10.2.18 ETH_MNG_ADDR –Management Address Register (address offset: 0x11) ............. 73
10.2.19 ETH_MNG_TX0 –Management Transmit Data 0 Register (address offset: 0x12)..... 73
10.2.20 ETH_MNG_TX1 –Management Transmit Data 1 Register (address offset: 0x13)..... 73
10.2.21 ETH_MNG_RX0 –Management Receive Data 0 Register (address offset: 0x14) ...... 74
10.2.22 ETH_MNG_RX1 –Management Receive Data 1 Register (address offset: 0x15) ...... 74
10.2.23 ETH_NUM_PKT –Number of Packets Register (address offset: 0x16) .................... 74
10.2.24 ETH_TR_REQ –Transmission Request Register (address offset: 0x17) .................. 74
11 CAN Bus Controller.................................................. 75
11.1 Register Summary.............................................................77
11.2 Register Details.................................................................78
11.2.1 CAN_MODE –Mode Register (address offset: 0x00) ............................................. 78
11.2.2 CAN_CMD –Command Register (address offset: 0x01)......................................... 78
11.2.3 CAN_STATUS –Status Register (address offset: 0x02) ......................................... 79
11.2.4 CAN_INT_STATUS –Interrupt Status Register (address offset: 0x03) ..................... 80
11.2.5 CAN_INT_ENABLE –Interrupt Enable Register (address offset: 0x04)..................... 80
11.2.6 CAN_RX_MSG –Receive Message Register (address offset: 0x05).......................... 81
11.2.7 CAN_BUS_TIM_0 –Bus Timing 0 Register (address offset: 0x06)........................... 81

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11.2.8 CAN_BUS_TIM_1 –Bus Timing 1 Register (address offset: 0x07)........................... 81
11.2.9 CAN_TX_BUF - Transmit Buffer Register ............................................................. 82
11.2.10 CAN_RX_BUF - Receive Buffer Register ............................................................. 83
11.2.11 CAN Acceptance Filter ..................................................................................... 84
11.2.12 CAN_ERR_CODE –Error Code Capture Register (address offset: 0x18) ................. 87
11.2.13 CAN_RX_ERR_CNTR –Receive Error Counter Register (address offset: 0x19) ........ 87
11.2.14 CAN_TX_ERR_CNTR –Transmit Error Counter Register (address offset: 0x1A)....... 88
11.2.15 CAN_ARB_LOST_CODE –Arbitration Lost Code Capture Register (address offset:
0x1B) ....................................................................................................................... 88
12 SD Host ................................................................... 89
12.1 Register Summary.............................................................89
12.2 Register Details.................................................................92
12.2.1 SDH_AUTO_CMD23_ARG2 –Auto CMD23 Argument 2 Register (address offset: 0x00)
................................................................................................................................ 92
12.2.2 SDH_BLK_SIZE –Block Size Register (address offset: 0x04) ................................. 92
12.2.3 SDH_BLK_COUNT –Block Count Register (address offset: 0x06) ........................... 92
12.2.4 SDH_ARG_1 –Argument 1 Register (address offset: 0x08) ................................... 92
12.2.5 SDH_TNSFER_MODE –Transfer Mode Register (address offset: 0x0C).................... 93
12.2.6 SDH_CMD –Command Register (address offset: 0x0E) ........................................ 93
12.2.7 SDH_RESPONSE –Response Register (address offset: 0x10-0x1C) ........................ 94
12.2.8 SDH_BUF_DATA –Buffer Data Port Register (address offset: 0x20) ....................... 94
12.2.9 SDH_PRESENT_STATE –Present State Register (address offset: 0x24)................... 95
12.2.10 SDH_HST_CNTL_1 –Host Control 1 Register (address offset: 0x28) ..................... 97
12.2.11 SDH_PWR_CNTL –Power Control Register (address offset: 0x29) ........................ 97
12.2.12 SDH_BLK_GAP_CNTL –Block Gap Control Register (address offset: 0x2A) ............ 97
12.2.13 SDH_CLK_CNTL –Clock Control Register (address offset: 0x2C) .......................... 98
12.2.14 SDH_TIMEOUT_CNTL –Timeout Control Register (address offset: 0x2E) ............... 98
12.2.15 SDH_SW_RST –Software Reset Register (address offset: 0x2F) .......................... 98
12.2.16 SDH_NRML_INT_STATUS –Normal Interrupt Status Register (address offset: 0x30)
................................................................................................................................ 99
12.2.17 SDH_ERR_INT_STATUS –Error Interrupt Status Register (address offset: 0x32) ... 99
12.2.18 SDH_NRML_INT_ENABLE –Normal Interrupt Status Enable Register (address offset:
0x34) ......................................................................................................................100
12.2.19 SDH_ERR_INT_ENABLE –Error Interrupt Status Enable Register (address offset:
0x36) ......................................................................................................................101
12.2.20 SDH_NRML_INT_SGNL_ENABLE –Normal Interrupt Signal Enable Register (address
offset: 0x38) ............................................................................................................101

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12.2.21 SDH_ERR_INT_SGNL_ENABLE –Error Interrupt Signal Enable Register (address
offset: 0x3A) ............................................................................................................102
12.2.22 SDH_AUTO_CMD12_ERR_STATUS –Auto CMD12 Error Status Register (address
offset: 0x3C) ............................................................................................................102
12.2.23 SDH_HOST_CNTL_2 –Host Control 2 Register (address offset: 0x3E)..................103
12.2.24 SDH_CAP_1 –Capabilities Register 1 (address offset: 0x40)...............................103
12.2.25 SDH_CAP_2 –Capabilities Register 2 (address offset: 0x44)...............................104
12.2.26 SDH_RSRV_1 –Reserved 1 Register (address offset: 0x48) ...............................105
12.2.27 SDH_RSRV_2 –Reserved 2 Register (address offset: 0x4C) ...............................105
12.2.28 SDH_FORCE_EVT_CMD_ERR_STATUS –Force Event Register for Auto CMD Error
Status (address offset: 0x50) .....................................................................................105
12.2.29 SDH_FORCE_EVT_ERR_INT_STATUS –Force Event for Error Interrupt Status Register
(address offset: 0x52) ...............................................................................................106
12.2.30 SDH_RSRV_3 –Reserved 3 Register (address offset: 0x54) ...............................106
12.2.31 SDH_RSRV_4 –Reserved 4 Register (address offset: 0x58) ...............................106
12.2.32 SDH_PRST_INIT –Preset value for initialization (address offset: 0x60) ................106
12.2.33 SDH_PRST_DFLT_SPD –Preset value for default speed (address offset: 0x62) .....107
12.2.34 SDH_PRST_HIGH_SPD –Preset value for the high speed (address offset: 0x64) ...107
12.2.35 SDH_PRST_SDR12 –Preset value for SDR12 (address offset: 0x66)....................107
12.2.36 SDH_PRST_SDR25 –Preset value for SDR25 (address offset: 0x68)....................108
12.2.37 SDH_PRST_SDR50 –Preset value for SDR50 (address offset: 0x6A)....................108
12.2.38 SDH_PRST_SDR104 –Preset value for SDR104 (address offset: 0x6C) ................109
12.2.39 SDH_PRST_DDR50 –Preset value for DDR50 (address offset: 0x6E) ...................109
12.2.40 SDH_RSRV_5 –Reserved 5 Register (address offset: 0xFC) ...............................110
12.2.41 SDH_HC_VER –Host Controller Version Register (address offset: 0xFE)...............110
12.2.42 SDH_VNDR_0 –Vendor-defined 0 Register (address offset: 0x100).....................110
12.2.43 SDH_VNDR_1 –Vendor-defined 1 Register (address offset: 0x104).....................111
12.2.44 SDH_VNDR_2 –Vendor-defined 2 Register (address offset: 0x108).....................111
12.2.45 SDH_VNDR_3 –Vendor-defined 3 Register (address offset: 0x10C).....................111
12.2.46 SDH_VNDR_4 –Vendor-defined 4 Register (address offset: 0x110).....................112
12.2.47 SDH_VNDR_5 –Vendor-defined 5 Register (address offset: 0x114).....................112
12.2.48 SDH_VNDR_6 –Vendor-defined 6 Register (address offset: 0x118).....................112
12.2.49 SDH_VNDR_7 –Vendor-defined 7 Register (address offset: 0x11C).....................112
12.2.50 SDH_VNDR_8 –Vendor-defined 8 Register (address offset: 0x120).....................113
12.2.51 SDH_VNDR_9 –Vendor-defined 9 Register (address offset: 0x124).....................113
12.2.52 SDH_RSRV_6 –Reserved 6 Register (address offset: 0x128)..............................113
12.2.53 SDH_HW_ATTR –Hardware Attributes Register (address offset: 0x178)...............113

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12.2.54 SDH_CPR_MOD_CNTL –Cipher Mode Control Register (address offset: 0x180) .....113
12.2.55 SDH_CPR_MOD_STATUS –Cipher Mode Status Register (address offset: 0x184) ..115
12.2.56 SDH_CPR_MOD_STATUS_EN –Cipher Mode Status Enable Register (address offset:
0x188).....................................................................................................................115
12.2.57 SDH_CPR_MOD_SIG_EN –Cipher Mode Signal Enable Register (address offset:
0x18A) ....................................................................................................................115
12.2.58 SDH_IN_DATA_LSB –Input Data LSB Register (address offset: 0x18C) ................115
12.2.59 SDH_IN_DATA_MSB –Input Data MSB Register (address offset: 0x190)...............115
12.2.60 SDH_IN_KEY_LSB –Input Key LSB Register (address offset: 0x194) ...................115
12.2.61 SDH_IN_KEY_MSB –Input Key MSB Register (address offset: 0x198) .................116
12.2.62 SDH_OUT_DATA_LSB –Output Data LSB Register (address offset: 0x19C) ..........116
12.2.63 SDH_OUT_DATA_MSB –Output Data MSB Register (address offset: 0x1A0) .........116
12.2.64 SDH_SCRT_CONS_DATA –Secret Constant Table Data Port (address offset: 0x1A4)
...............................................................................................................................116
13 UART..................................................................... 117
13.1 Register Summary...........................................................118
13.2 UART MODE SELECTION ..................................................120
13.3 STANDARD 550 COMPATIBLE REGISTERS .......................122
13.3.1 UART_RBR - Receiver Buffer Register (address offset: 0x00 and LCR[7] = 0) .........122
13.3.2 UART_THR - Transmitter Holding Register (address offset: 0x00 and LCR[7] = 0) ...122
13.3.3 UART_DIV_LSB - Divisor LSB Register (address offset: 0x00 and LCR[7] = 1) ........122
13.3.4 UART_DIV_MSB - Divisor MSB Register (address offset: 0x01 and LCR[7] = 1) ......122
13.3.5 UART_INT_ENABLE - Interrupt Enable Register (address offset: 0x01) ..................122
13.3.6 UART_INT_STATUS - Interrupt Status Register (address offset: 0x02)...................123
13.3.7 UART_FCR - FIFO Control Register (address offset: 0x02) ....................................124
13.3.8 UART_LCR - Line Control Register (address offset: 0x03) .....................................126
13.3.9 UART_MCR - Modem Control Register (address offset: 0x04)................................127
13.3.10 UART_LSR - Line Status Register (address offset: 0x05) ....................................128
13.3.11 UART_MSR - Modem Status Register (address offset: 0x06) ...............................129
13.3.12 UART_SPR - SPR Register (address offset: 0x07) ..............................................130
13.4 650 COMPATIBLE REGISTERS .........................................130
13.4.1 UART_EFR - Enhanced Feature Register (address offset: 0x02).............................130
13.4.2 UART_XON1 - XON1 Register (address offset: 0x04) ...........................................131
13.4.3 UART_XON2 - XON2 Register (address offset: 0x05) ...........................................131
13.4.4 UART_XOFF1 - XOFF1 Register (address offset: 0x06) .........................................131
13.4.5 UART_XOFF2 - XOFF2 Register (address offset: 0x07) .........................................131

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13.5 950 COMPATIBLE REGISTERS .........................................132
13.5.1 UART_ASR - Additional Status Register (address offset: 0x01)..............................132
13.5.2 UART_RFL - Receiver FIFO Level Register (address offset: 0x03) ..........................132
13.5.3 UART_TFL - Transmitter FIFO Level Register (address offset: 0x04) ......................132
13.5.4 UART_ICR - ICR Register (address offset: 0x05) .................................................133
13.6 INDEXED CONTROL REGISTERS ......................................133
13.6.1 UART_ACR - Additional Control Register (SPR offset: 0x00)..................................135
13.6.2 UART_CPR - Clock Prescaler Register (SPR offset: 0x01)......................................136
13.6.3 UART_TCR - Time Clock Register (SPR offset: 0x02)............................................136
13.6.4 UART_CKS Clock Select Register (SPR offset: 0x03) ............................................136
13.6.5 UART_TTL - Transmitter Trigger Level Register (SPR offset: 0x04) ........................137
13.6.6 UART_RTL - Receiver Trigger Level Register (SPR offset: 0x05) ............................137
13.6.7 UART_FCL - Flow Control Level LSB Register (SPR offset: 0x06) ...........................137
13.6.8 UART_FCH - Flow Control Level Register MSB (SPR offset: 0x07) ..........................137
13.6.9 UART_ID1 - Identification 1 Register (SPR offset: 0x08) ......................................138
13.6.10 UART_ID2 - Identification 2 Register (SPR offset: 0x09).....................................138
13.6.11 UART_ID3 - Identification 3 Register (SPR offset: 0x0A) ....................................138
13.6.12 UART_REV - Revision Register (SPR offset: 0x0B) .............................................138
13.6.13 UART_CSR - Channel Software Reset Register (SPR offset: 0x0C) .......................138
13.6.14 UART_NMR - Nine Bit Mode Register (SPR offset: 0x0D).....................................139
13.6.15 UART_MDM - Modem Disable Mask Register (SPR offset: 0x0E)...........................139
13.6.16 UART_RFC - Readable FCR Register (SPR offset: 0x0F) ......................................140
13.6.17 UART_GDS - Good Data Status Register (SPR offset: 0x10)................................140
13.6.18 UART_RSRV_1 - Reserved 1 Register (SPR offset: 0x11) ....................................140
13.6.19 UART_PIDX - Port Index Register (SPR offset: 0x12) .........................................140
13.6.20 UART_CKA - Clock Alteration Register (SPR offset: 0x13) ...................................140
14 Timers and Watchdog ........................................... 141
14.1 Register Summary...........................................................142
14.2 Register Details...............................................................142
14.2.1 TIMER_CONTROL_0 - Timers Control Register 0 (address offset: 0x00) .................142
14.2.2 TIMER_CONTROL_1 - Timers Control Register 1 (address offset: 0x01) .................143
14.2.3 TIMER_CONTROL_2 - Timers Control Register 2 (address offset: 0x02) .................143
14.2.4 TIMER_CONTROL_3 - Timers Control Register 3 (address offset: 0x03) .................143
14.2.5 TIMER_CONTROL_4 - Timers Control Register 4 (address offset: 0x04) .................144
14.2.6 TIMER_INT - Timers Interrupt Register (address offset: 0x05)..............................144

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14.2.7 TIMER_SELECT - Timers A..D Select Register (address offset: 0x06) .....................144
14.2.8 TIMER_WDG - Watchdog Start Value (address offset: 0x07).................................144
14.2.9 TIMER_WRITE_LS - Timer A..D Start Value 7:0 (address offset: 0x08) ..................145
14.2.10 TIMER_WRITE_MS - Timer A..D Start Value 15:8 (address offset: 0x09) ..............145
14.2.11 TIMER_PRESC_LS - Prescaler Start Value 7:0 (address offset: 0x0A) ...................145
14.2.12 TIMER_PRESC_MS - Prescaler Start Value 15:8 (address offset: 0x0B) ................145
14.2.13 TIMER_READ_LS - Timer A..D Current Value 7:0 (address offset: 0x0C) ..............145
14.2.14 TIMER_READ_MS - Timer A..D Current Value 15:8 (address offset: 0x0D) ...........145
15 I2S........................................................................ 146
15.1 Register Summary...........................................................148
15.2 Register Details...............................................................148
15.2.1 I2SCR - Configuration Register 1 (address offset: 0x00) ......................................148
15.2.2 I2SCR2 - Configuration Register 2 (address offset: 0x02) ....................................149
15.2.3 I2SIRQEN - Interrupt Enable Register (address offset: 0x04)................................150
15.2.4 I2SIRQPEND - Interrupt Pending Register (address offset: 0x06) ..........................150
15.2.5 I2SRWDATA - Transmit / Receive Data Register (address offset: 0x08) .................151
15.2.6 I2SRXCOUNT - RX Count Register (address offset: 0x0C).....................................151
15.2.7 I2STXCOUNT - TX Count Register (address offset: 0x0E) .....................................151
16 SPI Master ............................................................ 152
16.1 Register Summary...........................................................152
16.2 Register Details...............................................................153
16.2.1 SPIM_CNTL –Control Register (address offset: 0x00)..........................................153
16.2.2 SPIM_STATUS –Status Register (address offset: 0x04) .......................................153
16.2.3 SPIM_DATA –Receiver and Transmitter Data Registers (address offset: 0x08) .......154
16.2.4 SPIM_SLV_SEL_CNTL –Slave Select Control Register (address offset: 0x0C) .........154
16.2.5 SPIM_FIFO_CNTL –FIFO Control Register (address offset: 0x10) ..........................154
16.2.6 SPIM_TNSFR_FRMT_CNTL –Transfer Format Control Register (address offset: 0x14)
...............................................................................................................................155
16.2.7 SPIM_ALT_DATA –Alternative SPI Master Data Register (address offset: 0x18)......155
16.2.8 SPIM_RX_FIFO_COUNT –SPI Master RX FIFO Count Register (address offset: 0x1C)
...............................................................................................................................155
17 SPI Slaves............................................................. 156
17.1 Register Summary...........................................................156
17.2 Register Details...............................................................157

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17.2.1 SPIS_CNTL –Control Register (address offset: 0x00) ..........................................157
17.2.2 SPIS_STATUS –Status Register (address offset: 0x04) .......................................157
17.2.3 SPIS_DATA –Receiver and Transmitter Data Registers (address offset: 0x08)........158
17.2.4 SPIS_SLV_SEL_CNTL –Slave Select Control Register (address offset: 0x0C) ..........158
17.2.5 SPIS_FIFO_CNTL –FIFO Control Register (address offset: 0x10) ..........................158
17.2.6 SPIS_TNSFR_FRMT_CNTL –Transfer Format Control Register (address offset: 0x14)
...............................................................................................................................159
17.2.7 SPIS_ALT_DATA –Alternative SPI Slave Data Register (address offset: 0x18) ........159
17.2.8 SPIS_RX_FIFO_COUNT –SPI Slave RX FIFO Count Register (address offset: 0x1C).159
18 I2C Master ............................................................ 160
18.1 Register Summary...........................................................160
18.2 Register Details...............................................................161
18.2.1 I2CM_SLV_ADDR –Slave Address Register (address offset: 0x00) ........................161
18.2.2 I2CM_CNTL –Control Register (address offset: 0x01)..........................................161
18.2.3 I2CM_STATUS –Status Register (address offset: 0x01).......................................162
18.2.4 I2CM_DATA –Receive / Transmit Data Register (address offset: 0x02) .................162
18.2.5 I2CM_TIME_PERIOD –Timer Period Register (address offset: 0x03)......................162
18.2.6 I2CM_HS_TIME_PERIOD –High Speed Timer Period Register (address offset: 0x03)
...............................................................................................................................163
18.2.7 I2CM_FIFO_LEN –FIFO Mode Byte Length (address offset: 0x04) .........................163
18.2.8 I2CM_FIFO_INT_ENABLE –FIFO Mode Interrupt Enable (address offset: 0x05).......163
18.2.9 I2CM_FIFO_INT_PEND –FIFO Mode Interrupt Pending (address offset: 0x06) ........164
18.2.10 I2CM_FIFO_DATA - FIFO Data Register (address offset: 0x07)............................164
18.2.11 I2CM_TRIG - Trigger Register (address offset: 0x08).........................................164
19 I2C Slave .............................................................. 165
19.1 Register Summary...........................................................165
19.2 Register Details...............................................................166
19.2.1 I2CS_OWN_ADDR –Own Address Register (address offset: 0x00) ........................166
19.2.2 I2CS_CNTL –Control Register (address offset: 0x01) ..........................................166
19.2.3 I2CS_STATUS –Status Register (address offset: 0x01) .......................................166
19.2.4 I2CS_DATA –Receive / Transmit Data Register (address offset: 0x02) ..................167
19.2.5 I2CS_FIFO_LEN –FIFO Mode Byte Length (address offset: 0x04) .........................167
19.2.6 I2CS_FIFO_INT_ENABLE –FIFO Mode Interrupt Enable (address offset: 0x05) .......167
19.2.7 I2CS_FIFO_INT_PEND –FIFO Mode Interrupt Pending (address offset: 0x06).........168
19.2.8 I2CS_FIFO_DATA - FIFO Data Register (address offset: 0x07) ..............................168

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19.2.9 I2CS_TRIG - Trigger Register (address offset: 0x08) ...........................................168
20 RTC ....................................................................... 169
20.1 Register Summary...........................................................169
20.2 Register Details...............................................................169
20.2.1 RTC_CCVR - Current Counter Value Register (address offset: 0x00) ......................169
20.2.2 RTC_CMR - Counter Match Register (address offset: 0x04) ..................................169
20.2.3 RTC_CLR - Counter Load Register (address offset: 0x08) .....................................170
20.2.4 RTC_CCR - Counter Control Register (address offset: 0x0C) .................................170
20.2.5 RTC_STAT - Interrupt Status Register (address offset: 0x10) ...............................170
20.2.6 RTC_RSTAT - Interrupt Raw Status Register (address offset: 0x14).......................170
20.2.7 RTC_EOI - End of Interrupt Register (address offset: 0x18) .................................171
20.2.8 RTC_COMP_VERSION - Component Version Register (address offset: 0x1C)...........171
21 PWM...................................................................... 172
21.1 Register Summary...........................................................172
21.2 Register Details...............................................................174
21.2.1 PWM_CTRL0 - PCM Control Register (address offset: 0x00) ..................................174
21.2.2 PWM_CTRL1 - PWM Control Register (address offset: 0x01) .................................174
21.2.3 PWM_PRESCALER - PWM Prescaler Register (address offset: 0x02) .......................175
21.2.4 PWM_CNTL - PWM Counter Register (LSB) (address offset: 0x03) .........................175
21.2.5 PWM_CNTH - PWM Counter Register (MSB) (address offset: 0x04)........................175
21.2.6 PWM_CMP0L - Comparator 0 Value Register (LSB) (address offset: 0x05) ..............175
21.2.7 PWM_CMP0H - Comparator 0 Value Register (MSB) (address offset: 0x06) ............176
21.2.8 PWM_CMP1L - Comparator 1 Value Register (LSB) (address offset: 0x07) ..............176
21.2.9 PWM_CMP1H - Comparator 1 Value Register (MSB) (address offset: 0x08) ............176
21.2.10 PWM_CMP2L - Comparator 2 Value Register (LSB) (address offset: 0x09) ............176
21.2.11 PWM_CMP2H - Comparator 2 Value Register (MSB) (address offset: 0x0A)...........176
21.2.12 PWM_CMP3L - Comparator 3 Value Register (LSB) (address offset: 0x0B) ............176
21.2.13 PWM_CMP3H - Comparator 3 Value Register (MSB) (address offset: 0x0C)...........176
21.2.14 PWM_CMP4L - Comparator 4 Value Register (LSB) (address offset: 0x0D)............177
21.2.15 PWM_CMP4H - Comparator 4 Value Register (MSB) (address offset: 0x0E)...........177
21.2.16 PWM_CMP5L - Comparator 5 Value Register (LSB) (address offset: 0x0F) ............177
21.2.17 PWM_CMP5H - Comparator 5 Value Register (MSB) (address offset: 0x10)...........177
21.2.18 PWM_CMP6L - Comparator 6 Value Register (LSB) (address offset: 0x11) ............177
21.2.19 PWM_CMP6H - Comparator 6 Value Register (MSB) (address offset: 0x12)...........177

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21.2.20 PWM_CMP7L - Comparator 7 Value Register (LSB) (address offset: 0x13) ............177
21.2.21 PWM_CMP7H - Comparator 7 Value Register (MSB) (address offset: 0x14)...........178
21.2.22 PWM_TOGGLE0 - Channel 0 OUT Toggle Comparator Mask Register (address offset:
0x15) ......................................................................................................................178
21.2.23 PWM_TOGGLE1 - Channel 1 OUT Toggle Comparator Mask Register (address offset:
0x16) ......................................................................................................................178
21.2.24 PWM_TOGGLE2 - Channel 2 OUT Toggle Comparator Mask Register (address offset:
0x17) ......................................................................................................................178
21.2.25 PWM_TOGGLE3 - Channel 3 OUT Toggle Comparator Mask Register (address offset:
0x18) ......................................................................................................................178
21.2.26 PWM_TOGGLE4 - Channel 4 OUT Toggle Comparator Mask Register (address offset:
0x19) ......................................................................................................................178
21.2.27 PWM_TOGGLE5 - Channel 5 OUT Toggle Comparator Mask Register (address offset:
0x1A) ......................................................................................................................179
21.2.28 PWM_TOGGLE6 - Channel 6 OUT Toggle Comparator Mask Register (address offset:
0x1B) ......................................................................................................................179
21.2.29 PWM_TOGGLE7 - Channel 7 OUT Toggle Comparator Mask Register (address offset:
0x1C) ......................................................................................................................179
21.2.30 PWM_OUT_CLR_EN - PWM OUT Clear Enable Register (address offset: 0x1D) .......179
21.2.31 PWM_CTRL_BL_CMP8 - Control Block CMP8 Value Register (address offset: 0x1E) 179
21.2.32 PWM_INIT - PWM Initialization Register (address offset: 0x1F) ...........................179
21.2.33 PWM_INTMASK - PWM Interrupt Mask Register (address offset: 0x20).................180
21.2.34 PWM_INTSTATUS - PWM Interrupt Status Register (address offset: 0x21)............180
21.2.35 PWM_SAMPLE_FREQ_H - PWM Data Sampling Frequency High Byte Register (address
offset: 0x22) ............................................................................................................180
21.2.36 PWM_SAMPLE_FREQ_L - PWM Data Sampling Frequency Low Byte Register (address
offset: 0x23) ............................................................................................................181
21.2.37 PCM_VOLUME - PCM Volume Register (address offset: 0x24) ..............................181
21.2.38 PWM_BUFFER - PCM Buffer Register (address offset: 0x3C)................................181
22 Data Capture Interface ......................................... 182
22.1 Register Summary...........................................................182
22.2 Register Details...............................................................182
22.2.1 DCAP_REG1 –Data Capture Interface Register 1 (address offset: 0x00) ................182
22.2.2 DCAP_REG2 –Data Capture Interface Register 2 (address offset: 0x04) ................183
22.2.3 DCAP_REG3 –Data Capture Interface Register 3 (address offset: 0x08) ................183
22.2.4 DCAP_REG4 –Data Capture Interface Register 4 (address offset: 0x0C) ................183
23 Flash Controller..................................................... 184
23.1 Register Summary...........................................................184

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23.2 Register Details...............................................................185
23.2.1 RSADDR0 –Memory Start Address Register (LSB) (address offset: 0x00) ..............185
23.2.2 RSADDR1 –Memory Start Address Register (Byte 1) (address offset: 0x01)...........185
23.2.3 RSADDR2 –Memory Start Address Register (MSB) (address offset: 0x02) .............185
23.2.4 FSADDR0 –Flash Start Address Register (LSB) (address offset: 0x03) ..................186
23.2.5 FSADDR1 –Flash Start Address Register (Byte 1) (address offset: 0x04) ...............186
23.2.6 FSADDR2 –Flash Start Address Register (MSB) (address offset: 0x05)..................186
23.2.7 BLENGTH0 –Data Byte Length Register (LSB) (address offset: 0x06)....................186
23.2.8 BLENGTH1 –Data Byte Length Register (Byte 1) (address offset: 0x07) ................186
23.2.9 BLENGTH2 –Data Byte Length Register (MSB) (address offset: 0x08) ...................186
23.2.10 COMMAND –Command Register (address offset: 0x09) .....................................187
23.2.11 SEMAPHORE –Semaphore Register (address offset: 0x0B).................................187
23.2.12 CONFIG –Configuration Register (address offset: 0x0C) ....................................187
23.2.13 STATUS –Status Register (address offset: 0x0D)..............................................188
23.2.14 CRCL –Flash Content CRC Register (LSB) (address offset: 0x0E) ........................188
23.2.15 CRCH –Flash Content CRC Register (MSB) (address offset: 0x0F) .......................188
23.2.16 CHIPID0 –Chip ID Register (LSB) (address offset: 0x7C)...................................188
23.2.17 CHIPID1 –Chip ID Register (Byte 1) (address offset: 0x7D) ...............................189
23.2.18 CHIPID2 –Chip ID Register (Byte 2) (address offset: 0x7E) ...............................189
23.2.19 CHIPID3 –Chip ID Register (MSB) (address offset: 0x7F) ..................................189
23.2.20 DRWDATA –Data Register (address offset: 0x80) .............................................189
23.3 Flash Controller Commands ............................................189
24 Contact Information.............................................. 194
Appendix A –References ........................................... 195
Document References .............................................................195
Acronyms and Abbreviations...................................................195
Appendix B –List of Tables & Figures ........................ 197
List of Tables...........................................................................197
List of Figures .........................................................................208
Appendix C –Revision History ................................... 209

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1Introduction
FT900 is a programmable System-on-Chip device with a 12132-bit general purpose embedded
microprocessor core and a plethora of connectivity options. It has been developed for high speed,
data bridging tasks. With a parallel data capture interface, 10/100 Base-TX Ethernet interface,
CAN bus, and USB 2.0 Hi-Speed peripheral and host ports, this device offers excellent interconnect
capabilities and blazing computational power. The description of the general system registers, as
well as the register set of various peripheral interfaces, is explained in detail in this document.

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2FT900 System Architecture
2.1 Architecture Overview
The FT900 core contains the 32-bit CPU (FT32), with control logic, flash memory and RAM. The
flash memory size is 256 KB. The RAM consists of 256 KB shadow program memory and 64 KB
data memory. Upon reset, the content of the flash memory is copied into the shadow program
memory for fastest execution. The outside connections for the FT900 core are the memory-
mapped I/O interface, the interrupt interface, synchronous reset and the clock.
The peripherals of the FT900 series include:
•1 high-speed USB host interface, which supports USB Battery Charging Specification Rev
1.2. It can be configured as SDP, CDP or DCP.
•1 high-speed USB device interface, which supports USB Battery Charging Specification Rev
1.2. It can perform BCD mode detection.
•2 programmable UARTs
•SPI master interface
•2 SPI slave interfaces
•7-channel PWM blocks with optional digital filter on channel 0 and 1
•I2C master interface
•I2C slave interface
•I2S master / slave interface
•SD host interface
•2 CAN interfaces
•Ethernet
•RTC
•Watchdog & 4 16-bit general purpose timers
•Debug interface
•7-channel 10-bit 1MS/s ADC
•2-channel 10-bit 1MS/s DAC
•67 multi-purpose GPIOs
The block diagram shown below in Figure 2.1 illustrates the main IP blocks of FT900.
Figure 2.1 - FT900 System Architecture

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2.2 Memory Organization
The first 144 bytes in the Program Memory contains the followings:
•Reset vector
•Watchdog vector
•32 interrupt vectors
•1 non-maskable interrupt vector (reserved for the debugger)
•Program entry point
Address
Function
0x00
Reset vector
0x04
Watchdog vector
0x08
Interrupt vector 0
0x0C
Interrupt vector 1
…
…
0x80
Interrupt vector 30
0x84
Interrupt vector 31
0x88
Interrupt vector 32 (NMI)
0x8C
Program entry point
Table 2.1 - FT900 Program Memory Organization
2.3 FT900 Boot Control
Upon reset, boot control takes control of the memory buses and puts the CPU in a reset state.
It automatically transfers the data from the flash memory to the CPU program memory, starting
from address 0 on both sides. Boot control calculates a CRC check over the entire contents of flash
(256KB) and the result is placed in CRCH and CRCL registers found in the flash control module.
Figure 2.2 - FT900 Boot Control
Inst0[7:0]
Inst0[15:8]
Inst0[23:16]
Inst0[31:24]
Inst1[7:0]
Inst1[15:8]
Inst1[23:16]
Inst1[31:24]
Inst2[7:0]
Inst2[15:8]
Inst2[23:16]
Inst2[31:24]
Flash
Inst0
Inst1
Inst2
Shadow
Program
Memory

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2.4 Debugging Support
Debugging the FT900 series is carried out via the one-wire interface. The debugging support is
implemented in the FT900 bootloader. The protocol used for debugging is the GDB remote protocol
and a port of GDB is available in the Bridgetek FT9XX Toolchain. The GDB serial debug protocol
commands are interpreted by a debug interpreter in the bootloader.
In addition, the debug interpreter:
•saves all machine states
•executes commands received over the debug interface
•restores all machine states and returns
Figure 2.3 - FT900 Debugging Support

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3Register Map
This section lists the I/O map for registers / memory in the device. Please note that some
peripherals are not available on some models in the FT900 series. The details can be found in the
table below. An (X) indicates that the peripheral exists and a minus (-) indicates that the
peripheral is not available. All other peripherals that are not mentioned are available on all models
in the series.
CAN
Ethernet
Camera
SD Host
I2S
FT900Q/FT9
00L
X
X
X
X
X
FT901Q/FT9
01L
-
X
X
X
X
FT902Q/FT9
02L
X
-
X
X
X
FT903Q/FT9
03L
-
-
X
X
X
FT905Q/FT9
05L
X
X
-
-
-
FT906Q/FT9
06L
-
X
-
-
-
FT907Q/FT9
07L
X
-
-
-
-
FT908Q/FT9
08L
-
-
-
-
-
Table 3.1 - Peripheral Availability on FT900 Series Models
The register map of the peripherals is as follows:
Function
Address Base Range
Access Mechanism
General Setup
0x10000
0x100BF
DW, W, B
Interrupt Controller
0x100C0
0x100FF
DW, W, B
USB Host
0x10100
0x1017F
DW, W, B
USB Host RAM
0x11000
0x12FFF
DW, W, B
USB Device
0x10180
0x1021F
B
Ethernet
0x10220
0x1023F
DW, W, B (DW for FIFO)
CAN 0
0x10240
0x1025F
B
CAN 1
0x10260
0x1027F
B
RTC
0x10280
0x1029F
DW
SPI Master
0x102A0
0x102BF
DW
SPI Slave 0
0x102C0
0x102DF
DW
SPI Slave 1
0x102E0
0x102FF
DW
I2C Master
0x10300
0x1030F
B
I2C Slave
0x10310
0x1031F
B
UART 0
0x10320
0x1032F
B
UART 1
0x10330
0x1033F
B
Timers/Watchdog
0x10340
0x1034F
B
I2S (Master/Slave)
0x10350
0x1035F
W
Data Capture
0x10360
0x1036F
DW
PWM
0x103C0
0x103FF
B for registers, W for FIFO
SD Host
0x10400
0x107FF
DW
Flash Controller
0x10800
0x108BF
B
* DW (Double-Word): 32-bit; W (Word): 16-bit; B (Byte): 8-bit
Table 3.2 - Register Map for FT900 Series

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4Notations
These notations are used in the register descriptions:
Terms
Description
Reserved
Do not read/write the location
RO
Read-only
ROC
Read-only / Clear-when-read
RW
Read- and Write-able
RW1C
Read and Write-1-to-clear
RW1S
Read and Write-1-to-set
RWAC
Read- and Write-able with automatic clear
W1S
Write-1-to-set
W1T
Write-1-to-trigger-event
WO
Write-only
Table 4.1 - Notations used in Register Description