Freescale Semiconductor *KE02 Series Instruction manual

MKE02P64M20SF0
KE02 Sub-Family
Supports the following:
MKE02Z16VLC2(R),
MKE02Z32VLC2(R),
MKE02Z64VLC2(R),
MKE02Z16VLD2(R),
MKE02Z32VLD2(R),
MKE02Z64VLD2(R),
MKE02Z32VLH2(R),
MKE02Z64VLH2(R),
MKE02Z32VQH2(R), and
MKE02Z64VQH2(R)
Key features
•Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 20 MHz ARM® Cortex-M0+ core
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 64 KB flash
– Up to 256 B EEPROM
– Up to 4 KB RAM
• Clocks
– Oscillator (OSC) - loop-controlled Pierce
oscillator, crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz
– Internal clock source (ICS) - internal FLL with
internal or external reference, precision
trimming of internal reference allowing 1%
deviation across temperature range of 0 °C to
70 °C and 1.5% deviation across temperature
range of -40 °C to 105 °C, up to 20 MHz
– Internal 1 kHz low-power oscillator (LPO)
• System peripherals
– Power management module (PMC) with three
power modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or
interrupt, selectable trip points
– Watchdog with independent clock source
(WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Bit manipulation engine (BME)
• Security and integrity modules
– 64-bit unique identification (ID) number per chip
• Human-machine interface
– Up to 57 general-purpose input/output (GPIO)
– Two 8-bit keyboard interrupt modules (KBI)
– Interrupt (IRQ)
• Analog modules
– One 16-channel 12-bit SAR ADC, operation in
Stop mode, optional hardware trigger (ADC)
– Two analog comparators containing a 6-bit
DAC and programmable reference input
(ACMP)
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One real-time clock (RTC)
Freescale Semiconductor Document Number MKE02P64M20SF0
Data Sheet: Technical Data Rev 3, 07/2013
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2013 Freescale Semiconductor, Inc.

• Communication interfaces
– Two SPI modules (SPI)
– Three UART modules (UART)
– One I2C module (I2C)
• Package options
– 64-pin QFP/LQFP
– 44-pin LQFP
– 32-pin LQFP
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
2 Freescale Semiconductor, Inc.

Table of Contents
1 Ordering parts...........................................................................4
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3Parameter classification............................................................5
4Ratings......................................................................................6
4.1 Thermal handling ratings...................................................6
4.2 Moisture handling ratings..................................................6
4.3 ESD handling ratings.........................................................6
4.4 Voltage and current operating ratings...............................6
5General.....................................................................................7
5.1 Nonswitching electrical specifications...............................7
5.1.1 DC characteristics.................................................7
5.1.2 Supply current characteristics...............................14
5.1.3 EMC performance.................................................15
5.2 Switching specifications.....................................................16
5.2.1 Control timing........................................................16
5.2.2 FTM module timing...............................................17
5.3 Thermal specifications.......................................................18
5.3.1 Thermal characteristics.........................................18
6 Peripheral operating requirements and behaviors....................19
6.1 Core modules....................................................................19
6.1.1 SWD electricals ....................................................19
6.2 External oscillator (OSC) and ICS characteristics.............20
6.3 NVM specifications............................................................22
6.4 Analog...............................................................................23
6.4.1 ADC characteristics...............................................24
6.4.2 Analog comparator (ACMP) electricals.................26
6.5 Communication interfaces.................................................27
6.5.1 SPI switching specifications..................................27
7 Dimensions...............................................................................30
7.1 Obtaining package dimensions.........................................30
8 Pinout........................................................................................31
8.1 Signal multiplexing and pin assignments...........................31
8.2 Device pin assignment......................................................33
9 Revision history.........................................................................34
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 3

Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: KE02Z.
Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
KE## Kinetis family • KE02
A Key attribute • Z = M0+ core
FFF Program flash memory size • 16 = 16 KB
• 32 = 32 KB
• 64 = 64 KB
R Silicon revision • (Blank) = Main
• A = Revision after main
Table continues on the next page...
1
2
Ordering parts
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
4 Freescale Semiconductor, Inc.

Field Description Values
T Temperature range (°C) • V = –40 to 105
PP Package identifier • LC = 32 LQFP (7 mm x 7 mm)
• LD = 44 LQFP (10 mm x 10 mm)
• QH = 64 QFP (14 mm x 14 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CC Maximum CPU frequency (MHz) • 2 = 20 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MKE02Z64VQH2
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter classifications
P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
Parameter classification
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 5

Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –6000 +6000 V 1
VCDM Electrostatic discharge voltage, charged-device model –500 +500 V
ILAT Latch-up current at ambient temperature of 105°C –100 +100 mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in the following table may
affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this document.
4
Ratings
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
6 Freescale Semiconductor, Inc.

This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Table 2. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Supply voltage –0.3 6.0 V
IDD Maximum current into VDD — 120 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to all
port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
General
Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 3. DC characteristics
Symbol C Descriptions Min Typical1Max Unit
— — Operating voltage — 2.7 — 5.5 V
VOH P Output high
voltage
All I/O pins, standard-
drive strength
5 V, Iload = –
5 mA
VDD – 0.8 — — V
C 3 V, Iload = –
2.5 mA
VDD – 0.8 — — V
P High current drive
pins, high-drive
strength
5 V, Iload = –
20 mA
VDD – 0.8 — — V
C 3 V, Iload = –
10 mA
VDD – 0.8 — — V
Table continues on the next page...
5
5.1
General
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 7

Table 3. DC characteristics (continued)
Symbol C Descriptions Min Typical1Max Unit
IOHT D Output high
current
Max total IOH for all
ports
5 V — — –100 mA
3 V — — –60
VOL P Output low
voltage
All I/O pins, standard-
drive strength
5 V, Iload = 5
mA
— — 0.8 V
C 3 V, Iload =
2.5 mA
— — 0.8 V
P High current drive
pins, high-drive
strength2
5 V, Iload
=20 mA
— — 0.8 V
C 3 V, Iload =
10 mA
— — 0.8 V
IOLT D Output low
current
Max total IOL for all
ports
5 V — — 100 mA
3 V — — 60
VIH P Input high
voltage
All digital inputs VDD>4.5 V 0.70 × VDD — — V
VDD>2.7 V 0.75 × VDD — —
VIL P Input low
voltage
All digital inputs VDD>4.5 V — — 0.30 × VDD V
VDD>2.7 V — — 0.35 × VDD
Vhys C Input
hysteresis
All digital inputs — 0.06 × VDD — — mV
|IIn| P Input leakage
current
All input only pins
(per pin)
VIN = VDD or
VSS
— 0.1 1 µA
|IOZ| C Hi-Z (off-
state) leakage
current
All input/output (per
pin)
VIN = VDD or
VSS
— 0.1 1 µA
|IOZTOT| C Total leakage
combined for
all inputs and
Hi-Z pins
All input only and I/O VIN = VDD or
VSS
— — 2 µA
RPU P Pullup
resistors
All digital inputs,
when enabled
— 30.0 — 50.0 kΩ
IIC D DC injection
current3, 4, 5Single pin limit VIN < VSS, VIN > VDD
-0.2 — 2 mA
Total MCU limit,
includes sum of all
stressed pins
-5 — 25
CIn C Input capacitance, all pins — — — 7 pF
VRAM C RAM retention voltage — 2.0 — — V
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.
3. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD.
4. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large value.
5. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is
very low (which would reduce overall power consumption).
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
8 Freescale Semiconductor, Inc.

Table 4. LVD and POR specification
Symbol C Description Min Typ Max Unit
VPOR D POR re-arm voltage11.5 1.75 2.0 V
VLVDH C Falling low-voltage detect
threshold—high range (LVDV
= 1)2
4.2 4.3 4.4 V
VLVW1H C Falling low-
voltage
warning
threshold—
high range
Level 1 falling
(LVWV = 00)
4.3 4.4 4.5 V
VLVW2H C Level 2 falling
(LVWV = 01)
4.5 4.5 4.6 V
VLVW3H C Level 3 falling
(LVWV = 10)
4.6 4.6 4.7 V
VLVW4H C Level 4 falling
(LVWV = 11)
4.7 4.7 4.8 V
VHYSH C High range low-voltage
detect/warning hysteresis
— 100 — mV
VLVDL C Falling low-voltage detect
threshold—low range (LVDV
= 0)
2.56 2.61 2.66 V
VLVW1L C Falling low-
voltage
warning
threshold—
low range
Level 1 falling
(LVWV = 00)
2.62 2.7 2.78 V
VLVW2L C Level 2 falling
(LVWV = 01)
2.72 2.8 2.88 V
VLVW3L C Level 3 falling
(LVWV = 10)
2.82 2.9 2.98 V
VLVW4L C Level 4 falling
(LVWV = 11)
2.92 3.0 3.08 V
VHYSDL C Low range low-voltage detect
hysteresis
— 40 — mV
VHYSWL C Low range low-voltage
warning hysteresis
— 80 — mV
VBG P Buffered bandgap output 31.14 1.16 1.18 V
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 9

Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
IOH(mA)
VDD-VOH(V)
Figure 1. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
IOH(mA)
VDD-VOH(V)
Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
10 Freescale Semiconductor, Inc.

Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
IOH(mA)
VDD-VOH(V)
Figure 3. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
IOH(mA)
VDD-VOH(V)
Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 11

Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
IOL(mA)
VOL(V)
Figure 5. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
IOL(mA)
VOL(V)
Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
12 Freescale Semiconductor, Inc.

Typical IOL Vs. VOL(high drive strength) (VDD = 5 V)
IOL(mA)
VOL(V)
Figure 7. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)
Typical IOL Vs. VOL(high drive strength) (VDD = 3 V)
IOL(mA)
VOL(V)
Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 13

5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 5. Supply current characteristics
C Parameter Symbol Bus Freq VDD (V) Typical1Max Unit Temp
C Run supply current FEI
mode, all modules clocks
enabled; run from flash
RIDD 20 MHz 5 6.7 — mA –40 to 105 °C
C 10 MHz 4.5 —
1 MHz 1.5 —
C 20 MHz 3 6.6 —
C 10 MHz 4.4 —
1 MHz 1.45 —
C Run supply current FEI
mode, all modules clocks
disabled; run from flash
RIDD 20 MHz 5 5.3 — mA –40 to 105 °C
C 10 MHz 3.7 —
1 MHz 1.5 —
C 20 MHz 3 5.3 —
C 10 MHz 3.7 —
1 MHz 1.4 —
P Run supply current FBE
mode, all modules clocks
enabled; run from RAM
RIDD 20 MHz 5 9 14.8 mA –40 to 105 °C
C 10 MHz 5.2 —
1 MHz 1.45 —
P 20 MHz 3 8.8 11.8
C 10 MHz 5.1 —
1 MHz 1.4 —
P Run supply current FBE
mode, all modules clocks
disabled; run from RAM
RIDD 20 MHz 5 8 12.3 mA –40 to 105 °C
C 10 MHz 4.4 —
1 MHz 1.35 —
P 20 MHz 3 7.8 9.2
C 10 MHz 4.2 —
1 MHz 1.3 —
P Wait mode current FEI
mode, all modules clocks
enabled
WIDD 20 MHz 5 5.5 — mA –40 to 105 °C
C 10 MHz 3.5 —
1 MHz 1.4 —
C 20 MHz 3 5.4 —
10 MHz 3.4 —
1 MHz 1.4 —
P Stop mode supply current
no clocks active (except 1
kHz LPO clock)2, 3
SIDD — 5 2 85 µA –40 to 105 °C
P — 3 1.9 80 –40 to 105 °C
C ADC adder to Stop
ADLPC = 1
— — 5 86 (64-, 44-
pin
packages)
— µA –40 to 105 °C
Table continues on the next page...
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
14 Freescale Semiconductor, Inc.

Table 5. Supply current characteristics (continued)
C Parameter Symbol Bus Freq VDD (V) Typical1Max Unit Temp
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
42 (32-pin
package)
C 3 82 (64-, 44-
pin
packages)
41 (32-pin
package)
—
C LVD adder to stop4— — 5 128 — µA –40 to 105 °C
C 3 124 —
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
3. ACMP adder causes IDD to increase typically by less than 1 µA.
4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must consult
the following Freescale applications notes, available on freescale.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
Nonswitching electrical specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 15

Switching specifications
5.2.1 Control timing
Table 6. Control timing
Num C Rating Symbol Min Typical1Max Unit
1 P Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz
2 P Internal low power oscillator frequency fLPO 0.67 1.0 1.25 KHz
3 D External reset pulse width textrst 1.5 ×
tcyc
— — ns
4 D Reset low drive trstdrv 34 × tcyc — — ns
5 D IRQ pulse width Asynchronous
path2tILIH 100 — — ns
D Synchronous path tIHIL 1.5 × tcyc — — ns
6 D Keyboard interrupt pulse
width
Asynchronous
path2tILIH 100 — — ns
D Synchronous path tIHIL 1.5 × tcyc — — ns
7 C Port rise and fall time -
Normal drive strength
(load = 50 pF)
— tRise — 10.2 — ns
C tFall — 9.5 — ns
C Port rise and fall time -
high drive strength (load =
50 pF)3
— tRise — 5.4 — ns
C tFall — 4.6 — ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.






 
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
tILIH
IRQ/KBIPx
Figure 10. KBIPx timing
5.2
Switching specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
16 Freescale Semiconductor, Inc.

5.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 7. FTM input timing
No. C Function Symbol Min Max Unit
1 D External clock
frequency
fTCLK 0 fBus/4 Hz
2 D External clock
period
tTCLK 4 — tcyc
3 D External clock
high time
tclkh 1.5 — tcyc
4 D External clock
low time
tclkl 1.5 — tcyc
5 D Input capture
pulse width
tICPW 1.5 — tcyc






 
tTCLK
tclkh
tclkl
TCLK
Figure 11. Timer external clock






 
tICPW
FTMCHn
tICPW
FTMCHn
Figure 12. Timer input capture pulse
Switching specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 17

Thermal specifications
5.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 8. Thermal attributes
Board type Symbol Description 64
LQFP
64 QFP 44
LQFP
32
LQFP
Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction
to ambient (natural
convection)
71 61 75 86 °C/W 1, 2
Four-layer (2s2p) RθJA Thermal resistance, junction
to ambient (natural
convection)
53 47 53 57 °C/W 1, 3
Single-layer (1S) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
59 50 62 72 °C/W 1, 3
Four-layer (2s2p) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
46 41 47 51 °C/W 1, 3
— RθJB Thermal resistance, junction
to board
35 32 34 33 °C/W 4
— RθJC Thermal resistance, junction
to case
20 23 20 24 °C/W 5
—ΨJT Thermal characterization
parameter, junction to
package top outside center
(natural convection)
5 8 5 6 °C/W 6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
5.3
Thermal specifications
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
18 Freescale Semiconductor, Inc.

The average chip-junction temperature (TJ) in °C can be obtained from:
TJ= TA + (PD× θJA)
Where:
TA= Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD= Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PDand TJ(if PI/O is neglected) is:
PD= K ÷ (TJ+ 273 °C)
Solving the equations above for K gives:
K = PD× (TA+ 273 °C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be determined by measuring
PD(at equilibrium) for an known TA. Using this value of K, the values of PDand TJcan
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 9. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 5.5 V
J1 SWD_CLK frequency of operation
• Serial wire debug 0 25 MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
20 — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc. 19

Table 9. SWD full voltage range electricals (continued)
Symbol Description Min. Max. Unit
• Serial wire debug
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 13. Serial wire clock input timing
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 14. Serial wire data timing
Peripheral operating requirements and behaviors
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
20 Freescale Semiconductor, Inc.