Broadcom ACPL-355JC User manual

Broadcom ACPL-355JC-62mmSiC-RM100
March 25, 2022
ACPL-355JC
62-mm SiC Module EB1200M62-355JC Evaluation Board
Reference Manual
Version 1.0

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more information, go to www.broadcom.com. All trademarks, trade names, service marks, and logos referenced herein
belong to their respective companies.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does
not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
ACPL-355JC Reference Manual 62-mm SiC Module EB1200M62-355JC Evaluation Board
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Table of Contents
Chapter 1: Introduction ...................................................................................................................... 5
1.1 Design Features ........................................................................................................................................................6
1.2 Target Applications...................................................................................................................................................6
1.3 Warnings....................................................................................................................................................................7
Chapter 2: System Description ......................................................................................................... 8
2.1 Key Specifications ....................................................................................................................................................8
2.2 Functional Block Diagram........................................................................................................................................8
2.3 Pin Assignment .......................................................................................................................................................11
2.3.1 Power Interface...............................................................................................................................................11
2.3.2 Signal Interface ...............................................................................................................................................11
2.4 Mechanical Data ......................................................................................................................................................12
Chapter 3: Circuit Description ......................................................................................................... 13
3.1 Power Management ................................................................................................................................................13
3.2 Gate Driver Circuit ..................................................................................................................................................17
3.2.1 Gate Driver Circuit: Low-Voltage Side ............................................................................................................18
3.2.2 Gate Driver Circuit: High-Voltage Side ...........................................................................................................20
3.2.3 Protection Features.........................................................................................................................................21
3.2.3.1 OC ........................................................................................................................................................21
3.2.3.2 UVLO ....................................................................................................................................................23
3.3 Measurements .........................................................................................................................................................23
3.3.1 Isolated DC Bus Voltage Measurement (Detachable) ....................................................................................23
3.3.2 Example Test Setup for Switching Current Measurement ..............................................................................25
3.4 Connectors ..............................................................................................................................................................26
3.4.1 Power Connectors for the High-Voltage Side .................................................................................................26
3.4.2 VCC +15V Connector ......................................................................................................................................26
3.4.3 User Interface Connector................................................................................................................................27
3.4.4 Current Measurement Interface Connector ....................................................................................................28
3.4.5 ACPL-736J Sigma-Delta Current Sensing Module .........................................................................................29
3.5 Installation of the EB1200M62-355JC....................................................................................................................31
3.6 Evaluation of the EB1200M62-355JC ....................................................................................................................32
Chapter 4: Typical Switching and Over-Current Protection Characteristics .............................. 33
4.1 Typical Switching Waveforms with WAB300M12BM3 .........................................................................................33
4.2 Typical Switching Losses with WAB300M12BM3 ................................................................................................34
4.3 Typical Over-Current Protection Performance with WAB300M12BM3 ..............................................................36
4.4 Typical Switching Waveforms with FF6MR12KM1...............................................................................................37
4.5 Typical Switching Losses with FF6MR12KM1......................................................................................................40
4.6 Typical Over-Current Protection Performance with FF6MR12KM1....................................................................42

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Appendix A: Schematics, Layout, and Bill of Materials................................................................ 43
A.1 Schematics .............................................................................................................................................................43
A.2 Layout .....................................................................................................................................................................47
A.3 Bill of Materials ......................................................................................................................................................52
A.4 Test Points .............................................................................................................................................................54
Appendix B: Disclaimer ................................................................................................................... 55
Revision History ............................................................................................................................... 56
ACPL-355JC-62mmSiC-RM100; Version 1.0; March 25, 2022 ................................................................................... 56

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Chapter 1: Introduction
The evaluation board EB1200M62-355JC features Broadcom’s dual-output isolated gate drive optocouplers ACPL-355JC,
which are used to drive the SiC MOSFET module in an industry-standard 62-mm package. It also features precision optically
isolated amplifiers ACPL-C87B, which are used for DC bus voltage measurement, and a user interface/buffering circuit for
accommodating external output current measurement signals coming from the optically isolated sigma-delta modulator
ACPL-736J. EB1200M62-355JC, shown in Figure 1, has been developed to support Broadcom customers during their first
steps in designing power converter applications with ACPL-355JC drivers. Properties of the board are described in the
following chapters of this document.
Components were selected considering lead-free reflow soldering. The design was tested and verified with basic
measurements described in this document, but the evaluation board is not qualified for the operation in the whole operating
temperature range or lifetime. The board was subjected to functional testing only.
Figure 1: Evaluation Gate Driver Board EB1200M62-355JC
EB1200M62-355JC was originally designed to be used with the SiC MOSFET half-bridge module FF6MR12KM1 and
WAB300M12BM3, in a 62-mm package. With adequate adjustments for over-current (OC) protection and gate resistors, the
EB1200M62-355JC can support modules from different manufacturers in the same packaging, rated up to 1200V and having
the same pin assignment.

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1.1 Design Features
The EB1200M62-355JC includes the following main features:
Two isolated ACPL-355JC gate drive optocouplers with the following features:
– 10A peak output current
– 100-kV/μs common mode rejection
– VIORM = 2262VPK with CTI > 600V
– Over-current protection (or DESAT)
– Soft shutdown during fault
– Two isolated feedback signals, FAULT (for over-current) and UVLO
A single ACPL-C87B optically isolated amplifier for DC bus voltage measurement:
– 0 to 2V nominal input range
– 100-kHz bandwidth
– 3 to 5.5V wide supply range for the output side
– 15-kV/μs common-mode transient immunity
Electrically and mechanically suitable for 62-mm module FF6MR12KM1 and WAB300M12BM3.
With adjustment of the OC protection and gate resistors, the evaluation board supports the following 62-mm SiC
MOSFET modules:
– FF6MR12KM1
– FF3MR12KM1
– FF2MR12KM1
– WAB300M12BM3
– WAB400M12BM3
DC/DC power supply with current-limit protection and thermal shutdown.
Isolated SMPS for gate drivers.
Access to FAULT and UVLO output signals for protection and control development purposes.
Access to PWM input signals.
Access to current measurements via the ACPL-736J sigma-delta current sensing module:
– ±50-mV linear range (±80-mV full scale)
– 10- to 20-MHz external clock input range
– 1-bit, second-order sigma-delta modulator
– 16-bit resolution, no missing codes
– 80-dB typical SNR, 78-dB typical SNDR
– Sensing range of up to 1000A current together with a 0.05-mΩ shunt
1.2 Target Applications
Broadcom ACPL-355JC gate drive optocouplers target the following applications:
Motor drive for industrial automation and robotics
Power supply and battery charger
Renewable energy inverter and storage

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1.3 Warnings
The board operates at high voltages. Special care must be taken to avoid injury or endanger life. While operating the board,
the user must take into consideration following safety precautions:
If the board is powered up, do not touch the board, especially exposed metal parts.
Pay attention to the maximum ratings.
Use of a protection cover made of insulating materials is mandatory.
If the board is used with a power module to drive continuous load, the power module must be mounted on a heatsink.
The board may rise to high temperatures, and any contact with the human body must be avoided.
The board itself does not provide dead-time generation. The recommended minimal dead time is 500 ns.

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Chapter 2: System Description
This chapter gives essential electrical and mechanical specifications for the EB1200M62-355JC evaluation board.
2.1 Key Specifications
Table 1 lists the absolute maximum ratings of the EB1200M62-355JC evaluation board. Note that this table contains only
key parameters. Constraints from the ACPL-355JC, ACPL-C87B, and ACPL-736J data sheets, as well as specification of
other key components, must be considered when the EB1200M62-355JC is used.
2.2 Functional Block Diagram
Figure 2 and Figure 3 show the functional block diagram and the disposition of the functional blocks of the EB1200M62-
355JC gate driver evaluation board. The block diagram shows several different functional blocks:
Power management:
– +15V/+5V DC/DC regulator
– +15V/+10 (adjustable +10 to +12)
– +5V/+5V isolated DC/DC regulator
– +5V to +3.3V LDO
+10V/(+14V, –4V) isolated SMPS with two outputs (one for the high-side driver and one for the low-side driver)
High-side and low-side ACPL-355JC gate drivers with circuitry
Voltage measurements with ACPL-C87B
DC bus supply terminals
User interface connector
5V Vcc power supply connector
ACPL-736J current sensing module interface connector
Power terminals
Table 1: Absolute Maximum Ratings
Parameter
Values
Unit NoteMin. Typ. Max.
DC bus supply voltage — 600 800 V Limited by the DC bus capacitor voltage rating.
MOSFET half-bridge output
current (RMS)
— 270 382 A Limited by the module thermal.
Vcc input voltage 14 15 16 V External DC input power supply for digital circuitry. Limited by
the SMPS range for gate drivers.
PWM logic input level 0 3.3 5 V External PWM inputs for gate drivers.
Fault logic output level 0 — 5 V Logic output signal; refer to the ACPL-355JC data sheet.
UVLO output logic level 0 — 5 V Logic output signal; refer to the ACPL-355JC data sheet.
CLK and DATA output logic
level
0 — 5 V Clock and data logic output signals for current measurement;
refer to the ACPL-736J data sheet.
Voltage measurement 0 — 5 V Single-ended analog output signal.

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Figure 2: Functional Block Diagram of EB1200M62-355JC

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Figure 3: Disposition of the EB1200M62-355JC Functional Blocks. The Isolation Border Is Marked in Red.
According to Figure 3, the marked functional blocks are as follows:
1. J1 – Auxiliary connector input 15V
2. J2 – Signal connector
3. J3 – Voltage level selector 3.3V/5V for current measurement interface
4. J4 – Current measurement interface
5. J5 – Voltage measurement stand-alone supply
6. PWM buffering
7. MCLK and MDATA buffering for ACPL-736J current sensing module
8. Adjustable LDO
9. Switched power supply 5V/3V3
10. Switched power supply 15V/5V
11. High-side SiC driver based on ACPL-355J
12. Isolated SMPS for gate drivers
13. Low-side SiC driver based on ACPL-355J
14. DC bus voltage measurement based on ACPL-C87B. J8/J9 – Terminal to positive/negative DC bus rail for voltage
measurement
15. J6 – Terminal to high-side switch drain connection for OC detection
16. J7 – Terminal to low-side switch drain connection for OC detection

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2.3 Pin Assignment
Pin assignment for all connectors on the EB1200M62-355JC is listed in the following sections.
2.3.1 Power Interface
The J1 power supply connector is used to supply all ICs and supply gate driver voltage, and Table 2 shows its pin
assignment. There are four screw terminals (J6, J7, J8, J9). Terminals J6 and J7 are used for connecting the drain terminals
of the half bridge switches to the OC pin of the gate driver, and terminals J8 and J9 are used for connecting to the high-
voltage DC rails (DC+, DC-) for voltage measurement. Table 3 lists the functions for each of these connectors.
2.3.2 Signal Interface
Table 4 to Table 7 list the pin assignments of connectors J2, J3, J4, and J5.
Table 2: Pin Assignment of Connector J1 (Power Supply Connector)
Pin Label Function
1 +V_SUPPLY Power supply for low-voltage side.
2 GND Ground.
Table 3: Power Connectors J4, J5, J6, and J7
Designator Label Function
J6 DC+ Terminal to the high-side switch drain connection for OC detection.
J7 PHASE Terminal to the low-side switch drain connection for OC detection.
J8 DC+ Terminal to the positive DC bus rail for voltage measurement.
J9 DC- Terminal to the negative DC bus rail for voltage measurement.
Table 4: Pin Assignment of Connector J2 (User Interface Connector)
Pin Label Function Direction
1 VOLTAGE Single-ended DC bus voltage measurement signal. Output
2 GND Ground. Bidirectional
3 GND Ground. Bidirectional
4 MDAT Data signal for sigma-delta current measurement. Output
5 GND Ground. Bidirectional
6 MCLK Clock signal for sigma-delta current measurement. Output
7 GND Ground. Bidirectional
8 GND Ground. Bidirectional
9 FAULT Fault signal for over-current protection of both drivers. Output
10 UVLO UVLO fault signal for both drivers. Output
11 GND Ground. Bidirectional
12 PWM_L PWM signal for low-side driver. Input
13 PWM_H PWM signal for high-side driver. Input
14 GND Ground. Bidirectional

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2.4 Mechanical Data
Table 8 lists the basic mechanical data of the evaluation board.
Table 5: Pin Assignment of Jumper J3 (Power Supply Selection Jumper for Current Measurement)
Pin Label Function Direction
1 +5V Jumper position 1; +5V interface with current measurement. Output
2 +5V/+3V3 Jumper common point for current measurement power supply. Bidirectional
3 +3V3 Jumper position 2; +3.3V interface with current measurement. Output
Table 6: Pin Assignment of Connector J4 (Interface to the ACPL-736J Current Sensing Module)
Pin Label Function Direction
1 +5V +5V power supply fed directly to current measurement. Output
2 +5V/+3V3 Either +5V or +3.3V chosen by setting the jumper on J4. Output
3 MCLK_CSB Clock signal for current measurement. Input
4 MDAT_CSB Data signal for current measurement. Input
5 GND Ground. Bidirectional
Table 7: Pin Assignment of Jumper J5 (External Supply and Output of the Voltage Measurement Circuit)
Pin Label Function Direction
1 GND Ground. Bidirectional
2 VOLTAGE Single-ended DC bus voltage measurement signal. Output
3 +5V +5V external power supply. Bidirectional
Table 8: Mechanical Characteristics of the EB1200M62-355JC Evaluation Board
Description Value
Number of layers 4
PCB copper thickness 70 μm to all layers
PCB insulating material FR4
Board length 134.5 mm
Board width 82.6 mm
Board height 29.4 mm
PCB thickness 1.6 mm

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Chapter 3: Circuit Description
This chapter provides in-depth insight into the EB1200M62-355JC gate driver evaluation board features.
3.1 Power Management
Figure 4 shows the auxiliary power management block diagram of the EB1200M62-355JC. By default, the evaluation board
is supplied from an external +15V source.
Figure 4: Power Management Block Diagram

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Figure 5: +15V/+5V DC/DC Switching Regulator Circuit
EB1200M62-355JC is equipped with a nonisolated switch mode power supply (SMPS), which provides 5V for the ICs on the
low-voltage side. The +15V/+5V power supply is realized with an LM2674 DC-DC switching regulator, as shown in Figure 5.
The +5V output is used to supply the low-voltage side of ACPL-355JC gate drivers and the isolated SMPS controller IC. The
+5V power supply is capable of driving a 500-mA load and supplying all ICs on the board.
The power for the high-voltage side of the gate drivers is realized with the isolated SMPS, which provides two dual outputs
of +14V and –4V.
Since SiC MOSFETs from various manufacturers have different recommended gate voltage levels, the power supply for the
gate driver high-voltage side is designed to be configurable. There are two adjustments that must be done before the board
can be used on a MOSFET with a different part number.
The first parameter to be configured is the input voltage of the isolated SMPS. This is achieved by adjusting the
feedback resistor R49 of the adjustable LDO voltage regulator, shown in Figure 6. The output of the adjustable LDO
LD1086 is calculated as follows:
The minimum value for Vo is limited by the isolated SMPS to 10V. Do not adjust Vo below 10V to avoid unexpected board
behavior.
The second parameter is the Zener diodes D20 and D25 placed in the output stage of the SMPS, which define the
positive gate driver voltage, shown in Figure 7. A diode with a Zener voltage equal to the positive gate voltage level
recommended by the power module manufacturer should be used.
The presented adjustable circuitry enables in-depth evaluation of switching characteristics or benchmarking of SiC modules
in a 62-mm package from different semiconductor manufactures.

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Figure 6: Adjustable LDO +15V/(+10V ... 12V)
Figure 7: Output Stage of the Isolated SMPS

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Figure 8: Isolated SMPS for the Gate Driver Output Stage
Figure 8 shows the isolated SMPS circuitry. The SMPS is based on the IR2085 self-oscillating half-bridge gate driver and
two transformers with a 1:2 ratio. Table 9 shows the recommended power supply configurations for the WAB300M12BM3
and FF6MR12KM1 MOSFET modules. Based on the values shown in table, it is recommended to use the resistor and Zener
diode values that were used in the circuit with the FF6MR12KM1 and WAB300M12BM3 modules, due to small voltage drops
related to switching.
An isolated 5V/5V voltage regulator R1SX-0505-R provides isolated 5V for ACPL-C87B IC, as shown in Figure 9.
The EB1200M62-355JC can be connected to a current sensing module through the FPC 5-pin J4 connector. The J4
connector is provided for the external output current measurement board, which is based on Broadcom’s isolated sigma-
delta modulator ACPL-736J, but different current measurement boards with an equivalent pinout can be used. Because the
low-voltage side of the ACPL-736J supports a power supply of either 5V or 3.3V, the EB1200M62-355JC enables voltage
level selection via jumper J3. For this purpose, the EB1200M62-355JC features the high-performance LDO 5V/3.3V, shown
in Figure 10, which enables alternative powering of the ACPL-736J current sensing module with 3.3V.
Table 9: Power Supply Configurations
Device +V_Q –V_Q R49 D20 and D25
WAB300M12BM3 +14V –4V 820R 16V Zener diode
FF6MR12KM1 +15V –5V 953R 16V Zener diode

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Figure 9: +5V to +5V_ISO Unregulated Isolated DC/DC Converter
Figure 10: +5V/+3V3 LDO
3.2 Gate Driver Circuit
This section deals with the gate driver circuitry on the EB1200M62-355JC. A description of related features and
functionalities is presented in the following subsections. Figure 11 shows the gate drive circuitry.

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Figure 11: ACPL-355JC Gate Driver Circuitry
With a maximum peak output current of 10A, the ACPL-355JC can drive most of the power IGBT/MOSFET switches directly
without an external push-pull stage. This driver contains an LED that is electrically isolated and optically coupled to an
integrated circuit on the gate driver high-voltage side with two power output stages and a CLAMP function for preventing the
parasitic turn-on due to the parasitic Miller current during turn-off transient. Other features encompass under-voltage lockout
(UVLO) and over-current (OC) protection as well as a soft shutdown during an OC fault.
Table 10 provides the recommended gate turn-on/turn-off resistor values for the WAB300M12BM3 and FF6MR12KM1
MOSFET modules.
3.2.1 Gate Driver Circuit: Low-Voltage Side
Figure 12 shows the low-voltage side of the gate drive circuitry, which contains the power supply for ACPL-355JC, the LED
anode and cathode, and safety reporting signals (FAULT and UVLO).
The resistor responsible for the LED forward current setting is split in two, and those resistors are placed on anode pins 6
and 7 and cathode pin 8 to balance the common mode impedances at the LED’s anode and cathode. This helps to equalize
the common mode voltage change. Resistor values are selected because it was recommended in the device data sheet.
Table 10: Recommended Values for Gate Turn-On/Turn-Off Resistors
Device Rg_on Rg_off
WAB300M12BM3 2.95Ω (2x parallel 5.9Ω) 2.95Ω (2x parallel 5.9Ω)
FF6MR12KM1 4.03Ω (2x parallel 8.06Ω) 4.03Ω (2x parallel 8.06Ω)

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Figure 12: Gate Driver Circuit – Low-Voltage Side
While the input LED is directly polarized, and there is no fault, the turn-on command will be transferred to the high-voltage
side and the ACPL-355JC VOUTP pin will go high. The ANODE pin is pulled high via resistor R3. The input signal LED_IN_P
is connected to the CATHODE pin. When the input LED_IN_P signal is low, the LED is directly polarized and the MOSFET
is turned on. If the input signal LED_IN_P is high, the voltage across the LED and the two resistors is low; therefore the LED
is not conducting and the MOSFET is in off state.
External PWM signals that propagate through the user interface connector are buffered, as shown in Figure 13. Because
the buffer features an open drain output, inputs of the buffer are pulled down while outputs of the buffer are pulled high, to
ensure that the MOSFET module is off in case the input PWM signals are in high impedance states.
Figure 13: PWM Buffer

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UVLO and FAULT signals are open drain, so they are pulled up with 10-kΩ resistors and have 330-pF filtering capacitors.
The logic for these signals is inverted, so they are suitable for wired ‘OR’ applications. In this case, FAULT signals from both
drivers are connected in parallel, and the same is done with UVLO signals, so the user is notified if a FAULT or UVLO has
occurred regardless of which MOSFET it has occurred on. UVLO has the highest fault priority followed by FAULT.
3.2.2 Gate Driver Circuit: High-Voltage Side
The secondary side of the gate drive circuitry, shown in Figure 14, includes circuits related to OC and UVLO protection and
a soft shutdown in case of fault.
Figure 14: Gate Driver Circuit – High-Voltage Side
Based on FF6MR12KM1, when the gate driver input is set to high, VOUTP becomes high and +15.5V is supplied to the
MOSFET gate via two 8.06Ω (default value) parallel resistors. When the gate driver input is set to low, the VOUTN pin
becomes active and –5V is supplied to the MOSFET gate via two 8.06Ω (default value) parallel resistors; and when VOUTN
is low, –5V is connected to the MOSFET gate. These voltages are referred to the source of the respective MOSFET. The
switching time is determined by the gate charging and discharging process. Smaller gate resistors lead to higher peak gate
current, which subsequently decreases turn-on and turn-off time, reducing switching losses. However, gate resistors that are
too small may introduce voltage spikes and current oscillations on the MOSFET or can overload the gate driver IC. For the
proper selection of the gate resistors, several criteria must be fulfilled.
First is the limit of the gate peak current. MOSFET internal RGint must be considered when calculating the ideal value for the
gate resistor and the internal minimum turn-on resistance of driver RVOUTP. The equation for the gate resistor calculation is
given in the ACPL-355JC data sheet.