10.1 Introduction................................................................................................................................................ 39
10.2 User FPGA I/O ports................................................................................................................................40
10.3 Local Bus Interface .................................................................................................................................. 43
10.4 Gate and Delay Controller ......................................................................................................................45
General Description........................................................................................................................................................45
Register Description.......................................................................................................................................................46
Example Procedures......................................................................................................................................................47
10.5 Porting V1495 to V2495..........................................................................................................................48
11 Demo Firmware ............................................................................................................49
11.1 Introduction................................................................................................................................................ 49
11.2 Demo Structure ........................................................................................................................................ 49
11.3 Demo Setup..............................................................................................................................................49
11.4 Gate Pattern Demo Description.............................................................................................................50
Introduction......................................................................................................................................................................50
Register Map ....................................................................................................................................................................50
Register Description.......................................................................................................................................................50
11.5 Pattern Recorder Demo Description ..................................................................................................... 53
Introduction......................................................................................................................................................................53
Register Map ....................................................................................................................................................................53
Register Description.......................................................................................................................................................53
11.6 DAC Demo Description...........................................................................................................................55
Introduction......................................................................................................................................................................55
Register Map ....................................................................................................................................................................55
Register Description.......................................................................................................................................................55
11.7 Gate and Delay Demo Description........................................................................................................ 57
Introduction......................................................................................................................................................................57
Register Map ....................................................................................................................................................................57
Register Description.......................................................................................................................................................57
12 Software Development ................................................................................................60
13 CAEN Support...............................................................................................................61
13.1 Returns and Repairs................................................................................................................................61
13.2 Technical Support Service...................................................................................................................... 61
List of Figures
Fig. 2.1: Block diagram......................................................................................................................................................................10
Fig. 3.1: Main components and interconnections...........................................................................................................................11
Fig. 3.2: The UFPGA and GDG interface........................................................................................................................................12
Fig. 4.1: Front panels view................................................................................................................................................................13
Fig. 5.1: On-board internal connectors and LEDs..........................................................................................................................16
Fig. 7.1: V2495 motherboard with mezzanine boards...................................................................................................................22
Fig. 7.2: Multi-pin connector pin assignment..................................................................................................................................23
Fig. 7.3: CAEN A967 Cable Adapter................................................................................................................................................23
Fig. 7.4: Base Address on-board rotary switches ..........................................................................................................................24
Fig. 7.5: User Firmware rotary switch..............................................................................................................................................24
Fig. 7.6: Boot mode jumper for the Main FPGA.............................................................................................................................25
Fig. 8.1: V2495 hardware detection.................................................................................................................................................26
Fig. 8.2: USB driver manual installation: Step1..............................................................................................................................27
Fig. 8.3: USB driver manual installation: Step2..............................................................................................................................27
Fig. 8.4: USB driver manual installation: Step3..............................................................................................................................28
Fig. 8.5: USB driver manual installation: Step4..............................................................................................................................28
Fig. 8.6: USB driver manual installation: Step5..............................................................................................................................29
Fig. 8.7: CAENUpgrader Get Firmware Release menu................................................................................................................30
Fig. 8.8: CAENUpgrader MFPGA Upgrade Firmware menu........................................................................................................31
Fig. 8.9: CAENUpgrader UFPGA flash memory image menu......................................................................................................32
Fig. 8.10: CAENUpgrader UFPGA Upgrade Firmware menu......................................................................................................32
Fig. 8.11: CAEN PLULib Demo application prompt.......................................................................................................................33
Fig. 10.1: Simplified scheme related to Tab. 10.5..........................................................................................................................41
Fig. 10.2: Local bus signals at a write access (x8BADF00D is written on register x1800) ......................................................43
Fig. 10.3: Local bus signal at a read access (x8BADF00D is read from register x1800).........................................................43
Fig. 10.4: Prefetch mechanism.........................................................................................................................................................44
Fig. 10.5: Gate and Delay parameters representation..................................................................................................................45
