Caen DT5495 User manual

CAEN
Tools for Discovery
n
Electronic Instrumentation
User Manual UM6508
DT5495
Desktop Programmable Logic Unit
Rev. 0 - August 2nd, 2018

Purpose of this Manual
This document contains the full hardware and software description of the DT5495 Desktop Programmable Logic Unit.
Change Document Record
Date
Revision
Changes
August 2nd, 2018
00
Initial release
Symbols, Abbreviated Terms and Notation
AM
Address Modifier
ETH
Ethernet Interface
FPGA
Field Programmable Gate Array
GDG
Gate and Delay Generator
LB
Local Bus
LBM
Local Bus Master
LBS
Local Bus Slave
LED
Light Emitting Diode
MFPGA
Main FPGA
SPI
Serial Peripheral Interface
UFPGA
User FPGA
USB
Universal Serial Bus
Reference Documents
[RD1] GD2512 –CAENUpgrader QuickStart Guide
[RD2] A967 Adapter for P50E –068S 68 Pin Connectors
[RD3] UM6510 –CAEN PLULib Library User Manual
All documents can be downloaded at: http://www.caen.it/csite/LibrarySearch.jsp

CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. [phone] Fax [phone]
[email protected]
www.caen.it
© CAEN SpA –2018
Disclaimer
None of the parts of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or
otherwise, without the prior written permission of CAEN SpA.
The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without giving any
notice; for up to date information please visit www.caen.it.
MADE IN ITALY: We stress the fact that all the boards are made in Italy because in this globalized world, where getting
the lowest possible price for products sometimes translates into poor pay and working conditions for the people who
make them, at least you know that who made your board was reasonably paid and worked in a safe environment. (this
obviously applies only to the boards marked "MADE IN ITALY", we cannot attest to the manufacturing process of "third
party" boards).

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
4
Index
Purpose of this Manual .........................................................................................................................................2
Change Document Record...................................................................................................................................2
Symbols, Abbreviated Terms and Notation .......................................................................................................2
Reference Documents...........................................................................................................................................2
Index ........................................................................................................................................4
List of Figures.........................................................................................................................5
List of Tables..........................................................................................................................5
1Introduction.....................................................................................................................7
2Block Diagram ................................................................................................................9
3Main Components and Interconnections..................................................................10
3.1 USB Interface............................................................................................................................................11
3.2 Ethernet Interface.....................................................................................................................................11
3.3 Main FPGA................................................................................................................................................11
3.4 User FPGA................................................................................................................................................11
3.5 Gate and Delay Generator......................................................................................................................11
3.6 Clock Distribution .....................................................................................................................................11
4Front Panel Connectors, LEDs and Labels ..............................................................12
4.1 Front Panel................................................................................................................................................13
4.2 Rear Panel ................................................................................................................................................15
5Technical Specifications.............................................................................................17
6Power Requirements ...................................................................................................19
7Getting Started with DT5495.......................................................................................20
7.1 Shipping Content......................................................................................................................................20
7.2 Mezzanine Boards Installation ............................................................................................................... 21
7.3 Front Panel Connector Cabling.............................................................................................................. 22
7.4 Power-on Configuration Sequence........................................................................................................23
Restore Function.............................................................................................................................................................23
8Communication ............................................................................................................24
8.1 Drivers........................................................................................................................................................24
Direct USB Driver Installation......................................................................................................................................24
8.2 Ethernet Configuration............................................................................................................................. 28
8.3 Web Interface............................................................................................................................................30
8.4 Software Tools.......................................................................................................................................... 31
CAENUpgrader.................................................................................................................................................................31
PLULib Library.................................................................................................................................................................34
9Software Interface........................................................................................................35
9.1 Address Map.............................................................................................................................................35
User FPGA Data Access (0x0000-0x0FFF)................................................................................................................35
User FPGA Register Access (0x1000-0x7FFF).........................................................................................................35
Configuration ROM (0x8100-0x81FF).........................................................................................................................36
Configuration and Status Registers (0x8200-0x83FF)...........................................................................................36
MFPGA Firmware Revision Register..........................................................................................................................37
Software Reset Register................................................................................................................................................37
Scratch Register..............................................................................................................................................................37
Flash Configuration (0x8500-0x8AFF)........................................................................................................................37
Internal Scratch SRAM(0x8C00-0x8FFF)...................................................................................................................37
10 Firmware Development................................................................................................38
10.1 Introduction................................................................................................................................................ 38
10.2 User FPGA I/O ports................................................................................................................................39
10.3 Local Bus Interface .................................................................................................................................. 42
10.4 Gate and Delay Controller ......................................................................................................................44
General Description........................................................................................................................................................44
Register Description.......................................................................................................................................................45
Example Procedures......................................................................................................................................................46
10.5 Porting V1495 to DT5495 .......................................................................................................................47

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
5
11 Demo Firmware ............................................................................................................48
11.1 Introduction................................................................................................................................................ 48
11.2 Demo Structure ........................................................................................................................................ 48
11.3 Demo Setup.............................................................................................................................................. 48
11.4 Gate Pattern Demo Description.............................................................................................................49
Introduction......................................................................................................................................................................49
Register Map ....................................................................................................................................................................49
Register Description.......................................................................................................................................................49
11.5 Pattern Recorder Demo Description .....................................................................................................52
Introduction......................................................................................................................................................................52
Register Map ....................................................................................................................................................................52
Register Description.......................................................................................................................................................52
11.6 DAC Demo Description...........................................................................................................................54
Introduction......................................................................................................................................................................54
Register Map ....................................................................................................................................................................54
Register Description.......................................................................................................................................................54
11.7 Gate and Delay Demo Description........................................................................................................56
Introduction......................................................................................................................................................................56
Register Map ....................................................................................................................................................................56
Register Description.......................................................................................................................................................56
12 Software Development ................................................................................................59
13 CAEN Support...............................................................................................................60
13.1 Returns and Repairs................................................................................................................................60
13.2 Technical Support Service...................................................................................................................... 60
List of Figures
Fig. 2.1: Block diagram........................................................................................................................................................................9
Fig. 3.1: Main components and interconnections...........................................................................................................................10
Fig. 3.2: The UFPGA and GDG interface........................................................................................................................................11
Fig. 4.1: front (top) and rear (down) panel view .............................................................................................................................12
Fig. 7.1: DT5495 motherboard with mezzanine boards ................................................................................................................21
Fig. 7.2: Multi-pin connector pin assignment..................................................................................................................................22
Fig. 7.3: CAEN A967 Cable Adapter................................................................................................................................................22
Fig. 8.1: DT5495 hardware detection...............................................................................................................................................24
Fig. 8.2: USB driver manual installation: Step1..............................................................................................................................25
Fig. 8.3: USB driver manual installation: Step2..............................................................................................................................25
Fig. 8.4: USB driver manual installation: Step3..............................................................................................................................26
Fig. 8.5: USB driver manual installation: Step4..............................................................................................................................26
Fig. 8.6: USB driver manual installation: Step5..............................................................................................................................27
Fig. 8.7: The Network and Sharing Center window .......................................................................................................................28
Fig. 8.8: Properties window of the Ethernet network.....................................................................................................................28
Fig. 8.9: Ethernet Properties window”..............................................................................................................................................29
Fig. 8.10: Properties window of the ”Internet Protocol Version (TPC/IPv4)” ..............................................................................29
Fig. 8.11: Instrument Information page of the DT5495 Web Interface........................................................................................30
Fig. 8.12: Instrument Information page of the DT5495 Web Interface........................................................................................30
Fig. 8.13: CAENUpgrader Get Firmware Release menu..............................................................................................................31
Fig. 8.14: CAENUpgrader MFPGA Upgrade Firmware menu......................................................................................................32
Fig. 8.15: CAENUpgrader UFPGA flash memory image menu ...................................................................................................33
Fig. 8.16: CAENUpgrader UFPGA Upgrade Firmware menu......................................................................................................33
Fig. 8.17: CAEN PLULib Demo application prompt.......................................................................................................................34
Fig. 10.1: CAENComm Demo Java and LabVIEW graphical interface.......................................................................................40
Fig. 10.2: Local bus signals at a write access (x8BADF00D is written on register x1800) ......................................................42
Fig. 10.3: Local bus signal at a read access (x8BADF00D is read from register x1800).........................................................42
Fig. 10.4: Prefetch mechanism.........................................................................................................................................................43
Fig. 10.5: Gate and Delay parameters representation..................................................................................................................44
List of Tables
Tab. 1.1: Comparison table between V1495 and DT5495..............................................................................................................7
Tab. 1.2: Table of models and related items.....................................................................................................................................8
Tab. 5.1: DT5495 specifications table..............................................................................................................................................17

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
6
Tab. 5.2: A395A Mezzanine specifications table............................................................................................................................17
Tab. 5.3: A395B Mezzanine specifications table............................................................................................................................18
Tab. 5.4: A395C Mezzanine specifications table ...........................................................................................................................18
Tab. 5.5: A395D Mezzanine specifications table...........................................................................................................................18
Tab. 5.6: A395E Mezzanine specifications table............................................................................................................................18
Tab. 9.1: DT5495 register address map..........................................................................................................................................35
Tab. 9.2: ROM Address Map of the DT5495 ..................................................................................................................................36
Tab. 9.3: CSR registers .....................................................................................................................................................................36
Tab. 10.1: Clock ports description table..........................................................................................................................................39
Tab. 10.2: Mainboard Robinson-Nugent connector description table.........................................................................................39
Tab. 10.3: LEMO G ports description table.....................................................................................................................................39
Tab. 10.4: Expansion I/O ports description table...........................................................................................................................39
Tab. 10.5: A395D mapping................................................................................................................................................................40
Tab. 10.6: LED ports description table ............................................................................................................................................40
Tab. 10.7: Gate and Delay Generator ports description table......................................................................................................40
Tab. 10.8: Local Bus ports description table...................................................................................................................................41
Tab. 10.9: Main parameters of the Gate and Delay Generator....................................................................................................44
Tab. 10.10: Local Bus registers description for the Gate and Delay Generator configuration ................................................45

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
7
1Introduction
The DT5495 is a general-purpose programmable FPGA and I/O unit in a compact desktop form factor. The
board is a suitable solution for the implementation of digital functions such as Coincidence, Trigger Logic,
Gate and Delay Generator, Input/Output Register and more.
The programmable architecture is based on the User FPGA (hereafter UFPGA). The UFPGA is directly
interfaced to the front panel I/Os and to an onboard Gate and Delay Generator, that allows to delay and gate
up to 32 signals. A second FPGA, the Main FPGA (hereafter MFPGA), is responsible for USB and Ethernet
interface management. The MFPGA communicates with the UFPGA through an internal local bus.
The presence of three expansion slots interfaced to the UFPGA allows to extend the channel interface of the
DT5495 by adding up to three independent mezzanine boards. Five mezzanine board types are available:
A395A, A395B, A395C, A395D, A395E (see Tab. 1.2). The DT5495 can reach a maximum of 194 I/O channels.
The board can be controlled and programmed through either the Ethernet or the USB interface. The
CAENUpgrader software tool is provided to upload the FPGA firmware, while a dedicated C library is
available to support the custom software development. A rear panel dedicated JTAG connector allows for in-
system JTAG configuration and debugging (e.g. using Altera SignalTap).
Simple operations, like retrieving the board information or changing the ethernet settings, can be performed
simply via the Internet or a Local Area Network (LAN) through the web inteface, without need of any control
software but just opening a web browser.
The DT5495 is also available in VME form factor, called V2495, which represents an evolution of CAEN V1495
board. Thanks to several analogies with the V1495 (e.g. the front panel connectors have the same function
and nomenclature with respect to the V1495), users who want to upgrade their system with the DT5495 can
port their firmware already developed for the V1495 just considering few hints (Sect. Porting V1495 to
DT5495).
The following Tab. 1.1 is a comparison table between the two modules.
V1495
DT5495
User FPGA
Altera Cyclone EPI1C20, 20k LEs
Altera Cyclone V GX, 50k LEs
Front Panel I/O
Sections A and B (2 x 68-pin Robinson Nugent connector; 32 input channel each)
Section C (1 x 68-pin Robinson Nugent connector; 32 output channels)
Section G (2 X LEMO connector; input/output channels)
On-board Delay
Generator
4 Delay lines
32 Gate and Delay lines
Local Bus
16-bit 50 MHz parallel interface
VME Bus
Addressing spaces: A24, A32
Data transfer modes: D16, D32, BLT32
Not Supported
USB Interface
Not Supported
USB2.0
ETH Interface
Not Supported
ETHERNET 10/100T
Mezzanine
Boards
A395A, A395B, A395C, A395D, A395E
Tab. 1.1: Comparison table between V1495 and DT5495

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
8
Tab. 1.2 lists the board models, the firmware and hardware related products as well as the ordering option
information.
Board Models
Description
Product Code
DT5495
Desktop Programmable Logic Unit
WDT5495XAAAA
User Firmware
Description
Product Code
FW2495SC⁽*⁾
Channel Latching Scaler for V2495 and DT5495
WFW2495SCXAA
Accessories
Description
Product Code
A395A
32 LVDS/ECL/PECL input channels
WA395XAAAAAA
A395B
32 LVDS output channels
WA395XBAAAAA
A395C
32 ECL output channels
WA395XCAAAAA
A395D
8 NIM/TTL input/output channels
WA395XDAAAAA
A395E
8 Channel 16Bit ±5V DAC
WA395XEAAAAA
A967
32 Channel Cable Adapter (1x32 to 2x16)
WA967XAAAAAA
Tab. 1.2: Table of models and related items
⁽*⁾ Paid firmware; unlocking license needed. Please, refer to the FW2495SC web page for details.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
9
2Block Diagram
A
B
C
32
32
32
32
32
32
USER
PROGRAMMABLE
FPGA
(UFPGA)
MAIN FPGA
(MFPGA)
16 bit
ETHERNET
LOCAL
BUS
G
Gate and Delay
Generator
D
E
F
USB
32
Fig. 2.1: Block diagram

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
10
3Main Components and Interconnections
User
FPGA
(Cyclone V GX)
Main
FPGA
(Cyclone V E)
Gate and Delay
Generator
Local Bus
(16-bit@50MHz)
USB
PHY
FLASH
FLASH
FLASH
A PORT (IN) /
D PORT (IN/OUT)
B PORT (IN) /
E PORT (IN/OUT)
C PORT (OUT) /
F PORT (IN/OUT)
USB
G PORT (IN/OUT)
JTAG
JTAG
USER FW
SELECTOR
50 MHz
50 MHz
50 MHz
AD9520
ETH
ETH
Fig. 3.1: Main components and interconnections

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
11
3.1 USB Interface
The DT5495 is equipped with a USB2.0 interface. The USB physical layer is managed by a high-speed transceiver
controlled by the Main FPGA.
3.2 Ethernet Interface
In addition to the USB, the DT5495 provides a 10/100T Ethernet interface controlled by the Main FPGA.
3.3 Main FPGA
The MFPGA (Altera Cyclone V E) manages the Ethernet and USB interfaces and the connection with the UFPGA through
a proprietary 16-bit@50 MHz local bus. The MFPGA has a dedicated external flash memory for configuration purposes.
It also pilots the flash memories dedicated to loading the firmware on the UFPGA and on the GDG.
3.4 User FPGA
The User FPGA (Altera Cyclone V GX) manages the I/O peripherals (A/D, B/E, G, C/F ports) and communicates with the
GDG. A dedicated external flash memory can store a set of firmware images to be loaded on the User FPGA. A
dedicated JTAG connector allows to program the UFPGA “on-the-fly” for fast firmware prototyping and debugging.
3.5 Gate and Delay Generator
The DT5495 hosts a Gate and Delay Generator (see Fig. 3.2) able to provide up to 32 gated and delayed signals
(“delayed signals”) triggered by 32 inputs (“start signals”). The gate width and delay value are user programmable. The
GDG is an external component implemented in a Xilinx Spartan-6 FPGA. It is connected through a serial bus (SPI) to the
User FPGA for gate and delay register programming (refer to Sect. Gate and Delay Controller for detailed information).
The GDG configuration is stored in a dedicated flash memory. The GDG firmware cannot be modified by the user.
User FPGA Gate and Delay
Generator
32
32
Start signals
Delayed signals
Start[i]
Delayed[i]
Td Tg
Fig. 3.2: The UFPGA and GDG interface.
3.6 Clock Distribution
Each FPGA receives the same 50-MHz system clock generated by a common on-board oscillator.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
12
4Front Panel Connectors, LEDs and Labels
USB PORT
&
ACTIVITY LED
CONFIGURATION
LED
‘A’ CONNECTOR
(32-ch input only)
USER CONFIGURATION
LEDs
‘B’ CONNECTOR
(32-ch input only)
‘C’ CONNECTOR
(32-ch output only)
G0, G1 CONNECTORS
(Input/Output selectable)
ETH PORT
‘JTAG’ CONNECTOR
IDENTIFICATION
LABEL ‘RESTORE’ BUTTON
DC IN
CONNECTOR
ON/OFF
SWITCH
Fig. 4.1: front (top) and rear (down) panel view

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
13
4.1 Front Panel
USB PORT
FUNCTION
MiniUSB connector to
communicate with the DT5495 by
USB link for board configuration
and firmware upgrade.
ELECTRICAL SPECS
N.A.
MECHANICAL SPECS
Series: miniUSB connectors.
Type: SD-54819-026 (B-type).
Manufacturer: Molex Inc.
CABLES
A 1-m USB standard cable is included with
the DT5495 (USB A-type to miniUSB B-type).
USB LED (GREEN): driven by the Main PFGA, this LED lights up if a USB read/write access to the board is performed.
ETHERNET PORT
FUNCTION
Ethernet connector to communicate
with the DT5495 for board
configuration and firmware upgrade.
ELECTRICAL SPECS
10/100T ETHERNET
MECHANICAL SPECS
Series: RJ45 connectors.
Type: GIGABIT MIC3801D-5166.
Manufacturer: Wurt.
CABLES
A 2-m Ethernet cable is included with the
DT5495 (type ASSMANN: A-
MCSSP60020/R).
A, B, C CONNECTORS
FUNCTION
Motherboard I/O 34+34 pin connectors:
-A/B are inputs
-C is an output
ELECTRICAL SPECS
See Tab. 5.1.
MECHANICAL SPECS
Series: 80-0009-0666-1.
Type: P50E-068-P1-SR1-TG.
Manufacturer: 3M.
CFG LED
FUNCTION
This LED is constantly on when all the
on-board FPGAs are configured by the
application firmware on their relevant
flash memory. The LED blinks if the
MFPGA is in Factory mode.
COLOR
Green.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
14
G0, G1 CONNECTORS
FUNCTION
Bidirectional single-ended connectors. Factory
direction is Output. (high impedance state).
External 50Ωtermination required when using
the connector as input.
ELECTRICAL SPECS
See Tab. 5.1.
MECHANICAL SPECS
Series: 00 LEMO Connectors.
Type: EPY.00.250.NTN.
Manufacturer: LEMO
0, 1, 2, …, 7 LEDs
FUNCTION
The status of these LEDs is user-programmable
NOTE: when the UFPGA is in Factory mode, odd and even LEDs
alternatively blink.
COLOR
Green.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
15
4.2 Rear Panel
IDENTIFICATION LABEL
A blue label on the Desktop rear panel indicates:
- the model;
- the serial number (S/N);
- the symbol of the CE conformity marking.
JTAG CONNECTOR
FUNCTION
This connector allows for on-the-fly
FPGA programming.
ELECTRICAL SPECS
N.A.
MECHANICAL SPECS
Series: 4600 - panel rectangular
connectors.
Type: 4610-6350.
Manufacturer: 3M.
RESTORE BUTTON
FUNCTION
Restores the default IP address and
forces the module in factory state (see
Sect. Restore Function).
ELECTRICAL SPECS
N.A.
MECHANICAL SPECS
Series: 9000 - momentary pushbutton
switches.
Type: APR9433NA-O.
Manufacturer: Apem.
JTAG CONNECTOR
FUNCTION
Input connector for the DT5495
main power supply from the
external AC/DC adaptor.
ELECTRICAL SPECS
Input voltage: +12 VDC (typ.).
MECHANICAL SPECS
Series: DC power Jacks.
Type: KLDX-0202-A-LT.
Manufacturer: KYCON.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
16
ON/OFF SWITCH
FUNCTION
Power switch of the module:
on (I) / off (O)
ELECTRICAL SPECS
N.A.
MECHANICAL SPECS
Series: Power Switches.
Type: Rocker SwitchP (A11131121000)
Manufacturer: Molveno.

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
17
5Technical Specifications
DT5495 Motherboard
FORM FACTOR
Desktop module
I/O SECTIONS A and B
Nr. of Channels
32
Direction
Input
Logic
Direct
Signal
Differential LVDS/ECL/PECL
(single ended TTL optional)
Zdiff: 100 Ω
Extended Common Mode
Input range: -4V to +5V
Fail Safe input feature
Bandwidth
200 MHz
Front Panel Connector
Robinson Nugent P50E-068-P1-SR1-TG
type, (34+34) pins
I/O SECTION C
Nr. of Channels
32 channels
Direction
Output
Logic
Direct
Signal
Differential LVDS
Require 100 Ωtermination
Bandwidth
250 MHz
Front Panel Connector
Robinson Nugent P50E-068-P1-SR1-TG
type, (34+34) pins
I/O SECTION G
Nr. of Channels
2
Direction
I/O (default is Ouput)
External 50 Ωtermination
required when used as
input
Logic
TTL IN = Direct
TTL OUT = Direct
NIM IN = Invert
NIM OUT = Direct
Signal
Single ended NIM/TTL
selectable
Bandwidth
250 MHz
Front Panel Connector
LEMO 00
GATE and DELAY
GENERATOR
Minimum Delay/Gate
Min.
Typ.
Max.
9.6 ns
10.7 ns
11.8 ns
Maximum Delay/Gate
631 µs
701.2 µs
771.5 µs
Maximum channel-to-channel spread: 20%
COMMUNICATION
INTERFACE
ETHERNET
10/100T
USB
USB 2.0 compliant
POWER REQUIREMENTS
750 mA (max.) @ +12VDC
AC-DC 12V-45W power unit included
Tab. 5.1: DT5495 specifications table
A395A Mezzanine Board
I/O SECTION
Nr. Of Channels
32
Direction
Input
Logic
Direct
Signal
Differential LVDS/ECL/PECL
(single ended TTL optional)
Zdiff: 100 Ω
Extended Common Mode
input range: -4V to +5V
Fail Safe input feature
Bandwidth
200 MHz
Front Panel Connector
Robinson Nugent P50E-068-P1-SR1-TG
type, (34+34) pins
POWER CONSUMPTIONS
0.1 A (max) @ +5V internal rail
+12V and -12V internal rails are not used
Tab. 5.2: A395A Mezzanine specifications table

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
18
A395B Mezzanine Board
I/O SECTION
Nr. of Channels
32
Direction
Output
Logic
Direct
Signal
Differential LVDS
Requires 100 Ω
termination
Bandwidth
250 MHz
Front Panel Connector
Robinson Nugent P50E-068-P1-SR1-TG
type, (34+34) pins
POWER CONSUMPTIONS
0.1 A (max) @ +5V internal rail
+12V and -12V internal rails are not used
Tab. 5.3: A395B Mezzanine specifications table
A395C Mezzanine Board
I/O SECTION
Nr. of Channels
32
Direction
Output
Logic
Direct
Signal
Differential ECL
Bandwidth
300 MHz
Front Panel Connector
Robinson Nugent P50E-068-P1-SR1-TG
type, (34+34) pins
POWER CONSUMPTIONS
1.4 A (max) @ +5V internal rail
+12V and -12V internal rails are not used
Tab. 5.4: A395C Mezzanine specifications table
A395D Mezzanine Board
I/O SECTION
Nr. of Channels
8
Direction
I/O selectable
Logic
Direct
Signal
TTL IN = Direct
TTL OUT = Direct
NIM IN = Invert
NIM OUT = Direct
Bandwidth
250 MHz
Front Panel Connector
LEMO 00
POWER CONSUMPTIONS
1.1 A (max) @ +5V internal rail
+12V and -12V internal rails are not used
Tab. 5.5: A395D Mezzanine specifications table
A395E Mezzanine Board
I/O SECTION
Nr. of Channels
8
Direction
Output
Logic
Analog
Signal
16-bit resolution
±5V @10kΩ RL
±4V @200Ω RL
Bandwidth
n.a.
Front Panel Connector
LEMO 00
POWER CONSUMPTIONS
0.3 A (max) @ +5V internal rail
+12V and -12V internal rails are not used
Tab. 5.6: A395E Mezzanine specifications table

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
19
6Power Requirements
The DT5495 is powered by the external 45W 12V AC/DC stabilized power supply unit included in the delivered kit (see
Sect. Shipping Content). The maximum required current is typically 500mA (without any mezzanine extension).

CAEN
Electronic Instrumentation
UM6508 –DT5495 User Manual rev. 0
20
7Getting Started with DT5495
7.1 Shipping Content
DESCRIPTION
ITEM
DT5495 Programmable VME Logic Unit
With or without mezzanine board extension(s), according to the order⁽¹⁾
USB cable
Ethernet cable
Power Supply adaptor
DT5495 User Manual
⁽¹⁾ Mezzanine boards are available by ordering option (refer to Tab. 1.2).