Caen V895 Series User manual

Technical
Information
Manual
19 March 2009
Revision n. 3
MOD. V895 series
16 CHANNEL
LEADING EDGE
DISCRIMINATORS
NPO:
00101/97:V895x.MUTx/03

CAEN will repair or replace any product within the guarantee period if the Guarantor declares
that the product is defective due to workmanship or materials and has not been caused by
mishandling, negligence on behalf of the User, accident or any abnormal conditions or
operations.
CAEN declines all responsibility for damages or
injuries caused by an improper use of the Modules due
to negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's
Manual before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time
and without giving any notice.
Disposal of the Product
The product must never be dumped in the Municipal Waste. Please check your local
regulations for disposal of electronics products.

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TABLE OF CONTENTS
1. GENERAL DESCRIPTION ..................................................................................................................5
1.1. FUNCTIONAL DESCRIPTION.......................................................................................................................5
1.2. BLOCK DIAGRAM......................................................................................................................................7
1.3. TECHNICAL SPECIFICATION TABLE ...........................................................................................................8
2. TECHNICAL SPECIFICATIONS......................................................................................................10
2.1. PACKAGING............................................................................................................................................10
2.2. POWER REQUIREMENTS ..........................................................................................................................10
2.3. FRONT PANEL.........................................................................................................................................11
2.4. EXTERNAL CONNECTORS........................................................................................................................12
2.4.1. INPUT connectors.........................................................................................................................12
2.4.2. OUTPUT connectors.....................................................................................................................12
2.5. OTHER COMPONENTS .............................................................................................................................13
2.5.1. Displays.........................................................................................................................................13
2.5.2. Switches.........................................................................................................................................13
2.5.3. Jumpers .........................................................................................................................................13
2.6. CHARACTERISTIC OF THE SIGNALS .........................................................................................................16
3. VME INTERFACE...............................................................................................................................17
3.1. ADDRESSING CAPABILITY.......................................................................................................................17
3.2. DISCRIMINATOR THRESHOLDS................................................................................................................18
3.3. PATTERN OF INHIBIT...............................................................................................................................18
3.4. OUTPUT WIDTH CH.0÷7.........................................................................................................................18
3.5. OUTPUT WIDTH CH.8÷15.......................................................................................................................18
3.6. MAJORITY THRESHOLD ..........................................................................................................................18
3.7. TEST PULSE ............................................................................................................................................19
3.8. MODULE IDENTIFIER WORDS ..................................................................................................................19
4. OPERATING MODES.........................................................................................................................20
4.1. TEST,VETO AND OR SIGNALS................................................................................................................20
4.2. CHANNEL TEST.......................................................................................................................................20
4.3. THRESHOLD SETTING .............................................................................................................................21
4.4. OUTPUT PULSE WIDTH SETTING..............................................................................................................21
4.5. UPDATING AND NON-UPDATING MODE SETTING....................................................................................21
4.6. CURRENT SUM SIGNAL...........................................................................................................................23
4.7. MAJORITY SETTING ................................................................................................................................24

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LIST OF FIGURES
FIG.1.1: MODEL TYPE LABEL (EXAMPLE)................................................................................................................ 6
FIG.1.2: BLOCK DIAGRAM...................................................................................................................................... 7
FIG.2.1: MOD.V895 FRONT PANEL....................................................................................................................... 11
FIG.2.2: COMPONENTS LOCATION......................................................................................................................... 14
FIG.2.3: JUMPERS LOCATION................................................................................................................................. 15
FIG.2.4: VETO SIGNAL .......................................................................................................................................... 16
FIG.3.1: MODULE IDENTIFIER WORDS.................................................................................................................. 19
FIG.4.1: V895 UPDATING AND NON-UPDATING MODE ......................................................................................... 22
FIG.4.2: CURRENT SUM SIGNAL............................................................................................................................ 23
FIG.4.3: EXAMPLE OF THREE DAISY CHAINED V895 ............................................................................................. 25
LIST OF TABLES
TABLE 1.1:VERSIONS AVAILABLE FOR THE MODEL V895....................................................................................... 6
TABLE 1.2: TECHNICAL SPECIFICATION TABLE........................................................................................................ 8
TABLE 2.3: POWER REQUIREMENTS....................................................................................................................... 10
TABLE 3.1: ADDRESS MAP .................................................................................................................................... 17

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1. General description
1.1. Functional description
The CAEN Mod. V895 is a 16 CHANNEL LEADING EDGE DISCRIMINATOR housed in
a single width VME module. The module accepts 16 negative inputs (positive on request)
and produces 16 differential ECL outputs with a fan-out of two on two front panel header
connectors (a functional block diagram is shown in Fig. 1.2).
The pulse forming stage of the discriminator produces an output pulse whose width is
adjustable in a range from 5 ns to 40 ns via VME.
Each channel can work both in Updating and Non-Updating mode according to on-board
jumpers position.
The discriminator thresholds are individually settable in a range from -1 mV to -255 mV (1
mV step), via VME through an 8-bit DAC. The front panel houses also VETO and TEST
inputs.
A Current Sum output generates a current proportional to the input multiplicity, i. e. to the
number of channels over threshold, at a rate of -1.0 mA per hit ±20 %.
A "MAJORITY" output provides a NIM signal if the number of input channels over
threshold exceeds the MAJORITY programmed value.
Several V895 boards can be connected in a daisy chain via the Current Sum output: in
this case, by switching the majority logic to “External”, it’s possible to obtain a Majority
signal when the number of active channels in the chained modules exceeds a global
Majority level.
An "OR" output on a front panel connector provides a global OR of the output channels.
The relevant "OR" LED lights up if at least one of the unmasked channels is over
threshold. The module's operations are completely controlled via software for each
channel through the VME bus. The most important are:
-Setting of the discriminator thresholds (8 bit data) from -1 to -255 mV.
-Setting pattern of inhibit; each channel can be turned "ON" or "OFF" by using a mask
register.
-Setting output width in a range from 5 to 40 ns.
-Setting of the Majority threshold value.
-Common TEST.
Several versions are available, refer to Table 1.1 for details.

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Table 1.1:Versions available for the Model V895
Fig. 1.1: Model type label (example: V895 B)
1A label on the printed board soldering side indicates the module’s version (see Fig 1.1).
2The version with the PAUX connector requires the V430 backplane.
3Available exclusively on request
Version1Number of
channels PAUX connector2
V895316 yes
V895 B 16 no
TYPE
RIF N.
DATE MAY 5th 2002
WV895XBAAAAA

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1.2. Block diagram
Fig. 1.2: Block Diagram
DACs,TEST,
INHIBIT
WLOGIC
VME
INTERFACE
8 bit
DAC
ch.0
8 bit 8 bit 8 bit
ch.1 ch14 ch.15
........................
THRESHOLDS
.................discr.
INPUTS<0..15>
test
inhibit
ch.0 ch.1 ch.14 ch.15
TEST
VETO
OUTPUTS<0..15>A, B
OR LED
..................
discr. discr. discr.
ANDWIDTH
OR OUT
Σ
MAJ
8 bit
DAC
MAJ
DAC DAC DAC
VME
BUS

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1.3. Technical specification table
Table 1.2: Technical specification table
General
Packaging
6U-high, 1U-wide VME unit
Power requirements
Refer to § 2.2
Threshold range
-1 mV to -255 mV (-1 mV step)
Input Signals
Inputs Channels
16 inputs
negative polarity
DC coupling
Input Impedance
50 Ω
Reflections
<4% for input pulses of 2 ns rise time
Input Range
-5 mV ÷-5 V
Input Offset
±5 mV
Max input frequency
140 MHz (Updating mode)
80 MHz (Non Updating mode)
Double Pulse Resolution
7 ns (Updating mode)
12 ns (Non Updating mode)
Test Input
NIM logic signal
High impedance
Min. FWHM: 5 ns
Max. frequency: 60 MHz
Veto Input
NIM logic signal
High impedance
Min. FWHM: 15 ns

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Output Signals
Outputs
16 ECL outputs with a fan-out of two
Outputs Impedance
110 Ω
Output Width
5±1 ns to 40±5 ns FWHM
Output Rise/Fall Time
<3 ns
Input/Output Delay
15.5 ±1.5 ns
Crosstalk
<47 dB
Majority Output
NIM logic signal
50 Ωimpedance
Or Output
NIM logic signal
50 Ωimpedance
Max. frequency: 50 MHz
ΣOutput
-1 mA ±20% per hit
high impedance
Max. frequency: 25 MHz

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2. Technical Specifications
2.1. Packaging
The Models V895 and V895 B are housed in a 6U-high 1U-wide VME unit.
The Mod. V895 is provided with P1, P2 and PAUX connectors.
The Mod. V895 B is provided with P1, P2 connectors (NO PAUX).
2.2. Power requirements
The power requirements of the Mod. V895 and Mod. V895 B (NO PAUX) are as follows:
Table 2.3: Power requirements
Power supply V895 V895 B
+ 12 V 110 mA 110 mA
- 12 V 50 mA 50 mA
+ 5 V 700 m A 5.5 A
- 5 V 3.5 A -

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2.3. Front panel
Mod. V895
LED
16 CH
16 CH
OR
MAJ
Σ
I
N
2
0
4
6
3
1
5
7
I
N
12
14
10
8
13
15
11
9
DTK
V
E
T
O
T
E
S
T
- + - +
- + - +
8
0
15
7
OUT
OUT
Fig. 2.1: Mod. V895 front panel

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2.4. External connectors
The location of the connectors is shown in Fig. 2.1. Their function and electromechanical
specifications are listed in the following subsections.
2.4.1. INPUT connectors
INPUT CHANNELS: Mechanical specifications:
16 LEMO 00 type connectors.
Electrical specifications:
negative polarity, 50 Ohm impedance, DC
coupling; input range: -5 mV ÷-5 V; input
offset: ±5 mV; 140 MHz maximum input
frequency.
VETO INPUT: Mechanical specifications:
1 LEMO 00 type connectors.
Electrical specifications:
standard NIM logic signal, high impedance,
15 ns minimum FWHM; leading edge of the
VETO signal must precede of at least 8 ns the
leading edge of the input and overlap
completely the input signal; the VETO signal
doesn’t act on TEST input.
TEST INPUT: Mechanical specifications:
1 LEMO 00 type connectors.
Electrical specifications:
standard NIM logic signal, high impedance,
5 ns minimum FWHM, 60 MHz maximum
input frequency.
2.4.2. OUTPUT connectors
OUTPUT CHANNELS: Mechanical specifications:
4 Header 3M 3408-D202 type, 8+8 pin
connectors.
Electrical specifications:
Differential ECL level on 110 Ohm
impedance; pulse width adjustment from 5±1
ns to 40±5 ns FWHM.
Input/Output delay: 15.5±1.5 ns.
OR OUTPUT: Mechanical specifications:
1 LEMO 00 type connectors.
Electrical specifications:
standard NIM logic signal, 50 Ωimpedance;
50 MHz maximum input frequency.

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ΣOUTPUT: Mechanical specifications:
1 LEMO 00 type connectors.
Electrical specifications:
current output (-1 mA ±20% per hit), high
impedance; 25 MHz maximum input frequency.
MAJORITY OUTPUT: Mechanical specifications:
1 LEMO 00 type connectors.
Electrical specifications:
standard NIM logic signal, 50 Ωimpedance.
2.5. Other components
2.5.1. Displays
The front panel hosts the following LEDs:
DTACK
Type: 1 green LED
Function: VME selected; it lights up during a VME access.
OR
Type: 1 green LED
Function: it lights up if at least one output signal is present.
2.5.2. Switches
ROTARY SWITCHES
Function: they allow to select module’s base address; please refer to Fig. 2.2 for their
setting.
2.5.3. Jumpers
JP1
Function: it allows to select the Majority logic (Internal, External); please refer to Fig. 2.3
for the jumper location on the V895 board.
MODE JUMPERS
16 3-pin jumpers allow to select the channel’s operating mode (updating / non updating);
refer to Fig. 2.3 for the jumpers’ location on the V895 board.

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Channels 8 to 14
Flat Cable
Connectors A-B
Test
Veto
Channels 0 to 7
Flat Cable
Connectors A-B
VME P2
connector
VME P1
connector
Rotary switches for
Base Address selection
VME PAUX connector
OR
MAJ
SUM
Base address bit <23 ... 20>
Base address bit <19 ... 16>
Base address bit <31 ... 28>
Base address bit <27 ... 24>
Component side of the board
Rotary switches for
Base Address selection
0
8
4
C
3
B
1
9
A
2
7
F
5
D
E
6
0
8
4
C
3
B
1
9
A
2
7
F
5
D
E
6
0
8
4
C
3
B
1
9
A
2
7
F
5
D
E
6
0
8
4
C
3
B
1
9
A
2
7
F
5
D
E
6
Rotary switches for
Base Address selection
Discriminator
Ch. 14 - Ch. 15
Discriminator
Ch. 12 - Ch. 13
Discriminator
Ch. 8 - Ch. 9
Discriminator
Ch. 10 - Ch. 11
Discriminator
Ch. 6 - Ch. 7
Discriminator
Ch. 4 - Ch. 5
Discriminator
Ch. 2 - Ch. 3
Discriminator
Ch. 0 - Ch. 1
(V895 only)
Fig. 2.2: Components location

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Fig. 2.3: Jumpers location
Updating
Non Updating
VME P2
connector
VME P1
connector
VME PAUX connector
JP1
Internal
External
Components side
Mode
Jumpers

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2.6. Characteristic of the signals
INPUTS
Channels: Negative polarity, 50 Ohm impedance; maximum input frequency:
•140 MHz (updating)
•80 MHz (non updating)
DC coupling; input range: -5 mV ÷-5 V; input offset: ±5 mV; reflections: < 4% for 2 ns
rise time input signals.
VETO: standard NIM logic signal, high impedance, 15 ns minimum FWHM. Leading edge
of the VETO signal must precede of at least 8 ns the leading edge of the input and
overlap completely the input signal (see Fig. 2.4).
N.B.: the VETO signal doesn’t act on TEST input
INPUT SIGNAL
THRESHOLD
T
β
Tα
VETO
time Tαmin >8 ns
Tβ>0
T
Requirements:
T >15 ns
Fig. 2.4: Veto signal
TEST: standard NIM logic signal, high impedance, 5 ns minimum FWHM, 30 MHz
maximum input frequency.
OUTPUTS
Outputs: Differential ECL level on 110 Ohm impedance. Pulse width adjustment: from
5±1 ns to 40±5 ns FWHM. Outputs pulses can be programmed either in Updating or Non-
Updating mode (see § 4.5). Output pulse rise/fall time: <3 ns. INPUT-OUTPUT delay:
17.5+1.5 ns.
OR: standard NIM logic signal on 50 Ohm; maximum output frequency: 50 MHz; 4 ns
rise/fall time.
CURRENT SUM: high impedance with rate of -1 mA + 20% per hit; maximum output
frequency: 25 MHz; 8 ns rise/fall time.
MAJORITY: standard NIM logic signal on 50 Ohm.

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3. VME Interface
3.1. Addressing capability
The V895 module works in A24/A32 mode. This implies that the module’s address must
be specified in a field of 24 or 32 bits. The address modifiers codes recognized by the
module are:
AM = %39 Standard user data access
AM = %3D Standard supervisor data access
AM = %09 Extended user data access
AM = %0D Extended supervisor data access
The module’s Base address is fixed by 4 Internal rotary switches housed on two piggy-
back boards plugged into the main printed circuit board (see Fig. 2.2).
The Base address can be selected in the range:
% 00 0000 <-> % FF 0000 A24 mode
% 0000 0000 <-> % FFFF 0000 A32 mode
The module’s address lines A09÷A15 are not connected, so their content is meaningless:
for example writing to either Base + 104C or Base + 284C the same register is accessed.
Table 3.1: Address Map
ADDRESS REGISTER/CONTEN T TYPE
Base + %00
Base + %02
Base + %04
Base + %06
Base + %08
Base + %0A
Base + %0C
Base + %0E
Base + %10
Base + %12
Base + %14
Base + %16
Base + %18
Base + %1A
Base + %1C
Base + %1E
Threshold register Ch. 0
Threshold register Ch. 1
Threshold register Ch. 2
Threshold register Ch. 3
Threshold register Ch. 4
Threshold register Ch. 5
Threshold register Ch. 6
Threshold register Ch. 7
Threshold register Ch. 8
Threshold register Ch. 9
Threshold register Ch. 10
Threshold register Ch. 11
Threshold register Ch. 12
Threshold register Ch. 13
Threshold register Ch. 14
Threshold register Ch. 15
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Write only
Base + %40
Base + %42 Output width register Ch. 0 to 7 Output width register Ch. 8 to 15 Write only Write only
Base + %48 Majority threshold register Write only
Base + %4A Pattern Inhibit register Write only
Base + %4C Test pulse register Write only
Base + %FA
Base + %FC
Base + %FE
Fixed code
Manufacturer & Module type
Version & Serial number
Read only
Read only
Read only

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3.2. Discriminator thresholds
(Base address + %00 to %1E write only)
These registers contain the discriminator thresholds values on 8 bit words. The
thresholds values can be programmed in a range from -1 mV to -255 mV with 1 mV
steps, writing an integer number between 1 and 255 into the register; the thresholds are
individually settable.
3.3. Pattern of inhibit
(Base address + %4A write only)
This register contains the Pattern of Inhibit, a 16 bit word indicating which channels are
either enabled or disabled (bit X=1 ⇒Ch. X enabled…bitX=0 ⇒Ch. X disabled).
3.4. Output width Ch. 0÷7
(Base address + %40 write only)
This register contains the output pulse width value of the channels 0 through 7 on a 8 bit
word. This value can be adjusted in the range from 5 ns to 40 ns, writing an integer
number between 0 and 255 into the register. The set value corresponds to the width as
follows: 255 leads to a 40 ns pulse duration, 0 leads to a 5 ns pulse duration, with a
non-linear relation for intermediate values
3.5. Output width Ch. 8÷15
(Base address + %42 write only)
This register contains the output pulse width value of the channels 8 through 15 on a 8
bit word. This value can be adjusted in the range from 5 ns to 40 ns, writing an integer
number between 0 and 255 into the register. The set value corresponds to the width as
follows: 255 leads to a 40 ns pulse duration, 0 leads to a 5 ns pulse duration, with a
non-linear relation for intermediate values
3.6. Majority threshold
(Base address + %48 write only)
This register allows to set the Majority threshold between 1 and 16 for Internal Majority
and between 1 and 20 for External Majority writing a proper value in the Base address
+ %48 (value range: 1÷244).
The Majority threshold can be calculated in the following way:
MAJTHR = NINT[(MAJLEV*50 −25)/4],
where NINT is the nearest integer function (allowed values for MAJLEV: 1 to 20) e.g.: if
the desired Majority level is 5, the correct MAJTHR value to use is 56 (see also § 4.7).

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3.7. Test pulse
(Base address + %4C write only)
A test pulse on all output channels can be generated by performing a write access at
Base address + %4C; the test pulse is generated independently from the number written
into this register.
3.8. Module identifier words
(Base address + %FA, + %FC, + %FE, read only)
Three words located at the Base address + %FA,+ %FC, + %FE of the page are used to
identify the module, as shown in Fig. 3.1:
0123456789101112131415
V e r s i o n M o d u l e ' s s e r i a l n u m b e r Base + % FE
Address
Base + % FC
Base + % FA
Manufacturer number M o d u l e t y p e
% F A F i x e d c o d e % F 5 F i x e d c o d e
Fig. 3.1: Module Identifier Words
The word located at the address Base + %FE identifies the single module via a serial
number, and any change in the hardware will be shown by the version number .
For the Mod. V895 the word at the address Base + %FC has the following configuration:
Manufacturer N° = 000010 b
Type of module = 0001010100

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4. Operating Modes
4.1. Test, Veto and Or signals
Some operations can be performed sending two external NIM signals:
•TEST: an input signal sent through this connector triggers all the enabled
channels at once. This feature allows to check the module as well as to generate
a pattern of pulses suitable to test any following electronics.
•VETO: (see Fig.2.1) an input signal sent through this connector allows to inhibit
all channels simultaneously. Its leading edge must precede the input signal
leading edge by at least 8 ns and overlap completely the input signal. It doesn’t
act on TEST input
•An OR output connector provides also the logical OR of the output channels. The
relevant "OR" LED lights up if at least one of the enabled channels is over threshold.
4.2. Channel test
It is possible to test all channels in the following ways:
•sending a NIM pulse through one of the two "TEST" connectors located on the
front panel.
•performing a write access to the + %4C base address (see § 3.8).
Note: TEST and VETO are high impedance inputs and each one is provided
with two bridged connectors for daisy chaining (the chain has to be terminated
on 50 Ohm on the last module)