Chrontel CH7219 Installation and operating instructions

AN-B058
Application Note
206-1000-058 Rev. 0.1 2023-10-25 1
Chrontel
P C B L a y o u t a n d D e s i g n G ui d e f o r C H 7 2 1 9
1.0 INTRODUCTION
Chrontel’s CH7219 is specially designed to target the USB Type-C to HDMI converter, adapter and docking device.
The CH7219’s DP/eDP receiver is compliant with the DisplayPort Specification 1.4 and Embedded DisplayPort (eDP)
Specification version 1.4. With sophisticated DisplayPort signal detection and the Lane Swap/AUX polarity inversion
logic, the CH7219 supports USB Type-C cable plug orientation switch. With internal HDCP key Integrated, the
device support HDCP 1.4 and 2.3 specifications. In the device’s receiver block, which supports four DisplayPort
Main Link Lanes input with data rate running at 1.62Gbps, 2.7Gbps, 5.4Gbps or 8.1Gbps, and converted the input
signal to HDMI output up to 4Kx2k@60Hz. Leveraging the USB Power Delivery control logic, the USB billboard
module for USB device indentify and DisplayPort’s unique source/sink “Link Training” routine, the CH7219 is
capable of instantly bring up the video display to the HDMI/DVI TV/Monitor when the initialization process is
completed.
This application note focuses only on the basic PCB layout and design guidelines for the CH7219. Guidelines in
component placement, power supply decoupling, grounding, input /output signal interface are discussed in this
document.
The discussion and figures presented in this document are based on the 68-pin QFN (8x8 mm) package of the
CH7219. Please refer to the CH7219 datasheet for details of the pin assignments.
2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS
Components associated with the CH7219 should be placed as close as possible to the respective pins. The following
will describe guidelines on how to connect critical pins, as well as the guidelines for the placement and layout of
components associated with these pins.
2.1 Power Supply Decoupling
The optimal power supply decoupling is accomplished by placing a ceramic capacitor at each of the power supply
pins as shown in Figure 1. These capacitors (C1, C2, C3, C4, C6, C7, C9, C11, C12, C14, C15, C16, C17, C18, C19
C21,C23,C24,C25,C26,C27 and C28) should be connected as close as possible to their respective power and ground
pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should
connect the ground pins of the decoupling capacitors to the CH7219 ground pins, in addition to ground vias.
2.1.1 Ground Pins
The CH7219 should be connected to a common ground plane to provide a low impedance return path for the supply
currents. Whenever possible, each of the CH7219 ground pins should be connected to its respective decoupling
capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and wide traces
should be used to minimize the lead inductance. Refer to Table 1 for the Ground pin assignments.
2.1.2 Power Supply Pins
There are twelve power supply pins: AVCC, DVDD, AVDDPLL, VDDS, AVDD and VDDPLL. Refer to Table 1
for the Power supply pin assignments. Refer to Figure 1 for Power Supply Decoupling.
Table 1: Power Supply Pin Assignments for the CH7219

CHRONTEL AN-B058
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Pin
# of Pins
Type
Symbol
Description
2, 25, 41, 55
4
Power
AVCC
Analog supply voltage (3.3V)
11, 42
2
Power
DVDD
Digital supply voltage (1.2V)
18
1
Power
AVDDPLL
PLL supply voltage (1.2V)
21, 29
2
Power
VDDS
Serializer supply voltage (1.2V)
58, 59,65,66
4
Power
AVDD
Analog supply voltage (1.2V)
1
1
power
VDDPLL
Analog supply voltage (1.2V)
12, 22, 28, 43, 62
Thermal pad
6
Ground
GND
Power ground
C5
10uF
L1 47R 100MHz
1 2
C2
0.1uF C4 0.1uF
C1
0.1uF C3 0.1uF
VCC3_3
C8
10uF
C6
0.1uF
C7
0.1uF
L2 47R 100MHz
1 2
VCC1_2
C9
0.1uF C10
10uF
C11
0.1uF C12 0.1uF
C13
10uF
C21
0.1uF
C22
10uF
U1
CH7219
DVDD 11, 42
AVDDPLL 18
AVCC 2, 25, 41, 55
Thermal Pad 69
DGND 12, 43
VDDS 21, 29
GNDS 22, 28
AVDD 58,59, 65,66
VDDPLL 1
AGND 62
L3 47R 100MHz
1 2
L4 47R 100MHz
1 2
L6 47R 100MHz
1 2
L5 47R 100MHz
1 2
C23
0.1uF
C24
10nF
C25
1nF
C26
0.1uF
C27
10nF
C28
1nF
C15
10nF
C14
0.1uF
C20
10uF
C16
1nF
C17
0.1uF
C18
10nF
C19
1nF
QFN
Figure 1: Power Supply Decoupling and Distribution
Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than
0.05Ω at DC; 23Ω at 25MHz & 47Ωat 100MHz. Refer to Fair Rite part #2743019447 for details (an equivalent
part can be used for the diagram).
2.1.3 On chip power-on reset function’s sequence
The power supply must be valid and stable at least 9ms before RB signal become invalid.
Power supply
(3.3V and 1.2V)
RB
T1>9ms
Figure 2: Power on and RB timing

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 3
2.2 Internal Reference Pins
• RBIAS pin
This pin sets the reference current for internal circuit. A 1 KΩ, 1% tolerance resistor should be connected between
RBIAS and GND as shown in Figure 3. The distance between the resistor and the CH7219 should be less than 6mm,
the shorter and wider trace the better. For optimal performance, this signal should not overlay the analog power or
analog output signals.
R1 1K(1%)
U1
CH7219
RBIAS 54
QFN
Figure 3: RBIAS Pin Connection
2.3 General Control Pins
• RB
This pin is the chip reset pin for the CH7219. The RB pin is internally pulled-up. But when it is pulled-low, this pin
places the device in the power-on-reset condition.
The RB signal can be generated by on board Resistor and Capacitor delay, as shown in Figure 5, one 1MΩ resistor is
necessary to be pulled high to 3.3V. One 0.1uf capacitor is recommended to be pulled low to GND. After the powers
are stable, RB signal (low to high) is generated and sent to the chip, as shown in Figure 2.
While RB signal is generated by system global reset. In this case, the power supply should be valid and stable for at
least 20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise,
the chip can’t work well. The timing is shown in Figure 4.
Figure 4: Power-on Reset Function’s Sequence external global reset
Note:
1. The rising threshold of RB is 2.4V.
2. The falling threshold of RB is 0.4V.
• XI, XO
A 25MHz crystal (30ppm) can be connected to XI and XO as the CH7219 the optional reference clock input. In
PCB design, a 25MHz crystal must be placed as close as possible to the XI and XO pins, with traces connected from
>20ms
3.3V
1.2V
ResetB
>100
us

CHRONTEL AN-B058
4 206-1000-058 Rev. 0.12023-10-25
point to point, overlaying the ground plane. Since the crystal generates the timing reference for the CH7219, it is
essential that noise not couple into these input pins.
The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. Refer to Figure 5 for a
crystal circuit reference design and an example of load capacitors.
• GPIO0~8
General Purpose Input/Output Interface
U1
CH7219
XO 4
XI/CK_25M 3
RB 13
Y1
25MHz
C2
22pF
C3
22pF
R1
1M
C1
0.1uF
12
VCC3_3
Figure 5: General Control Pins
2.4 Serial Port Control Pins
• SPC0 and SPD0
SPD0 and SPC0 function as a serial interface where SPD0 is the bi-directional data and SPC0 is an input-only serial
clock. In the reference design, SPD0 and SPC0 pins are pulled up to +3.3V with 6.8k resistors. Through these two
pins, the internal register values of the chip can be read.
• DDC_SC and DDC_SD
DDC_SC and DDC_SD are used to interface with the DDC of DVI/HDMI receiver. This DDC pair needs to be pulled
up to 5V through 1.8 KΩ resistors
D15
SM5817
DDC_SCL_HDMI
VDD5
DDC_SDA_HDMI
R1
1.8K
1 2
R2
1.8K
1 2
VCC3_3
R3
6.8K
1 2
R4
6.8K
1 2
U1
CH7219
SPD0 44
DDC_SDA 50
DDC_SCL 51
SPC0 45
QFN
Figure 6: Serial Port Interface

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 5
2.5 Display Port Signal Pins
• DP0P/N, DP1P/N, DP2P/N, DP3P/N
These pins accept two AC-coupled differential pair signals from the Display Port transmitter or the Type-C DP Alt.
For USB Type-C Receptacle application, DP Main link lane swap is supported for compliance with the USB type C
cable plug orientation switch.
Since the digital serial data of the CH7219 may be toggled at speeds up to 8.1 Gbps, it is strongly recommended that
the connection of these video signals between the graphics controller and the CH7219 be kept as short as possible,
avoid discontinuities in the reference plane and be isolated as much as possible from the analog outputs and analog
circuitry. For optimal performance, these signals should not overlay the analog power or analog output signals. When
a signal pair has to changes layers, the ground stitching vias should be placed close to the signal vias. A minimum of
1 to 3 stitching vias per pair of signals is recommended. Never route a trace so that it straddles a plane split. It is
recommended that 5 mils traces be used in routing these signals. There should be 7 mils spacing between each intra
pair. The length for a pair of intra differential signals should be matched within 5 mils. The length for inter pairs
should be matched within 50mils. Bend smaller than 45 degrees should be avoided. The AC coupling capacitors for
the serial video inputs must be placed close to the GMCH, as shown in Figure 7.
CH7219
D0P 56
D0N 57
D1P 60
D1N 61
D2P 63
D2N 64
D3P 67
D3N 68
GMCH
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
C1 100nF
C2 100nF
C3 100nF
C4 100nF
C5 100nF
C6 100nF
C7 100nF
C8 100nF
DP Source
D0P 56
D0N 57
D1P 60
D1N 61
D2P 63
D2N 64
D3P 67
D3N 68
CH7219
C10 100nF ML0-
B3
ML0+
B2
ML3+
A2
ML3-
A3
ML2+
B11
ML2-
B10
ML1-
A10
ML1+
A11
C12 100nF
C14 100nF
C16 100nF
C18 100nF
C20 100nF
C22 100nF
C24 100nF
UFP_D Pin Assignment C
Type-C Connector
Figure 7: CH7219 DP Main Link Lane or USB Type-C DP Alt Mode Inputs
• AUXP and AUXN
These two pins are for Display Port AUX channel control or USB Type-C DP Alt Mode that accepts a half-duplex,
bi-directional AC-coupled differential signal. An AC coupling capacitor, 0.1μF recommended, must be placed on the
end as shown in Figure 8.
• HPD_DP
This output pin indicates whether the device is active or not. It also generates an interrupt pulse as defined by the
Display Port standard. Output voltage is 3.3V. A resistor, greater than 100KΩ, should be connected between this pin
and GND as shown in Figure 8.

CHRONTEL AN-B058
6 206-1000-058 Rev. 0.12023-10-25
U1
CH7219
AUXN 52
HPD_DP 49
AUXP 53
U2
GMCH
AUXN
HPDET
AUXP
C1 0.1uF
C2 0.1uF
R1
100K R2 100K
Source eDPSink
U3
CH7219
AUXN 52
HPD_DP 49
AUXP 53
U4
GMCH
AUXN
HPD_DP
AUXP
C3 0.1uF
C4 0.1uF
R3
100K R4 100K
Sink Source DP
C5 0.1uF
C6 0.1uF
R5
1M R6 1M R7
100KR8 100K
+3.3V +3.3V
U5
CH7219
AUXN 52
HPD_DP 49
AUXP 53
Sink
C7 0.1uF
C8 0.1uF
R10
1M R11 1M
+3.3V
U6
SBU1
A8
SBU2
B8
UFP_D Pin Assignment C
Type-C Connector
Figure 8: CH7219 AUX channel and HPD_DP
2.6 USB Type-C Signal Pins
• USB0_DN/P
The D+/- input of USB Type-C interface. These pin should be pulled low with 10K Ωor shorted to Ground directly if
unused.
• VBUS_DET
Voltage input 0~5V.
• Rd
USB Type-C Dead Battery Rd Resistor, Connect CC0_A or CC1_A to this pin to enable dead battery Rd on CC0_A
or CC1_A pin. It can be left open or pulled down to the ground if unused.
• CC0_A/VCONN/VCONN_DET
CC0_A Port A USB Type-C Configure Channel 0.
VCONN Connect this pin to VCONN pin of USB Type-C Plug Connector if CH7219 is used in VCONN Power
Accessory mode.
VCONN_DET USB VCONN Voltage Detection, Voltage input 2.7 ~ 5.5v
• Ra

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 7
Ra Resistor. When used in typeC accessory mode, this pin needs connect to CC0. It can be left open or pulled down
to the ground if unused.
• CC1_A
Port A USB Type-C Configure Channel 1
• GPIO5/CC0_B
General Purpose Input/output or Port B USB Type-C Configure Channel 0
• GPIO4/CC1_B
General Purpose Input/output or Port B USB Type-C Configure Channel 1
USB0_DN 5
USB0_DP 6
VBUS_DET 10
Rd1 37
CC0_A/Vconn/VCONN_DET 34
Ra 35
CC1_A 36
GPIO5/CC0_B 46
GPIO4/CC1_B 47
USB0_DN_A7
16
USB0_DP_A6
17
CC_A5
20
VCONN_B5
19
VBUS
18
USB Type-C
Wire Solder
R1 91K
R2 10K
Type-C Receptacle
CC1
A5
CC2
B5
Charging
USB0_DN 5
USB0_DP 6
VBUS_DET 10
Rd0 33
CC0_A/Vconn/VCONN_DET 34
Rd1 37
CC1_A 36
GPIO5/CC0_B 46
GPIO4/CC1_B 47
USB0_DN
A7, B7
USB0_DP
A6, B6
CC1
A5
CC2
B5
VBUS
A4, A9, B4, B9
USB Type-C Receptacle
UFP_D Assignment C
R3 91K
R4 10K
Type-C Receptacle
CC1
A5
CC2
B5
Charging
Receptacle
Plug
R5 0
Figure 9: CH7219 Plug and Receptacle Interface
2.7 HDMI Output
The TXCB/TXC, TX0B/TX0, TX1B/TX1, TX2B/TX2 signals are high frequency differential signals that need to be
routed with special precautions. Since those signals are differential, they must be routed in pairs.
2.7.1 Differential Pair Impedance
To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the
impedance target of 100Ω ± 10% for the differential data/clock traces. The restriction of this impedance target is to
prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired
by proper design of trace length, trace width, signal layer thicknes s, board dielectric, etc. The HDMI differential
pairs should be routed on the top layer directly to the HDMI connector pads if possible.
2.7.2 Trace Routing Length
To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and
bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. The CH7219
should be as close to the HDMI connector as possible.

CHRONTEL AN-B058
8 206-1000-058 Rev. 0.12023-10-25
2.7.3 Length Matching for Differential Pairs
The HDMI specifies the intra-pair skew and the inter-pair skew as in Table 2. The intra-pair skew is the maximum
allowable time difference on both low-to-high and high-to-low transitions between the true and complement signals.
The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions
between any two single-ended data signals that do not constitute a differential pair.
Table 2: Maximum Skews for the HDMI Transmitter
Skew Type
Maximum at Transmitter
Intra-Pair Skew
0.15 Tbit
Inter-Pair Skew
0.20 TPixel
Where Tbit is defined as the reciprocal of Data Transfer Rate and TPixel is defined as the reciprocal of Clock Rate.
Therefore, TPixelsis 10 times Tbit. In other words, the intra-pair length matching is much more stringent than the inter-
pair length matching.
It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should
occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a
pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be
within 100 mils.
Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for
instance, is electrically considered part of the pad itself.
2.7.4 ESD Protection for HDMI Interface
In order to minimize the hazardof ESD, a set of protection diodes are highly recommended for each HDMI
output (data and clock).
International standard EN 55024:1998 establishes 4kV as the common immunity requirement for contact discharges
in electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic
systems. International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 establishes the immunity testing and
measurement techniques.
System level ESD testing to International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 has confirmed that the
proper implementation of Chrontel recommended diode protection circuitry, using SEMTECH Rclamp0524P diode
array devices, will protect the CH7219 device from HDMI transmitter discharges of greater than 19kV (contact) and
20kV (air). The Rclamp0524P have a typical capacitance of only 0.30pF between I/O pins. This low capacitance
won’t bring too much bad effect on HDMI eye diagram test.
Figure 10 show the connection of HDMI connectors, including the recommended design of Rclamp0524P diode
array devices. HDMI connector is used to connect the CH7219 HDMI outputs.

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 9
TX2
TX2B
TX0B
TX0
R1
47K
TXCB
TXC
U1
HDMI TX (TYPE A)
TMDA Data2+
1GND1 2
TMDA Data2-
3TMDA Data1+ 4
GND2
5TMDA Data1- 6
TMDA Data0+
7GND3 8
TMDA Data0-
9TMDA Clock+ 10
GND4
11 TMDA Clock- 12
CEC
13 Reserved 14
SCL
15 SDA 16
DDC/CEC Ground
17 +5V Power 18
HPDET
19
Shield
20
Shield
21
Shield
22
Shield
23
TX1B
TX1
DDC_SDADDC_SCL
HPD_HM
GND
GND
GND
GND
GND
TX2B
TX2
TX1
TX1B
GND
TX2B
TX2
TX1
TX1B
GND
DDC_SDA DDC_SDA
DDC_SCL DDC_SCL
GND
U3
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10
GND
HPD_HMHPD_HM
TX0B
TX0 TX0
TX0B
TXC
TXCB TXCB
TXC
GND GND
U4
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10
VBUS5V
U2
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10
D1SM5817
Figure 10: The connection of the HDMI outputs
• HPD_HM
This output pin connects to the GND through a 47KΩ resistor. Refer to Figure 10 for the design example.
2.8 Thermal Exposed Pad Package
The CH7219 is available in a 68-pin QFN package with exposed thermal pad. The advantage of the exposed thermal
pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When properly
implemented, the exposed thermal pad package provides a means of reducing the thermal resistance of the CH7219.
Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed thermal pad of the package should be soldered to the PCB as shown in Figure 11.
Die
Exposed Pad
Solder
PCB
Pin
Figure 11: Cross-section of exposed thermal padpackage

CHRONTEL AN-B058
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3.0 REFERENCE DESIGN EXAMPLE
The following schematics are to be used as a CH7219 PCB design example only. It is not a complete design. Those
who are seriously doing an application design with the CH7219 and would like to have a complete reference design
schematic should contact Applications within Chrontel, Inc.
3.1 Schematics of Reference Design Example

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 11
PWR
DDC_SCL
VDD5_DDC
DDC_SDA
HDMI TX
R29
1.8K
1 2
R4
47K
HMTX2+
HMTX2-
R28
1.8K
1 2
HMTX0-
R22
47K
HMTX0+
HMTXC-
HMTXC+
U3
HDMI TX (TYPE A)
TMDA Data2+
1GND1 2
TMDA Data2-
3TMDA Data1+ 4
GND2
5TMDA Data1- 6
TMDA Data0+
7GND3 8
TMDA Data0-
9TMDA Clock+ 10
GND4
11 TMDA Clock- 12
CEC
13 Reserved 14
SCL
15 SDA 16
DDC/CEC Ground
17 +5V Power 18
HPDET
19
Shield
20
Shield
21
Shield
22
Shield
23
HMTX1-
HMTX1+
DDC_SDADDC_SCL
HPD_HMTX
RVBUS_DET
GNDS
GNDS
GNDS
GNDS
GNDS
HMTX2-
HMTX2+
HMTX1+
HMTX1-
GNDS
HMTX2-
HMTX2+
HMTX1+
HMTX1-
GNDS
DDC_SCL
CEC
GNDS
HPD_HMTX
HMTX0-
HMTX0+ HMTX0+
HMTX0-
HMTXC+
HMTXC- HMTXC-
HMTXC+
GNDS GNDS
USB0_DN
VBUS5V
D2P
D2N
D3P
D3N
Q1
DMG7401 Q2 DMG7401
RVBUS_CHARGEEN
USB0_DN
USB0_DP
DVDD_12
+3.3V
CHARGE_EN
PVBUS_DISCHARGE
C28
0.1uf
R23 1M
RVBUS_CHARGEEN
Q6
BSS138
1
32
R6
10K
R2
47K
VCONN
R14
0 1%
VCC
C17 0.1uF
L1 3.3uH
CC
SBU1
VCONN
C8
270pF
USB0_DP
C12
47pF
AVCC_33
VBUS
VDD5_DDC
C50
0.1uf
L5
FB
1 2
C48
10uF C49
0.1uf
U1
TypeC wire solder
RX2+_A11 10 VBUS
1
RX2-_A10 11
CC_A5
5TX2+_B2 12
SBU2_B8
4
TX2-_B3 13
SBU1_A8
7
RX1+_B11 16
TX1+_A2 14
RX1-_B10 17
TX1-_A3 15
GND
20
GND 18
USBDP_A6
9
VCONN_B5
6
USBDM_A7
8GND 19
VBUS
2
VBUS
3
SBU2
C52
0.1uf
PVBUS
PVBUS
PVBUS
C51
0.1uf
PVBUS
C2
100uF/35V
PVBUS
C5
22uf/35V
U7
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10
C23 0.1uF
U8
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10 U10
RClamp0524P
I/O 1
1
I/O 7 9 I/O 2
2
GND
3
I/O 3
4
I/O 4
5I/O 5 6
I/O 6 7
GND 8
I/O 8 10
R27
100K
D3 RED_LED
DDC_SCL
GNDS
HPD_HMTX
CEC
DDC_SDA
CHARGE_EN
D1N
D1P
C3
0.1uf
C7
0.1uf
C4
0.1uf
D0N
D0P
C1
0.1uf
R11
10K
C9 0.1uf
C10 0.1uf
C11 0.1uf
C14 0.1uf
VCC
C27
10uF
C37
10nF
C36
0.1uf C38 1nF
VDDS_12
HMTX2+ HMTX2- HMTX1+ HMTX1- HMTX0+ HMTX0-
AVCC_33 VDDPLL_12
HMTXC- HMTXC+
POWER
L3 2.2uH
R30 100K 1%
U9
SY8089
VIN
4SW 3
EN
1
GND
2
FB 5
PWR
R31
100K 1%
+1.2V
C32
10uf
C34
47uf
C33 22pF
+3.3V
D1SM5817
AVDD_12
C42
0.1uf
R20
2.2K
12
C43
10nF
R19
2.2K
1 2
C44
1nF
AVDD_12
C45
0.1uf C46 10nF C47 1nF
R21
10mR
12
+1.2V
C6
22uf/35V
VO-
C39
0.1uf
L4
FB
1 2
C35
10uF
DVDD_12
L6
FB
1 2
C53
10uF C55 0.1uf
C54
0.1uf
VDDPLL_12
C56
10uF C58 0.1uf
C57
0.1uf
L7
FB
1 2
PVBUS_DISCHARGE
VDDS_12
C59
10uF C60 0.1uf
L8
FB
1 2
C61
0.1uf
CC0_B
CC1_B
RVBUS
RVBUSRVBUS
RVBUS
D2N D2P
Receptacle For Charging
Charging control
R24
20K/NF
U5
CH7219
AVCC
2
XI/CK_25M
3
XO
4
USB0_DN
5
USB0_DP
6
USB1_DN
7
USB1_DP
8
AVCC5V
9
VBUS_DET
10
DVDD
11
DGND
12
RB
13
GPIO0
14
GPIO1
15
GPIO2
16
GPIO3
17
AVDDPLL
18
TXCB
19
TXC
20
VDDS
21
GNDS
22
TX0B
23
TX0
24
AVCC
25
TX1B
26
TX1
27
GNDS
28
VDDS
29
TX2B
30
TX2
31
CEC_HM
32
Rd0
33
CC0_A/Vconn/VCONN_DET
34
Ra 35
CC1_A 36
GPIO8 38
GPIO7 39
GPIO6 40
AVCC 41
DVDD 42
DGND 43
SPD0 44
SPC0 45
GPIO5/CC0_B 46
GPIO4/CC1_B 47
HPD_HM 48
HPD_DP 49
DDC_SDA 50
DDC_SCL 51
AUXN 52
AUXP 53
RBIAS 54
AVCCBG 55
D0P 56
D0N 57
AVDD 58
D1P 60
D1N 61
D2P 63
D2N 64
AVDD 65
D3P 67
D3N 68
VDDPLL
1
TPAD
69
Rd1 37
AVDD 59
GND 62
AVDD 66
J1
HEADER 3
1
2
3
Q5
BSS138
1
32
D1N D1P
AVDD_12
C40
10nF
SPC0
RVBUS_DET
C24
0.1uF/35V
C25
10uF/35V
PVBUS_DET
C26
10uF/35V
AVCC_33
C41
1nF
Aux
Y1
25MHz30ppm
1 3
4 2
C18
22pF C19
22pF
VBUS
R8
10K
+3.3V
R9
20K
R3
10K
Q3
BSS138 1
32
U4
JW3651
FB 5
CSN
15
VCC
13
VIN 2
CSP 1
SW2
10 SW1
9
BST2
11
EN 7
TEST
12
GND
14 OLIM 6
BST1 8
PGND 3
VO 4
CEC
CC
AVCC_33
DVDD_12
C20
0.1uf
C21
10uF
C22
10uF
R5
91K 1%
R7
10K 1%
SPD0
SPC0
CC0_B
CC1_B
HPD_HMTX
DDC_SDA
DDC_SCL
D2 SM5817
Q4
BSS138
1
32
VCONN
R10
10K
R1
100R
IIC Port
VBUS5V
AUXN SBU2
AUXP
+3.3V
VBUS5V
SBU1
C15 0.1uf
C16 0.1uf
R13 1M
R12 1M
R17 100K 1%
+3.3V
SPD0
U2
USB Type-C Receptacle
D+ B6
D- B7
SBU2 B8
Vbus B9
RX1+ B11
GND B12
RX1- B10
CC2 B5
Vbus B4
TX2- B3
TX2+ B2
GND B1
TX1+
A2
TX1-
A3
Vbus
A4
CC1
A5
D+
A6
D-
A7
SBU1
A8
Vbus
A9
RX2-
A10
RX2+
A11
GND
A12
GND
A1
s
H3
s
H4
s
H5
s
H6
IIC R33
6.8K
R32
6.8K
L2 2.2uH
R25 453K 1%
AUXN
AUXP
R18
1K 1%
U6
SY8089
VIN
4SW 3
EN
1
GND
2
FB 5
PWR
R26
100K 1%
+3.3V
C29
10uf C30 22pF
C31
22uf
AVCC_33 D0P
D0N D3N D3P
CEC
DDC_SDA
AVDD_12
VDDPLL_12
R16
22K 1%
R15
0 1%
C13
47pF
RVBUS
PVBUS_DET
Figure 12: CH7219Plug1 to 2 Reference schematic

CHRONTEL AN-B058
12 206-1000-058 Rev. 0.12023-10-25
3.2 Reference Board Preliminary BOM
Table 3: CH7219 Reference Design BOM List
Item
Quantity
Reference
Part
1
28
C1,C3,C4,C7,C9,C10,C11, C14,C15,C16,C17,C20,
C23,C28,C36,C39,C42,C45,C49,C50,C51,C52,C54,
C55,C57, C58,C60,C61
0.1uF
2
1
C2
100uF/35V
3
2
C5,C6
22uf/35V
4
1
C8
270pF
5
2
C12,C13
47pF
6
4
C18,C19,C30,C33
22pF
7
10
C21,C22,C27,C29,C32,C35, C48,C53,C56,C59
10uF
8
1
C24
0.1uF/35V
9
2
C25,C26
10uF/35V
10
1
C31
22uf
11
1
C34
47uf
12
4
C37,C40,C43,C46
10nF
13
4
C38,C41,C44,C47
1nF
14
2
D1,D2
SM5817
15
1
D3
RED_LED
16
1
J1
HEADER 3
17
1
L1
3.3uH
18
2
L2,L3
2.2uH
19
5
L4,L5,L6,L7,L8
FB
20
2
Q1,Q2
DMG7401
21
4
Q3,Q4,Q5,Q6
BSS138
22
1
R1
100R
23
3
R2,R4,R22
47K
24
5
R3,R6,R8,R10,R11
10K
25
1
R5
91K 1%
26
1
R7
10K 1%
27
1
R9
20K
28
3
R12,R13,R23
1M
29
2
R14,R15
0 1%
30
1
R16
22K 1%
31
4
R17,R26,R30,R31
100K 1%
32
1
R18
1K 1%
33
2
R19,R20
2.2K
34
1
R21
10mR
35
1
R24
20K/NF
36
1
R25
453K 1%
37
1
R27
100K
38
2
R28,R29
1.8K
39
2
R32,R33
6.8K

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 13
40
1
U1
TypeC wire solder
41
1
U2
USB Type-C Receptacle
42
1
U3
HDMI TX (TYPE A)
43
1
U4
JW3651
44
1
U5
CH7219
45
2
U6,U9
SY8089
46
3
U7,U8,U10
RClamp0524P
47
1
Y1
25MHz 30ppm

CHRONTEL AN-B058
14 206-1000-058 Rev. 0.12023-10-25
4.0 REVISION HISTORY
Table 4: Revisions
Rev.
#
Date
Section
Description
0.1
10/25/2023
All
Layout Guide and Design Guide for CH7219 release.

CHRONTEL AN-B058
206-1000-058 Rev. 0.1 2023-10-25 15
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