Cirrus Logic CS5374 User manual

Copyright  Cirrus Logic, Inc. 2010
(All Rights Reserved)
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Dual High-performance Amplifier & ΔΣ Modulator
Features
High Input Impedance Differential Amplifier
• Ultra-low input bias: < 1 pA
• Max signal amplitude: 5 Vpp differential
Fourth Order Delta-Sigma (ΔΣ) Modulator
• Signal Bandwidth: DC to 2 kHz
• Common mode rejection: 110 dB CMRR
Differential Analog Input, Digital ΔΣ Output
• Multiplexed inputs: INA, INB, 800Ωtermination
• Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x
Excellent Amplifier Noise Performance
•1.5μVpp between 0.1 Hz and 10 Hz
• 11 nV / √Hz from 200 Hz to 2 kHz
High Modulator Dynamic Range
• 126 dB SNR @ 215 Hz BW (2 ms sampling)
• 123 dB SNR @ 430 Hz BW (1 ms sampling)
Low Total Harmonic Distortion
• –118 dB THD typical (0.000126%)
• –108 dB THD maximum (0.0004%)
Low Power Consumption
• Normal operation: 6.5 mA per channel
• Power down: 15 μA per channel max
Dual Power Supply Configuration
• VA+ = +2.5 V; VA– = –2.5 V; VD = +3.3 V
Description
The CS5374 combines two marine seismic analog mea-
surement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a high
input impedance programmable gain differential amplifi-
er that buffers analog signals into a high-performance,
fourth-order ΔΣ modulator. The low-noise ΔΣ modulator
converts the analog signal into a one-bit serial bit stream
suitable for the CS5376A digital filter.
Each amplifier has two sets of external inputs, INA and
INB, to simplify system design as inputs from a hydro-
phone sensor or the CS4373A test DAC. An internal
800Ωtermination can also be selected for noise tests.
Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x,
32x, 64x) and match the CS4373A test DAC output at-
tenuation settings for full-scale testing at all gain ranges.
Both the input multiplexer and gain are set by registers
accessed through a standard SPI™ port.
Each fourth-order ΔΣ modulator has very high dynamic
range combined with low total harmonic distortion and
low power consumption. It converts differential analog
signals from the amplifier to an oversampled ΔΣ serial bit
stream which is decimated by the CS5376A digital filter
to a 24-bit output at the final output word rate.
ORDERING INFORMATION
See page 43.
INA1+
INB1+
MUX1
MUX2
INB1-
INA1-
GUARD1
+
-
-
+
400 Ω400 Ω
INA2+
INB2+
INB2-
INA2-
+
-
-
+
400 Ω400 Ω
Reset, Clock,
and
Synchronization
INR1- VA+
MFLAG1
MCLK
MSYNC
MFLAG2
MDATA2
GAIN1GAIN2
GUARD2 INR2- INR2+
4th Order
Modulator
4th Order
Modulator
INF1- INF1+INR1+
RST
SPITM Serial
Interface
SDI
SDO
SCLK
CS
INF2+INF2-OUT2-OUT2+
OUT1+ OUT1-
CS5374
VA-
GND
VD
VREF-VREF+
VA+
VA-
MDATA1
SEP '10
DS862F2
CS5374

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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................ 4
ABSOLUTE MAXIMUM RATINGS .......................................................................................... 4
THERMAL CHARACTERISTICS ............................................................................................. 5
ANALOG CHARACTERISTICS ............................................................................................... 5
PERFORMANCE SPECIFICATIONS ...................................................................................... 7
CHANNEL PERFORMANCE PLOTS ...................................................................................... 9
DIGITAL CHARACTERISTICS .............................................................................................. 10
SPI™ INTERFACE TIMING (EXTERNAL MASTER) ............................................................ 12
POWER SUPPLY CHARACTERISTICS ............................................................................... 13
2. GENERAL DESCRIPTION..................................................................................................... 14
3. AMPLIFIER OPERATION ...................................................................................................... 16
3.1 Amplifier Inputs — INA, INB.......................................................................................... 16
3.1.1 Multiplexer Settings — MUX ............................................................................... 16
3.1.2 Gain Settings — GAIN ........................................................................................ 16
3.2 Amplifier Outputs — OUTR, OUTF............................................................................... 16
3.2.1 Guard Output — GUARD.................................................................................... 16
3.3 Differential Signals ........................................................................................................ 17
4. MODULATOR OPERATION .................................................................................................. 18
4.1 Modulator Anti-Alias Filter............................................................................................. 18
4.2 Modulator Inputs — INR, INF........................................................................................ 19
4.2.1 Modulator Input Impedance ................................................................................ 19
4.2.2 Modulator Idle Tones — OFST ........................................................................... 19
4.3 Modulator Output — MDATA ........................................................................................ 19
4.3.1 Modulator One’s Density..................................................................................... 19
4.3.2 Decimated 24-bit Output ..................................................................................... 19
4.4 Modulator Stability — MFLAG....................................................................................... 20
4.5 Modulator Clock Input — MCLK.................................................................................... 20
4.6 Modulator Synchronization — MSYNC......................................................................... 20
5. SPITM SERIAL PORT ............................................................................................................. 21
5.1 SPI Pin Descriptions ..................................................................................................... 21
5.2 SPI Serial Transactions................................................................................................. 21
5.3 SPI Registers................................................................................................................23
5.3.1 VERSION — 0x00............................................................................................... 23
5.3.2 AMP1CFG — 0x01 ............................................................................................. 23
5.3.3 AMP2CFG — 0x02 ............................................................................................. 23
5.3.4 ADCCFG — 0x03................................................................................................ 24
5.3.5 PWRCFG — 0x04............................................................................................... 24
5.4 Example: CS5374 Configuration by an External SPI Master........................................ 24
5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port ...................................... 25
5.5.1 CS5376A SPI 1 Transactions ............................................................................. 25
6. POWER MODES .................................................................................................................... 29
6.1 Normal Operation.......................................................................................................... 29
6.2 Power Down, MCLK Enabled........................................................................................ 29
6.3 Power Down, MCLK Disabled....................................................................................... 29
7. VOLTAGE REFERENCE ....................................................................................................... 30
7.1 VREF Power Supply ..................................................................................................... 30
7.2 VREF RC Filter ............................................................................................................. 30
7.3 VREF PCB Routing....................................................................................................... 30
7.4 VREF Input Impedance................................................................................................. 30
7.5 VREF Accuracy............................................................................................................. 31
8. POWER SUPPLIES .............................................................................................................. 32
8.1 Analog Power Supplies................................................................................................. 32
8.2 Digital Power Supply..................................................................................................... 32
8.3 Power Supply Bypassing .............................................................................................. 32

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8.4 PCB Layers and Routing............................................................................................... 33
8.5 Power Supply Rejection................................................................................................ 33
8.6 SCR Latch-up Considerations....................................................................................... 33
8.7 DC-DC Converters........................................................................................................ 33
9. SPITM REGISTER SUMMARY................................................................................................ 34
9.1 VERSION: 0x00 ............................................................................................................ 35
9.2 AMP1CFG: 0x01........................................................................................................... 36
9.3 AMP2CFG: 0x02........................................................................................................... 37
9.4 ADCCFG: 0x03 ............................................................................................................. 38
9.5 PWRCFG: 0x04 ............................................................................................................ 38
10. PIN DESCRIPTIONS ............................................................................................................. 40
11. PACKAGE DIMENSIONS ...................................................................................................... 42
12. ORDERING INFORMATION ................................................................................................. 43
13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........................... 43
14. REVISION HISTORY ............................................................................................................44
LIST OF FIGURES
Figure 1. External Anti-alias Filter Components.............................................................................. 6
Figure 2. CS5374 Amplifier Noise Performance............................................................................. 7
Figure 3. CS5374 Noise Performance (1x Gain) ........................................................................... 9
Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance ................................................... 9
Figure 5. Digital Rise and Fall Times SYNC from external system............................................... 10
Figure 6. System Synchronization Diagram.................................................................................. 10
Figure 7. MCLK / MSYNC Timing Detail....................................................................................... 11
Figure 8. SDI Write Timing in SPI Slave Mode ............................................................................. 12
Figure 9. SDO Read Timing in SPI Slave Mode........................................................................... 12
Figure 10. CS5374 System Block Diagram................................................................................... 14
Figure 11. CS5374 Connection Diagram...................................................................................... 15
Figure 12. CS5374 to CS5376A Digital Interface.......................................................................... 15
Figure 13. CS5374 Amplifier Block Diagram................................................................................. 16
Figure 14. CS5374 Modulator Block Diagram............................................................................... 18
Figure 15. SPI Interface Block Diagram........................................................................................ 21
Figure 16. CS5374 (Slave) Serial Transactions with CS5376A (Master)...................................... 22
Figure 17. Power Mode Diagram.................................................................................................. 29
Figure 18. Voltage Reference Circuit............................................................................................30
Figure 19. Power Supply Diagram................................................................................................ 32
Figure 20. Hardware Version ID Register VERSION.................................................................... 35
Figure 21. Amplifier 1 Configuration Register AMP1CFG............................................................. 36
Figure 22. Amplifier 2 Configuration Register AMP2CFG............................................................. 37
Figure 23. Modulator 1 & 2 Configuration Register ADCCFG....................................................... 38
Figure 24. Power Configuration Register PWRCFG..................................................................... 39
LIST OF TABLES
Table 1. 24-bit Output Coding ...................................................................................................... 20
Table 2. SPI Configuration Registers ...........................................................................................23
Table 3. Digital Selections for Gain and Input Mux Control ......................................................... 23
Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers .... 24
Table 5. Example CS5376A SPI 1 Transactions to Write and Read the GPCFG0 Register ....... 25
Table 6. Example CS5376A SPI 1 Transactions to Write the CS5374 AMP1CFG Register ....... 26
Table 7. Example CS5376A SPI 1 Transactions to Write AMP2CFG and ADCCFG .................. 27
Table 8. Example CS5376A SPI 1 Transactions to Write the CS5374 PWRCFG Register ......... 28

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1. CHARACTERISTICS AND SPECIFICATIONS
• Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions.
• Typical performance characteristics and specifications are derived from measurements taken at nom-
inal supply voltages and TA= 25°C.
• GND = 0 V, all voltages with respect to 0 V.
• Device connected as shown in Figure 11 and Figure 12 unless otherwise noted.
SPECIFIED OPERATING CONDITIONS
Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions.
2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance.
3. Channel-to-channel gain accuracy is directly proportional to the voltage reference absolute accuracy.
4. VREF inputs must satisfy: VA- ≤VREF- < VREF+ ≤VA+.
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 5. Transient currents up to 100mA will not cause SCR latch-up.
6. Includes continuous over-voltage conditions on the analog input pins.
Parameter Symbol Min Nom Max Unit
Bipolar Power Supplies
Positive Analog +2% VA+ 2.45 2.50 2.55 V
Negative Analog (Note 1) +2% VA- -2.45 -2.50 -2.55 V
Positive Digital +3% VD 3.20 3.30 3.40 V
Voltage Reference
[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V
Thermal
Ambient Operating Temperature -CNZ TA-10 25 70 °C
Parameter Symbol Min Max Unit
DC Power Supplies Positive Analog
Negative Analog
Digital
VA+
VA-
VD
-0.3
-6.8
-0.3
6.8
0.3
6.8
V
V
V
Analog Supply Differential [(VA+) - (VA-)] VADIFF -6.8V
Digital Supply Differential [(VD) - (VA-)] VDDIFF -6.8V
Input Current, Any Pin Except Supplies (Note 5, 6)I
IN -+10 mA
Input Current, Power Supplies (Note 5)I
PWR -+50 mA
Output Current (Note 5)I
OUT -+25 mA
Power Dissipation PD - 500 mW
Analog Input Voltages VINA (VA-)-0.5 (VA+)+0.5 V
Digital Input Voltages VIND -0.5 (VD)+0.5 V
Storage Temperature Range TSTG -65 150 °C

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THERMAL CHARACTERISTICS
ANALOG CHARACTERISTICS
Notes: 7. Common mode signals pass through the differential amplifier architecture and are rejected by the
modulator CMRR.
8. Output impedance characteristics are approximate and can vary up to ±30% depending on process
parameters.
Parameter Symbol Min Typ Max Unit
Ambient Operating Temperature TA-10 - 70 °C
Storage Temperature Range TSTR -65 - 150 °C
Allowable Junction Temperature TJCT --125°C
Junction to Ambient Thermal Impedance (4-layer PCB) θJA -26-°C/W
Parameter Symbol Min Typ Max Unit
Amplifier Inputs
Signal Frequencies BW DC - 2000 Hz
Differential Gain GAIN x1 - x64
Common Mode Gain (Note 7) GAINCM -x1-
Common Mode Voltage Vcm -(VA-)+2.5 -V
Voltage Range (Signal + Vcm) x1
x2 - x64 VIN (VA-)+0.7
(VA-)+0.7 -
-(VA+)-1.25
(VA+)-1.75 V
Full Scale Differential Input x1
x2
x4
x8
x16
x32
x64
VINFS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
2.5
1.25
625
312.5
156.25
78.125
Vpp
Vpp
Vpp
mVpp
mVpp
mVpp
mVpp
Differential Input Impedance ZINDIFF -1,20- TΩ, pF
Common Mode Input Impedance ZINCM - 0.5, 40 - TΩ, pF
Input Bias Current IIN -140pA
Amplifier Outputs
Full Scale Output, Differential VOUT --5V
pp
Output Voltage Range (Signal + Vcm) VRNG (VA-)+0.5 -(VA+)-0.5 V
Output Impedance (Note 8)Z
OUT -40- Ω
Output Impedance Drift (Note 8)Z
TC -0.38- Ω/°C
Output Current IOUT --+25 mA
Load Capacitance CL--100nF
Guard Outputs
Guard Output Voltage VGUARD -V
cm -V
Guard Output Impedance (Note 8)ZG
OUT -500- Ω
Guard Output Current IGOUT --40μA
Guard Load Capacitance CGL--100pF

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6
ANALOG CHARACTERISTICS (CONT.)
Notes: 9. The upper bandwidth limit is determined by the selected digital filter cut-off frequency.
10. Anti-alias capacitors are discrete external components and must be of good quality (C0G, NPO, poly).
Poor-quality capacitors will degrade total harmonic distortion (THD) performance. See Figure 1 for
external anti-alias filter connections.
11. Maximum integrated noise over the measurement bandwidth forthe voltage reference device attached
to the VREF inputs.
Parameter Symbol Min Typ Max Unit
Modulator Inputs
Input Signal Frequencies (Note 9) VBW DC - 2000 Hz
Full-scale Differential AC Input VAC --5V
pp
Full-scale Differential DC Input VDC -2.5 - 2.5 VDC
Input Common Mode Voltage VCM -(VA-)+2.5 -V
Input Voltage Range (Vcm ±Signal) V
RNG (VA-)+0.7 -(VA+)-1.25 V
Differential Input Impedance INR±
INF± ZDIFINR
ZDIFINF
-
-20 1- -kΩ MΩ
Single-ended Input Impedance INR±
INF± ZSEINR
ZSEINF
-
-40 2- -kΩ MΩ
External Anti-alias Filter Series Resistance
(Note 10) Differential Capacitance RAA
CDIFF
-
-680 20 - -Ω nF
VREF Inputs
[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V
VREF Input Current VREFII -120- µA
VREF Input Noise (Note 11)VREF
IN --1µV rms
MODULATOR
INR+
INF+
INF-
INR-
20nF
C0G 20nF C0G
680
AMPLIFIER
OUT+
OUT-
680
680
680
CS5374
Figure 1. External Anti-alias Filter Components

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PERFORMANCE SPECIFICATIONS
Notes: 12. Dynamic Range defined as 20 log [(RMS full scale) / (RMS idle noise)] where idle noise is measured
with the amplifier input terminated. Dynamic Range is dominated by high-frequency quantization noise
at the 1/4 ms rate and amplifier noise at high gain.
13. Tested with a 31.25 Hz sine wave at 1 ms sampling rate and -1 dB amplitude.
Parameter Symbol Min Typ Max Unit
Amplifier Noise
Voltage Noise f0= 0.1 Hz to 10 Hz VNPP -1.5 3 μVpp
Voltage Noise Density f0= 200 Hz to 2 kHz VND-11 14
Current Noise Density IND-20 -
Channel Dynamic Range
Dynamic Range (1/4 ms) DC to 1720 Hz
(1x Gain, Multiple OWRs) (1/2 ms) DC to 860 Hz
(Note 9, 12) (1ms)DCto 430Hz
(2 ms) DC to 215 Hz
(4 ms) DC to 108 Hz
(8 ms) DC to 54 Hz
(16 ms) DC to 27 Hz
SNR -
-
121
-
-
-
-
105
120
123
126
129
131
135
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
Dynamic Range 1x
(Multiple Gains, 1 ms OWR) 2x
(Note 9, 12)3x
8x
16x
32x
64x
SNR 121
-
-
-
-
-
-
123
122
120
116
111
105
98
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
Channel Distortion
Total Harmonic Distortion 1x
(Note 13)2x
4x
8x
16x
32x
64x
THD
-
-
-
-
-
-
-
-118
-119
-119
-119
-118
-115
-112
-108
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
nV/ Hz
fA/ Hz
0
5
10
15
20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
CS5374 Amplifier In-Band Noise
Noise Density (nV/rtHz)
0
100
200
300
400
0.1 1 10 100 1k
Frequency (Hz)
CS5374 Amplifier Wide Band Noise
Noise Density (nV/rtHz)
10k 100k 1M
Figure 2. CS5374 Amplifier Noise Performance

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8
PERFORMANCE SPECIFICATIONS (CONT.)
Notes: 14. Channel Gain is the nominal full-scale 24-bit output code from the CS5376A digital filter for a 5 VPP
differential signal into the CS5374 analog inputs at 1x gain. Value is offset corrected.
15. Absolute gain accuracy tests the matching of 1x gain across multiple CS5374 channels in a system.
16. Relative gain accuracy tests the tracking of 2x, 4x, 8x, 16x, 32x, 64x gain relative to 1x gain on a single
CS5374 channel.
17. Specification is for the parameter over the specified temperature range and is for the CS5374 device
only. It does not include the effects of external components.
18. Offset voltage is tested with the amplifier inputs connected to the internal 800 Ωtermination.
19. The offset after calibration specification is measured from the digitally calibrated output codes of the
CS5376A digital filter.
20. Offset calibration is performed in the CS5376A digital filter and includes the full-scale signal range.
Parameter Symbol
CS5374
UnitMin Typ Max
Channel Gain Accuracy
Channel Gain, Offset Corrected (Note 3, 14)GAIN
LSB -6101194
0xA2E736 - -6101194 0x5D18CA LSB
LSB
Absolute Gain Accuracy (Note 3, 15)GAIN
ABS -±1+2%
Relative Gain Accuracy 2x
(Note 16)4x
8x
16x
32x
64x
GAINREL
-0.3
-
-
-
-
-
-0.1
-0.1
0.1
0.4
0.4
0.3
0.1
-
-
-
-
-
%
%
%
%
%
%
Gain Drift (Note 17) GAINTC -25-ppm/°C
Channel Offset Accuracy
Amplifier Offset Voltage, Input Referred (Note 18)OFST
AMP - ±250 ±750 µV
Amplifier Offset Drift, Input Referred (Note 17)OFST
ATC -0.3-µV/°C
Modulator Offset Voltage, Differential (OFST =1) OFST
MOD -±1- mV
Modulator Offset Voltage, Channel 1 (OFST =0) OFST
MOD1 --60- mV
Modulator Offset Voltage, Channel 2 (OFST =0) OFST
MOD2 --35- mV
Modulator Offset Drift (Note 17)OFST
MTC -1-µV/°C
Offset After Calibration (Note 19)OFST
CAL -±1- μV
Offset Calibration Range (Note 20)OFST
RNG -100- %FS
Channel CMRR and Crosstalk
Common Mode Rejection Ratio CMRR - 110 - dB
Crosstalk, Amplifier Multiplexed Inputs CXTMI --130- dB
Crosstalk, Channel-to-Channel CXTCC --130- dB

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9
CHANNEL PERFORMANCE PLOTS
Figure 3. CS5374 Noise Performance (1x Gain)
Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance

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10
DIGITAL CHARACTERISTICS
Notes: 21. Device is intended to be driven with CMOS logic levels.
22. Guaranteed by design and/or characterization.
Parameter Symbol Min Typ Max Unit
Digital Inputs
High-level Input Voltage (Note 21)V
IH 0.6*VD - VD V
Low-level Input Voltage (Note 21)V
IL 0.0 - 0.8 V
Input Leakage Current IIN -±1±10μA
Digital Input Capacitance CIN -9- pF
Input Rise Times Except MCLK tRISE --100ns
Input Fall Times Except MCLK tFALL --100ns
Digital Outputs
High-level Output Voltage, Iout =-40μAV
OH VD - 0.3 - - V
Low-level Output Voltage, Iout =40μAV
OL --0.3V
High-Z Leakage Current IOZ -±1±10μA
Digital Output Capacitance COUT -9- pF
Output Rise Times (Note 22) tRISE --100ns
Output Fall Times (Note 22) tFALL --100ns
0.9 * VD
0.1 * VD
tfall trise
Figure 5. Digital Rise and Fall Times SYNC from external system.
MCLK
MSYNC
t
MDATA
TDATA
0
SYNC
MFLAG
Figure 6. System Synchronization Diagram
SYNC from External. MCLK, MSYNC, TDATA from CS5376A. MDATA, MFLAG from CS5374.

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DIGITAL CHARACTERISTICS (CONT.)
Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically
enters a power-down state. See Power Supply Characteristics for typical power-down timing.
24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,
synchronization instant (t0) is on the next MCLK rising edge.
25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.
Parameter Symbol Min Typ Max Unit
Master Clock Input
MCLK Frequency (Note 23)f
MCLK - 2.048 - MHz
MCLK Duty Cycle MCLKDTC 40 - 60 %
MCLK Rise Time tRISE - - 50 ns
MCLK Fall Time tFALL - - 50 ns
MCLK Jitter (in-band or aliased in-band) MCLKIBJ --300ps
MCLK Jitter (out-of-band) MCLKOBJ --1 ns
Master Sync Input
MSYNC Setup Time to MCLK Falling (Note 24)t
MSS 20 366 - ns
MSYNC Period (Note 24)t
MSYNC 40 976 - ns
MSYNC Hold Time after MCLK Falling (Note 24)t
MSH 20 610 - ns
MDATA Output
MDATA Output Bit Rate fMDATA -512-kbits/s
MDATA Output One’s Density Range (Note 22)MDAT
1D 14 - 86 %
Full-scale Output Code, Offset Corrected (Note 25)MDAT
FS 0xA2E736 - 0x5D18CA
MCLK
MSYNC t0
tMSS 1 / fMCLK
tMSYNC
tMSH
MDATA
MFLAG
1 / fMDATA
Figure 7. MCLK / MSYNC Timing Detail

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SPI™ INTERFACE TIMING (EXTERNAL MASTER)
Parameter Symbol Min Typ Max Unit
SDI Write Timing
CS Enable to Valid Latch Clock t160 - - ns
Data Set-up Time Prior to SCK Rising t260 - - ns
Data Hold Time After SCK Rising t360 - - ns
SCK High Time t4120 - - ns
SCK Low Time t5120 - - ns
SCK Falling Prior to CS Disable t660 - - ns
SDO Read Timing
SCK Falling to New Data Bit t7- - 90 ns
SCK High Time t8120 - - ns
SCK Low Time t9120 - - ns
SCK Falling Hold Time Prior to CS Disable t10 60 - - ns
MSB MSB - 1 LSB
t6 t5 t4 t3 t2 t1
CS
SDI
SCK
Figure 8. SDI Write Timing in SPI Slave Mode
MSB MSB - 1 LSB
t9 t8
t7
CS
SDO
SCK
t10
Figure 9. SDO Read Timing in SPI Slave Mode

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POWER SUPPLY CHARACTERISTICS
Notes: 26. All outputs unloaded. Digital inputs forced to VD or GND respectively. Amplifier inputs connected to the
800 Ωinternal termination.
Parameter Symbol Min Typ Max Unit
Power Supply Current, ch1 + ch2 combined
Analog Power Supply Current (Note 26)I
A-1316mA
Digital Power Supply Current (Note 26)I
D-50100μA
Power Supply Current, ch1 or ch2 only
Analog Power Supply Current (Note 26)I
A-6.58 mA
Digital Power Supply Current (Note 26)I
D-2550 μA
Power Down Current, MCLK enabled
Analog Power Supply Current (Note 26)I
A- 150 250 μA
Digital Power Supply Current (Note 26)I
D-1075 μA
Power Down Current, MCLK disabled
Analog Power Supply Current (Note 26)I
A-215μA
Digital Power Supply Current (Note 26)I
D-115μA
Power Down Timing (after MCLK disabled) (Note 22)PD
TC -40- μS
Power Supply Rejection
Power Supply Rejection Ratio (Note 22)PSRR - 100 - dB

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14
2. GENERAL DESCRIPTION
The CS5374 combines two marine seismic analog
measurement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a
high input impedance programmable gain differen-
tial amplifier that buffers analog signals into a
high-performance, fourth-order ΔΣ modulator. The
low-noise ΔΣ modulator converts the analog signal
into a one-bit serial bit stream suitable for the
CS5376A digital filter.
Each amplifier has two sets of external inputs, INA
and INB, to simplify system design as inputs from
a hydrophone sensor or the CS4373A test DAC. An
internal 800 Ωtermination can also be selected for
noise tests. Gain settings are binary weighted (1x,
2x, 4x, 8x, 16x, 32x, 64x) and match the CS4373A
test DAC output attenuation settings for full-scale
testing at all gain ranges. Both the input multiplex-
er and gain are set by registers accessed through a
standard SPI™ port.
Each fourth-order ΔΣ modulator has very high dy-
namic range combined with low total harmonic dis-
tortion and low power consumption. It converts
differential analog signals from the amplifier to an
oversampled ΔΣ serial bit stream which is decimat-
ed by the CS5376A digital filter to a 24-bit output
at the final output word rate.
Figure 10 shows the system-level architecture of a
4-channel acquisition system using two CS5374,
one CS5376A digital filter and one CS4373A test
DAC.
Figure 11 and Figure 12 shows connection dia-
grams for the CS5374 device when connected to
the CS5376A digital filter.
Hydrophone
Sensor
Hydrophone
Sensor
Hydrophone
Sensor
Hydrophone
Sensor
DS
Modulator
Digital Filter
CS5376A
Test
DAC
Microcontroller
or
Configuration
EEPROM
System
Telemetry
AMP
CS4373A
CS5374
DS
Modulator
AMP
M
U
X
DS
Modulator
AMP
M
U
X
CS5374
DS
Modulator
AMP
M
U
X
M
U
X
Figure 10. CS5374 System Block Diagram

CS5374
CS5374
15
Figure 11. CS5374 Connection Diagram
A
INA1+
INA1-
MUX1
MUX2
INB1-
INB1+
GUAR D1
+
-
-
+
400 Ω400 Ω
INB2+
INB2-
INA2-
INA2+
+
-
-
+
400 Ω400 Ω
Reset, Clock, and
Synchronization
INR1-
VA+
MFLAG1
MDATA1
MCLK
MSYNC
MFLAG2
MDATA2
GAIN1GAIN2
GUARD2 INR2-
INR2+
4
th
Order
ΔΣ Modulator
4
th
Order
ΔΣ Modulator
INF1-
INF1+ INR1+
RST
SPITM Serial
Communications
Interface
SDI
SDO
SCLK
CS
INF2+
INF2-
OUT2-OUT2+
OUT1+ OUT1-
CS5374
VA-
GND
VD+
VREF-VREF+
VA+
VA-
Hydrophone
Sensor
Hydrophone
Sensor
VA-
0.1
VA+
0.1 μF
μF
Test
DAC
CS4373A
0.02
C0G
0.02
C0 G
680
680
680
680
μFμ
Ω
Ω
Ω
Ω
F
0.02
C0G
0.02
C0G
680
680
680
680
μFμ
Ω
Ω
Ω
F
Ω
VA-
0.1
VA+
0.1μF
μF
0.01 μF
2.5V
Precision
Voltage
Reference
To CS5376A
Digital Control
Figure 12. CS5374 to CS5376A Digital Interface
Reset, Clock, and
Synchronization
MFLAG1
MDATA1
MCLK
MSYNC
MFLAG2
MDATA2
4
th
Order
ΔΣ Modulator
4
th
Order
ΔΣ Modulator
RST
SPI
TM
Serial
Communications
Interface
SDI
SDO
SCLK
CS
CS5374
MSYNC
MCLK Clock and
Synchronization
Modulator Data
Interface
SPI 2
Serial Peripheral
Interface2
RESET
MFLAG1
MDATA1
MFLAG2
MDATA2
SI1
SO
SCK2
CS0
CS5376A
EXTERNAL RESET
CONTROLLER

CS5374
CS5374
16
3. AMPLIFIER OPERATION
The CS5374 high-impedance, low-noise CMOS
differential input, differential output amplifiers are
optimized for precision analog signals between DC
and 2 kHz. They have multiplexed inputs and pro-
grammable gains of 1x, 2x, 4x, 8x, 16x, 32x, and
64x. The performance of this amplifier makes it
ideal for low-frequency, high-dynamic-range ap-
plications requiring low distortion and minimal
power consumption.
3.1 Amplifier Inputs — INA, INB
The amplifier analog inputs are designed for high-
impedance differential hydrophone sensors and so
have very low input bias below 1 pA.
3.1.1 Multiplexer Settings — MUX
Input multiplexing simplifies system connections
by providing separate inputs for a sensor and test
DAC (INA, INB) as well as an internal termination
for noise tests. The multiplexer determines which
input is connected to the amplifier, and is set
through internal configuration registers accessed
through the SPI port, see the “SPITM Register Sum-
mary” on page 34 for more information.
Although a mux selection is provided to enable the
INA and INB switches simultaneously, significant
current should not be driven through them in this
mode. The CS5374 mux switches will maintain
good linearity only with minimal signal current.
3.1.2 Gain Settings — GAIN
The CS5374 supports gain ranges of 1x, 2x, 4,x 8x,
16x, 32x, and 64x. Amplifier gain is selected using
internal configuration registers accessed through
the SPI port, see the “SPITM Register Summary”
on page 34 for more information.
3.2 Amplifier Outputs — OUTR, OUTF
The amplifier analog outputs are externally sepa-
rated into rough / fine charge signals to connect
into the modulator inputs. Each differential output
requires two series resistors and a differential ca-
pacitor to create the modulator anti-alias RC filter.
3.2.1 Guard Output — GUARD
The GUARD pin outputs the common mode volt-
age of the selected analog signal input. It can be
used to drive the cable shield between a high-im-
pedance sensor and the amplifier inputs. Driving
the cable shield with the analog signal common
mode voltage minimizes leakage and improves sig-
nal integrity from high-impedance sensors.
The GUARD output is defined as the midpoint
voltage between the + and – halves of the currently
INA1+
INB1+
MUX1
INB1-
INA1-
GUARD1
+
-
-
+
400 Ω400 Ω
GAIN1
OUT1+ OUT1-
Figure 13. CS5374 Amplifier Block Diagram

CS5374
CS5374
17
selected differential input signal, and will vary as
the signal common mode varies. The GUARD out-
put will not drive a significant load, as it can only
provide a shielding voltage.
3.3 Differential Signals
Analog signals into and out of the amplifiers are
differential, consisting of two halves with equal but
opposite magnitude varying about a common mode
voltage.
A full-scale 5 Vpp differential signal centered on a
–0.15 V common mode can have:
SIG+ = –0.15 V + 1.25 V = 1.1 V
SIG– = –0.15 V – 1.25 V = –1.4 V
SIG+ is +2.5 V relative to SIG-
For the reverse case:
SIG+ = –0.15 V – 1.25 V = –1.4 V
SIG– = –0.15 V + 1.25 V = 1.1 V
SIG+ is –2.5 V relative to SIG-
The total swing for SIG+ relative to SIG– is
(+2.5 V) – (–2.5 V) = 5 Vpp. A similar calculation
can be done for SIG– relative to SIG+. Note that a
5V
pp differential signal centered on a –0.15 V
common mode voltage never exceeds 1.1 V and
never drops below –1.4 V on either half of the sig-
nal.
By definition, differential voltages are to be mea-
sured with respect to the opposite half, not relative
to ground. A multi-meter differentially measuring
between SIG+ and SIG– in the above example
would properly read 1.767 Vrms, or 5 Vpp.

CS5374
CS5374
18
4. MODULATOR OPERATION
The CS5374 modulators are fourth-order ΔΣ type
optimized for extremely high-resolution measure-
ment of signals between DC and 2000 Hz. When
combined with the internal differential amplifiers,
the CS4373A test DAC and CS5376A digital filter,
a small, low-power, self-testing, high-accuracy,
multi-channel measurement system results.
The modulators have high dynamic range and low
total harmonic distortion with very low power con-
sumption. They are optimized for extremely high-
resolution measurement of 5 Vp-p or smaller differ-
ential signals. They convert analog input signals
from the differential amplifiers to an oversampled
serial bit stream which is then passed to the digital
filter.
The companion CS5376A digital filter generates
the clock and synchronization inputs for the modu-
lators while receiving the one-bit data and over-
range flag outputs. The digital filter decimates the
modulator’s oversampled output bit stream to a
high-resolution, 24-bit output at the final selected
output word rate.
4.1 Modulator Anti-Alias Filter
The modulator inputs are required to be bandwidth
limited to ensure modulator loop stability and pre-
vent high-frequency signals from aliasing into the
measurement bandwidth. The use of simple, sin-
gle-pole, differential, low-pass RC filters across
the INR± and INF± inputs ensures high-frequency
signals are rejected before they can alias into the
measurement bandwidth.
The approximate –3 dB corner of the input anti-
alias filter is nominally set to the internal analog
sampling rate divided by 64, which itself is a divi-
sion by 4 of the MCLK rate.
Figure 1 on page 6 illustrates the CS5374 amplifi-
er-to-modulator analog connections with input
anti-alias filter components. Filter components on
the rough and fine pins should be identical values
for optimum performance, with the capacitor val-
ues a minimum of 0.02 μF. The rough input can use
either X7R or C0G-type capacitors, while the fine
input requires C0G-type capacitors for optimal lin-
earity. Using X7R-type capacitors on the fine ana-
log inputs will significantly degrade total harmonic
distortion performance.
Reset, Clock,
and
Synchronization
INR1- VREF-
MFLAG1
MCLK
MSYNC
4th Order
Modulator
INF1- INF1+INR1+
RST
VREF+
MDATA1
Figure 14. CS5374 Modulator Block Diagram
• MCLK Frequency = 2.048 MHz
• Sampling Frequency = MCLK / 4 = 512 kHz
• –3 dB Filter Corner = Sampling Freq / 64 = 8 kHz
• RC filter = 1 / [ 2πx(2xR
series)xC diff ] ~ 8 kHz

CS5374
CS5374
19
4.2 Modulator Inputs — INR, INF
The modulator analog inputs are separated into dif-
ferential rough and fine signals (INR±, INF±) to
maximize sampling accuracy. The positive half of
the differential input signal is connected to INR+
and INF+, while the negative half is attached to
INF– and INR–. The INR± pins are switched-ca-
pacitor ‘rough charge’ inputs that pre-charge the
internal analog sampling capacitor before it is con-
nected to the INF± fine input pins.
4.2.1 Modulator Input Impedance
The modulator inputs have a dynamic switched-ca-
pacitor architecture and so have a rough charge in-
put impedance that is inversely proportional to the
input master clock frequency and the input capaci-
tor size, [1 / (f ·C)].
Internal to the modulator, the rough inputs (INR±)
pre-charge the sampling capacitor used by the fine
inputs (INF±), therefore the input current to the
fine inputs is typically very low and the effective
input impedance is an order of magnitude above
the impedance of the rough inputs.
4.2.2 Modulator Idle Tones — OFST
The modulators are delta-sigma-type and so can
produce “idle tones” in the measurement band-
width when the differential input signal is a steady-
state DC signal near mid-scale. Idle tones result
from low-frequency patterns in the output data
stream and appear in the measurement spectrum as
small tones about -135 dB down from full scale.
By default the OFST bit in the ADCCFG register is
low and idle tones are eliminated within the modu-
lator by adding –60 mV (channel 1) and –35 mV
(channel 2) of internal differential offset during
conversion to push idle tones out of the measure-
ment bandwidth. Care should be taken to ensure
external offset voltages do not negate the internally
added differential offset, or idle tones will reap-
pear.
4.3 Modulator Output — MDATA
The CS5374 modulators are designed to operate
with the CS5376A digital filter. The digital filter
generates the modulator clock and synchronization
signals (MCLK and MSYNC) while receiving
back the modulator one-bit ΔΣ conversion data and
over-range flag (MDATA and MFLAG).
4.3.1 Modulator One’s Density
During normal operation the CS5374 modulators
output a ΔΣ serial bit stream to the MDATA pin,
with a one’s density proportional to the differential
amplitude of the analog input signal. The output bit
rate from the MDATA output is a divide-by-four of
the input MCLK, and so is nominally 512 kHz.
The MDATA output has a 50% one’s density for a
mid-scale analog input, approximately 86% one’s
density for a positive full-scale analog input, and
approximately 14% one’s density for a negative
full-scale analog input. One’s density of the MDA-
TA output is defined as the ratio of ‘1’ bits to total
bits in the serial bit stream output; i.e. an 86% one’s
density has, on average, a ‘1’ value in 86 of every
100 output data bits.
4.3.2 Decimated 24-bit Output
When the CS5374 modulators operate with the
CS5376A digital filter, the final decimated, 24-bit,
full-scale output code range depends if digital off-
set correction is enabled. With digital offset correc-
tion enabled within the digital filter, amplifier
• MCLK = 2.048 MHz
• INR± Internal Input Capacitor = 20 pF
• Impedance = [1 / (2.048 MHz * 20 pF)] = 24 kΩ

CS5374
CS5374
20
offset and the modulator internal offset are re-
moved from the final conversion result.
4.4 Modulator Stability — MFLAG
The CS5374 ΔΣ modulators have a fourth-order ar-
chitecture which is conditionally stable and may go
into an oscillatory condition if the analog inputs are
over-ranged more than 5% past either positive or
negative full scale.
If an unstable condition is detected, the modulator
collapses to a first-order system to regain stability
and transitions the MFLAG output low-to-high to
signal an error condition to the CS5376A digital
filter. The MFLAG output connects to a dedicated
input on the digital filter, causing an error flag to be
set in the status byte of the next output data word.
The analog input signal must be reduced to within
the full-scale range for at least 32 MCLK cycles for
the modulator to recover from an oscillatory condi-
tion. If the analog input remains over-ranged for an
extended period, the modulator will cycle between
fourth-order and first- order operation and the
MFLAG output will be seen to pulse.
4.5 Modulator Clock Input — MCLK
The CS5376A digital filter generates the master
clock for the CS5374, typically 2.048 MHz, from a
synchronous clock input from the external system.
If MCLK is disabled during operation, the CS5374
will enter a power down state after approximately
40 µS. By default, MCLK is disabled at reset and
is enabled by writing the digital filter CONFIG reg-
ister.
MCLK must have low jitter to guarantee full ana-
log performance, requiring a crystal- or VCXO-
based system clock input to the digital filter. Clock
jitter on the digital filter CLK input directly trans-
lates to jitter on MCLK.
4.6 Modulator Synchronization —
MSYNC
The CS5374 modulators are designed to operate
synchronously with other modulators in a distribut-
ed measurement network, so a rising edge on the
MSYNC input resets the internal conversion state
machine to synchronize analog sample timing.
MSYNC is automatically generated by the
CS5376A digital filter after receiving a synchroni-
zation signal from the external system, and is chip-
to-chip accurate within ± 1 MCLK period. The in-
put SYNC signal to the CS5376A digital filter sets
a common reference time t0for measurement
events, thereby synchronizing analog sampling
across a measurement network. By default,
MSYNC generation is disabled at reset and is en-
abled by writing the digital filter CONFIG register.
The CS5374 MSYNC input is rising-edge trig-
gered and resets the internal MCLK counter/divid-
er to guarantee synchronous operation with other
system devices. While the MSYNC signal syn-
chronizes the internal operation of the modulators,
by default, it does not synchronize the phase of the
sine wave from the CS4373A test DAC unless en-
abled in the digital filter TBSCFG register.
Table 1. 24-bit Output Coding
Modulator
Differential
Analog Input
Signal
CS5376A Digital Filter
24-Bit Output Code
Offset
Corrected
CH1
–60 mV
Offset
CH2
–35 mV
Offset
> + (VREF+5%) Error Flag Possible
+ VREF 5D18CA 5ADCCE 5BCB22
0 V 000000 FDC404 FEB258
– VREF A2E736 A0AB3A A1998E
> – (VREF+5%) Error Flag Possible
for the CS5374 Modulator and
CS5376A Digital Filter Combination