CMOSTEK NextGenRF CMT2189B Instruction Manual

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Summary
CMT2189B is a low power, high performance, Flash-based, OOK RF transmitter chip.It covers the 240MHz -
960MHz wireless communication band. This chip is embedded with RISC Flash type MCU. It belongs to the
CMOSTEK NextGenRFTM series product.The product series includes the short range wireless communication
chips, such as transmitter, receiver, transceiver, SoC and so on.
The part numbers covered by this document are as shown below.
Table1. Part Numbers Covered by This Document
Part No.
Frequency
Modem
Tx Power
Tx Current
Configuration
Package
CMT2189B
240 - 960MHz
OOK
+13dBm
17.5mA
Embedded
MCU
SOP14
Note: The test condition for the Tx power and Tx current is at 433.92MHz. CW mode is always in the Tx
carrier mode. The Tx current is about 8.5mA according to the Tx mode of Duty 50%.
AN201
CMT2189B User Guideline
Copyright © By CMOSTEK

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Table of Contents
1Chip Architecture Introduction............................................................................................................... 6
1.1 Overall Operation Principle......................................................................................................... 6
1.2 IO Pin Description....................................................................................................................... 7
2RF Configuration and Control Mechanism............................................................................................ 9
2.1 Work Mode.................................................................................................................................. 9
2.2 Simple Work Mode...................................................................................................................... 9
2.3 Advanced Configuration Mode ................................................................................................. 10
2.4 SPI Interface Timing...................................................................................................................11
2.5 RF Configuration Parameter..................................................................................................... 12
2.6 Configuration Register.............................................................................................................. 15
2.7 Packet Bank Register ............................................................................................................... 16
2.7.1 Tx Rate.............................................................................................................................. 17
2.7.2 Hardware Packet Format .................................................................................................. 17
2.7.3 Preamble........................................................................................................................... 18
2.7.4 Head/Sync......................................................................................................................... 19
2.7.5 Addr/ID .............................................................................................................................. 20
2.7.6 Key Value .......................................................................................................................... 22
2.7.7 LBD Status Configuration.................................................................................................. 23
2.7.8 Stop Bit Configuration ....................................................................................................... 25
2.7.9 Pause/Interval Configuration............................................................................................. 26
2.7.10 Tcycle Configuration.......................................................................................................... 26
2.8 Status and Function Register ................................................................................................... 28
2.8.1 Soft Reset.......................................................................................................................... 28
2.8.2 Working Status and Status Switching ............................................................................... 29
2.8.3 Work Status Query............................................................................................................ 29
2.9 Hardware Packet TxMode ........................................................................................................ 30
2.9.1 Power-up Initialization....................................................................................................... 30
2.9.2 Tx Process ........................................................................................................................ 30
2.10 Direct Tx Mode(Advanced Configuration Mode)....................................................................... 31
2.10.1 Power-up Initialization....................................................................................................... 31
2.10.2 Tx Process ........................................................................................................................ 31
2.10.3 Related Register................................................................................................................ 32
3Program Memory ................................................................................................................................... 33
4Special Function Register(SFR) ........................................................................................................... 34

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4.1 Address Mapping...................................................................................................................... 34
4.1.1 Bank0 SFR........................................................................................................................ 34
4.1.2 BANK1 SFR ...................................................................................................................... 35
4.1.3 TMR0（Addr:0x01）......................................................................................................... 36
4.1.4 STATUS（Addr:0x03）..................................................................................................... 36
4.1.5 PORTA（Addr:0x05）....................................................................................................... 37
4.1.6 PORTC（Addr:0x07）...................................................................................................... 38
4.1.7 INTCON（Addr:0x0B）..................................................................................................... 38
4.1.8 PIR1（Addr:0x0C）.......................................................................................................... 39
4.1.9 TMR2（Addr:0x11）......................................................................................................... 40
4.1.10 T2CON（Addr:0x12）....................................................................................................... 40
4.1.11 WDTCON（Addr:0x18）.................................................................................................. 41
4.1.12 CMCON0（Addr:0x19）................................................................................................... 42
4.1.13 PR0（Addr:0x1A）........................................................................................................... 43
4.1.14 MSCKCON（Addr:0x1B）................................................................................................ 43
4.1.15 SOSCPR（Addr:0x1C/0x1D）......................................................................................... 44
4.1.16 OPTION（Addr:0x81）..................................................................................................... 44
4.1.17 TRISA（Addr:0x85）........................................................................................................ 45
4.1.18 TRISC（Addr:0x87）........................................................................................................ 46
4.1.19 PIE1（Addr:0x8C）.......................................................................................................... 46
4.1.20 PCON（Addr:0x8E）........................................................................................................ 47
4.1.21 OSCCON（Addr:0x8F）................................................................................................... 47
4.1.22 PR2（Addr:0x92）............................................................................................................ 48
4.1.23 WPUA（Addr:0x95）........................................................................................................ 49
4.1.24 IOCA（Addr:0x96）.......................................................................................................... 49
4.1.25 VRCON（Addr:0x99）...................................................................................................... 49
4.1.26 EEDAT（Addr:0x9A）....................................................................................................... 50
4.1.27 EEADR（Addr:0x9B）...................................................................................................... 50
4.1.28 EECON1（Addr:0x9C）................................................................................................... 50
4.1.29 EECON2（Addr:0x9D）................................................................................................... 51
4.1.30 Configuration Register UCFGx ......................................................................................... 51
4.1.31 PCL and PCLATH.............................................................................................................. 53
4.1.32 INDF and FSR Register .................................................................................................... 54
5System Clock Source ............................................................................................................................ 55
5.1 Clock Source Mode................................................................................................................... 55
5.2 External Clock Mode................................................................................................................. 56

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5.2.1 EC Mode ........................................................................................................................... 56
5.2.2 LP and XT Modes.............................................................................................................. 56
5.3 Internal Clock Mode.................................................................................................................. 56
5.3.1 Frequency Selection Bit（IRCF）..................................................................................... 57
5.3.2 Clock Switch Timing of HFINTOSC and LFINTOSC......................................................... 57
5.4 Clock Switching......................................................................................................................... 58
5.4.1 System Clock Select Bit (SCS) ......................................................................................... 58
5.4.2 Oscillator Start-up Timeout Status(OSTS) Bit................................................................... 59
5.5 Two-Speed Clock Start-up Mode.............................................................................................. 59
5.5.1 Two-Speed Start-up Mode Configuration.......................................................................... 59
5.5.2 Two-Speed Start-up Sequence......................................................................................... 60
5.6 Fail-Safe Clock Monitor............................................................................................................. 60
5.6.1 Fail-Safe Detection............................................................................................................ 60
5.6.2 Fail-Safe Operation........................................................................................................... 60
5.6.3 Fail-Safe Condition Being Cleared.................................................................................... 61
5.6.4 Reset or Wake-up from Sleep........................................................................................... 61
6Reset Timing........................................................................................................................................... 62
6.1 Power-on Reset (POR)............................................................................................................. 63
6.2 External Reset (MCLR)............................................................................................................. 63
6.3 Power-up Timer (PWRT)........................................................................................................... 64
6.4 Brown-out Reset (BOR（LVR）).............................................................................................. 64
6.5 Error Instruction Reset.............................................................................................................. 64
6.6 Timeout Action .......................................................................................................................... 64
7BOOT....................................................................................................................................................... 67
8Watchdog Timer..................................................................................................................................... 68
9Timer0 ..................................................................................................................................................... 69
9.1 Timer0 Introduction................................................................................................................... 69
9.2 Timer0 Timer Mode................................................................................................................... 69
9.3 Timer0 Counter Mode............................................................................................................... 69
9.3.1 Software Configuring Prescaler Circuit............................................................................. 70
9.3.2 Timer0 Interrupt................................................................................................................. 70
9.3.3 Drive Timer0 with the External Clock ................................................................................ 71
10 Timer2 ..................................................................................................................................................... 72
11 Comparator............................................................................................................................................. 74
12 Data EEPROM......................................................................................................................................... 75
13 Clock Measurement............................................................................................................................... 76

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14 Interrupt Mode........................................................................................................................................ 77
14.1 INT Interrupt.............................................................................................................................. 77
14.2 PORTA Level Change Interrupt ................................................................................................ 78
14.3 Interrupt Response ................................................................................................................... 78
14.4 Context Saving During Interrupts.............................................................................................. 80
15 MCU Sleep Saving Mode....................................................................................................................... 81
15.1 Wake-up Mode.......................................................................................................................... 81
15.2 Watchdog Wake-up................................................................................................................... 81
16 I/O Port .................................................................................................................................................... 82
16.1 PORTA Port and TRISA Register.............................................................................................. 82
16.2 Other Functions of the Port....................................................................................................... 82
16.2.1 Weak Pull-Up .................................................................................................................... 82
16.2.2 Interrupt-On-Change......................................................................................................... 82
16.3 Port Description ........................................................................................................................ 83
16.3.1 PORTA<2:0>..................................................................................................................... 83
16.3.2 PORTA3/PA3..................................................................................................................... 84
16.3.3 PORTA4/PA4..................................................................................................................... 86
16.3.4 PORTA5/PA5..................................................................................................................... 87
16.3.5 PORTA7/PA7..................................................................................................................... 87
16.3.6 PORTC<7:0>..................................................................................................................... 88
17 Instruction Set List ................................................................................................................................ 89
18 Document Modification Record............................................................................................................ 91
19 Contact Information............................................................................................................................... 92

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1 Chip Architecture Introduction
1.1 Overall Operation Principle
CMT2189B is a digital and analog integrated RF transmiter chip. It is applied with the crystal oscillator to
provide the reference frequency and digital clock for PLL, supports the OOK modulation that the data rate is
from 1Kbps to 40Kbps, and supports the status control based on the MCU programming. It is suitable for all
kinds of low power transmission applications.
LDOs
PFD/CP
N-DIV
Interface and Digital Logic
Loop Filter
Modulator Ramp
Control
VCO
XOSC
AVDD
GND
XTAL
RFCTRL
RFO
POR LFOSC
PA
EEPROM
Bandgap VTR
CPU
Program ROM
2K * 14Bit
Data EEPROM
256 * 8Bit
TMR/WDT
IO
CMP
RSTC/OST/
PWRT/BOOT CLKC
SFR
EXTCK
IRCCK
SRAM
128 * 8Bit
CFG
DVDD
PA0 PA1 PA2 PA3 PA4 PC4 PC6PA7
DIN
3-SPI
PC0
PC[3:1]
Figure 1-1. CMT2189B System Architecture
The chip adopts the PLL+PA architecture to achieve the Sub-GHz wireless transmission function. It supports
the packet FIFO mode and Direct mode (The embedded encoder in the Packet FIFO mode can select the
appropriate encoding format). The processed data is sent to the modulator (For the Direct mode, they are not
processed by the encoder, and directly deburred, and then sent to the modulator), the modulator controls PLL
and PA, and the data is modulated by OOK and transmitted out.
The MCU of the chip controls the RF part by the 3-wire SPI interface, and achieves various status switching,
mode selection and low power control.

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1.2 IO Pin Description
DVDD
PC6
PC4/C2OUT
XTAL
RFCTRL
AVDD
GND
PA2/T0CKI/INT/C1OUT
RFO
PA3
PA7/OSC1/CLKI
PA1/C1IN-/ICSPDAT
PA0/C1IN+/ICSPCLK
1
2
3
4
5
6
7
9
14
13
12
11
10
8
PA4
Figure 1-2. CMT2189B Pin Top View
Table 1-2. CMT2189B SOP14 Package Pin Description
Pin No.
Name
Type
I/O
Function Description
1
DVDD
Digital
I
Chip power supply positive pole
2
PC6
Digital
IO
General IO
3
PC4/C2OUT
Digital
IO
PC4
General IO
C2OUT
Comparator2 output
4
XTAL
Analog
I
RF part crystal oscillator input
5
RFCTRL
Digital
I
RF part SPI interface enable control bit, active low,
internal pull-up
6
AVDD
Analog
I
RF part power supply positive pole
7
GND
Digital
--
Chip power supply ground
8
RF0
Analog
O
RF part PA output
9
PA4
Digital
IO
General IO, support IOC, can be configured as pull-up
10
PA3
Digital
IO
General IO, support IOC, can be configured as pull-up
11
PA2/T0CKI/INT/C1OUT
Digital
IO
PA2
General IO, support IOC, can be
configured as pull-up
T0CKI
Timer0 clock source input (Max=4MHz)
INT
External interrupt input
C1OUT
Comparator1 output
12
PA0/C1IN+/ICSPCLK
Digital
IO
PA0
General IO, support IOC, can be
configured as pull-up
C1IN+
Comparator1 input+
ICSPCLK
Debug/ burning mode serial port Clock
signal
13
PA1/C1IN-/ICSPDAT
Digital
IO
PA1
General IO, support IOC, can be
configured as pull-up
C1IN-
Comparator1 input -

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Pin No.
Name
Type
I/O
Function Description
ICSPDAT
Debug/ burning mode serial port Data
signal
14
PA7/OSC1/CLKI
Digital
IO
PA7
General IO, support IOC, can be
configured as pull-up
OSC1
MCU Crystal pin
CLKI
External clock input pin
Internal
pin
PC0/C2IN+/RFDIN
Digital
IO
PC0
General IO
C2IN+
Comparator2 input +
RFDIN
Data input pin in the RF direct mode
Internal
pin
PC1/C2IN-/SDIO
Digital
IO
PC1
General IO，it is connected to the RF part
inside the chip.
C2IN-
Comparator2 output -
SDIO
RF Part 3-wire SPI serial bus data SDIO,
SDIO itself has no pull-up or pull-down
resistance, it is a bi-directional port.
Internal
pin
PC2/SCLK
Digital
IO
PC2
General IO，it is connected to the RF part
inside the chip.
SCLK
RF Part 3-wire SPI serial bus clock SCLK
Internal
pin
PC3/CSB
Digital
IO
PC3
General IO，it is connected to the RF part
inside the chip.
CSB
RF 3-wire SPI serial bus chip selection bar
CSB, with internal pull-up resistor.
Note:
1. The two comparators are integrated within the MCU, but the internal comparator can not be used
because they have the package terminals and some of them are reused to the RF part at the same
time.However, in the initialization process, MCU needs to turn off the comparator function and set its
corresponding pin as the digital IO, to avoid affecting the work of other functions.
2. The clock source system of MCU supports the internal oscillation and the external oscillation. The
external oscillation supports the dual-end crystal and the single-end clock source input. However, due to
the limitation of the package pin, the PA6 has no the package terminal, so the external oscillation mode of
the dual-end crystal is not supported, which only supports the external oscillation mode of the single-end
clock source.
3. PC<3:0> is the internal control pin of the chip and not the package terminal, but it is used as a bus to
control the RF.

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2 RF Configuration and Control Mechanism
2.1 Work Mode
There are two working modes for the OOK Tx function of CMT2189B.
Simple work mode: the default entry mode on Power-up, that is, the non configuration mode, only
supports the Direct Tx mode in this mode.
Advanced configuration mode: the mode of configuring registers and controlling the working state
through the SPI bus, which supports the FIFO and the Direct mode.
Note: the direct Tx input source in the two work modes is different, and the following is described in detail.
2.2 Simple Work Mode
In the simple work mode, the peripheral only needs to match a crystal oscillator. After power-up, the chip
controls the transmitted data through the internal PC1 (SDIO), and then to realize the transmission of the
corresponding frequency. In this mode, the frequency doubling coefficient is fixed to 16.5, which is the
following formula:
 
，314 MHz ≤FRF≤480 MHz
Among them, FXTAL is the crystal frequency and FRF is the target frequency, and the frequency range is
314MHz ~ 480MHz.
TOFF
PC1/SDIO
STATE
PA _ OUT
SLEEP CALS
PLL
TX
SLEEP
PA _ OUT
Figure 2-1. Tx Timing Diagram in the Simple Work Mode
Note:
1. This mode supports the rate of 1Kbps to 20Kbps.
2. The maximum power output is fixed to +13dBm. When the user needs to reduce the Tx power, he can
only connect the current limiting resistor before the Chock inductor.
3. The internal SPI bus does not need to send any control commands and only needs to hold PC<3:0> in a
high resistance input status (except PC1).
4. The RFCTRL pin can be suspended in this mode.
5. In this mode, the transmitted data pin is PC1(SDIO), which is set to 0 in the low power consumption

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status(that is normal). When the transmission is needed, the rising edge is triggered to enter the
transmission status. After transmitting, PC1 is set to 0 and lasts more than 20ms (TOFF time), and RF
automatically exit from the Tx mode to enter the low power consumption status.
6. In this mode, the low power internal pin processing, PC1/SDIO is set to 0 output, PC2/SCLK, PC3/CSB,
and PC0/RFDIN are set to high resistance input.
2.3 Advanced Configuration Mode
When users need to achieve more functions and higher performance, such as: the target working frequency is
868MHz, the chip automatically sends packets in the transmission process, and so on, and they need to use
the advanced configuration mode. In this mode:
Select more frequency multiplication ratio coefficients to achieve the frequency range coverage of
240MHz ~ 960MHz.
Release the MCU to do more work (In the Direct mode, this process takes up the MCU resource) by
filling the FIFO and automatically sending the message (repeatedly, multiply and periodically).
Support the more accurate Tx rate, and the accuracy is determined by the crystal. It is quite accurate
(in the Direct mode, the speed is controlled by the MCU software, and the accuracy depends on the
software and internal RC).
Support the voltage detection function inside the RF, and realize the simple power supply voltage
detection and analysis judgment processing.
Adjust the Tx power dynamically according to the power supply voltage, so as to save the power and
prolong the battery life.
In this mode, the internal MCU of the chip can control the mode of RF part operation register through 3-wire
SPI (PC3/CSB, PC2/SCLK, PC1/SDIO), and to achieve the two Tx modes.
1. Hardware packet Tx mode that fill FIFO through SPI (see Section 2.9 in detail)
The contents that need to be transmitted are filled into the specified registers, which are automatically
transmitted according to the speed, coding mode, number of packets and packet interval, etc. (The data
package format and other relevant information are detailed in Section 2.7 of this chapter).
2. Direct Tx mode that PC0/RFDIN is as the data pin(see Section 2.10 in detail)
That is, the 1-Pin Tx mode, the data stream is generated by the MCU, and the output is carried out by the
specified pin to achieve the most basic work mode of "data entry and antenna out".
Note:
1. The two Tx modes mentioned above are all under the advanced configuration mode, that is, configuring
and operating the chip through SPI.
2. In the advanced configuration mode, RFCTRL needs to be controlled, that is to say, the RFCTRL needs
to be controlled by other pins, so the RFCTRL can not be suspended.
3. The Direct mode which is supported by the advanced configuration mode is similar to the Direct mode of
the simple work mode, by which is controlled by one data pin, but the data input source is different. In the

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simple work mode, the Tx input pin is PC1/SDIO, while in the advanced configuration mode, it is changed
to PC0/RFDIN because PC1/SDIO is the serial data line of SPI. Of course, the Direct mode in the
advanced configuration mode can support more frequency selection and power selection than in the
simple mode.
2.4 SPI Interface Timing
The RF function inside the chip is controlled by the 3-wire SPI, and the corresponding relationship to the IO of
the MCU part is as follows:
Table 2-1. The Relationship between SPI Bus and Control Port
3-wire SPI
MCU Control Port
Function
CSB
PC3
Bus chip selection bar, enabled low, built-in pull-up.
SCLK
PC2
Bus clock line, rising edge trigger
SDIO
PC1
Bus bi-directional data
Note: SDIO, a bi-directional port, used for input and output data. Both the address and the data section are
transmitted from the MSB.
When the RF part is accessed, RFCTRL is pulled down [*], the SPI serial port function is enabled, then the
chip selection bar (PC3/CSB) is pulled down, a R/W bit is sent, and followed by a 7-bit register address. After
the chip selection bar (PC3/CSB) is pulled down, it is necessary to wait for at least half a PC2 (SCLK) cycle to
start sending R/W bit.After sending the falling edge of the last PC2 (SCLK), the chip must wait for at least half
a SCLK cycle, and then pull the PC3 (CSB) high.
In the SPI read operation below, pay special attention to PC1/SDIO, because SDIO is a bi-directional
port.SDIO will switch from the input state to output state on the eighth clock falling edge (middle dotted line in
the figure below), and SDIO needs to switch from the output state to input state before the eighth clock falling
edge.
X 01234567 X
register address register read data
01234567
r/w =1
>0.5 SCLK cycle >0.5 SCLK cycle
PC3/CSB
PC2/SCLK
1PC /SDIO
RFCTRL
Figure 2-2. SPI Read Register Timing

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X X01234567 01234567
register address register write datar/w =0
>0.5 SCLK cycle >0.5 SCLK cycle
RFCTRL
PC3/CSB
PC2/SCLK
PC1/SDIO
Figure 2-3. SPI Write Register Timing
Note: RFCTRL is the input port and needs the external control. It is recommended that users control it
by any function port in CMT2189B, and pull it down to enable the SPI interface function. In the whole
process, RFCTRL can hold low, but in the low power sleep mode, need to set the RFCTRL pin of MCU
to a high impedance input, because RFCTRL internal pull-up can pull the level high. Do not set the
MCU pin to low output, because the pull-down can generate the power consumption.
2.5 RF Configuration Parameter
CMT2189B operates in the advanced configuration mode, which can achieve more wide working frequency,
packet format, and other functions. These functions need corresponding configuration parameters, which can
be exported by RFPDK software. The specific approach is to open the RFPDK software and select the
CMT2157B model (the same specifications and performance as the CMT2189B built-in RF), as shown in the
following figure.
Figure 2-4. RFPDK CMT2157B Interface

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On the interface, there are mainly two zones: RF parameter settings zone and data packet settings zone.
Users configuration are based on the requirements according to the relevant registers below, and then click
Export to generate an exp file, which is as follows:
;---------------------------------------
; CMT2157B Configuration File
; Generated by CMOSTEK RFPDK 1.46
; 2017.11.14 13:47
;---------------------------------------
; (The annotation with ";" in the middle is omitted.)
;---------------------------------------
; The following are the EEPROM contents
;---------------------------------------
0x7E4F
0x2134
0x017F
0x8015
0x0018
0x7F00
0x0000
0x8000
0x0000
0x0000
0xA073
0xE080
0x2010
0x8040
0x5030
0x6090
0xC0A0
0x0000
0x0100
0x027C
0x957B
0x70F0
0x0083
0x0000
;---------------------------------------
;The following is the CRC result for
; the above EEPROM contents
;---------------------------------------
0xEDFA
;---------------------------------------

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; The following are for CMOSTEK
; use, customers can ignore them
;---------------------------------------
0x0000
0x0018
Among them, the red font part is the specific configuration content, they are all 16-bit word, a total of 24 words,
so users need to convert the 16-bit word to the 8-bit register content. The method of conversion is that the
higher 8-bit of each 16-bit word is an odd number address, and the lower 8-bit is an even address. The 24
words conversion gets 48 register configuration values, and the address range is 0x00 to 0x2E (the last 8-bit
is invalid). According to the above file, the contents of the register are as follows:
Table 2-2. Conversion Table from 16-bit EEPROM Word to 8-bit Register Content
16-bit
Word
Register
Address
8-bit Register
Configuration
Value
0x7E4F
0x00
0x4F
0x01
0x7E
0x2134
0x02
0x34
0x03
0x21
0x017F
0x04
0x7F
0x05
0x01
0x8015
0x06
0x15
0x07
0x80
0x0018
0x08
0x18
0x09
0x00
0x7F00
0x0A
0x00
0x0B
0x7F
0x0000
0x0C
0x00
0x0D
0x00
0x8000
0x0E
0x00
0x0F
0x80
0x0000
0x10
0x00
0x11
0x00
0x0000
0x12
0x00
0x13
0x00
0xA073
0x14
0x73
0x15
0xA0
0xE080
0x16
0x80
0x17
0xE0
0x2010
0x18
0x10

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16-bit
Word
Register
Address
8-bit Register
Configuration
Value
0x19
0x20
0x8040
0x1A
0x40
0x1B
0x80
0x5030
0x1C
0x30
0x1D
0x50
0x6090
0x1E
0x90
0x1F
0x60
0xC0A0
0x20
0xA0
0x21
0xC0
0x0000
0x22
0x00
0x23
0x00
0x0100
0x24
0x00
0x25
0x01
0x027C
0x26
0x7C
0x27
0x02
0x957B
0x28
0x7B
0x29
0x95
0x70F0
0x2A
0xF0
0x2B
0x70
0x0083
0x2C
0x83
0x2D
0x00
0x0000
0x2E
0x00
The user only needs to write the above contents to the 0x01～0x2E register address through SPI write timing.
2.6 Configuration Register
The above exported configuration parameter address from 0x01 to 0x2E can be divided into three banks
according to the functions, which are as follows:
Table 2-3. Configuration Register Bank Partition Table
Bank
Address
Involved Content
Tx Bank
0x00 –0x03
Tx frequency,Tx power
Packet Bank
0x04 –0x27
Tx rate, packet format (only for hardware packet Tx
mode）
System Bank
0x28 –0x2E
System working parameters

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Tx Bank
The register address range associated with the Tx bank parameter is 0x00~0x03. These parameters are
mainly about Tx central frequency and Tx power. Therefore, when users need to transmit multiple frequencies
in the application, such as frequency hopping, or adjusting the Tx power according to the voltage value, they
can export different parameter tables by setting in the RFPDK, and only need to take 0x00~0x03 segment. So
there is no detailed description about each register meaning in this part.
Packet Bank
The register address range associated with the packet bank parameters is 0x04~0x27. These parameters are
mainly setting items of the hardware packet format, and also applicable to the hardware packet Tx mode. For
the meaning of the specific registers, please read Section 2.7 in this chapter.
System Bank
The register address range associated with the system bank parameters is 0x28~0x2E. These parameters
are the specific parametersof RF, and are not related to user applications. Users need not pay attention to
them, only need to configure them according to the parameters exported from RFPDK, so they are also not
discussed in detail here.
2.7 Packet Bank Register
The overview of the packet bank register is shown below.
Table 2-4. Packet Bank Register Overview Table
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x04
CUS_DIG1
SYMBOL_TIME<7:0>
0x05
CUS_DIG2
SYMBOL_TIME<15:8>
0x06
CUS_DIG3
LBD_TH<3:0>
LBD_OUT_EN
LBD_ON
0x07
CUS_DIG4
DEGLITCH_EN
TX_OVERTIMES<2:0>
0x08
CUS_PKT1
TCYCLE_EN
INTERVAL_EN
STOP_EN
KEY_EN
SYNC_EN
PREAMBLE_LOCATION
PREAMBLE_SEL
PREAMBLE_EN
0x09
CUS_PKT2
TXCYCLE<7:0>
0x0A
CUS_PKT3
PREAMBLE_LENGTH<7:0>
0x0B
CUS_PKT4
KEY_LENGTH<2:0>
SYNC_LENGTH<4:0>
0x0C
CUS_PKT5
SYNC_HEADER<7:0>
0x0D
CUS_PKT6
SYNC_HEADER<15:8>
0x0E
CUS_PKT7
SYNC_HEADER<23:16>
0x0F
CUS_PKT8
SYNC_HEADER<31:24>
0x10
CUS_PKT9
ADDR_ID<7:0>
0x11
CUS_PKT10
ADDR_ID<15:8>
0x12
CUS_PKT11
ADDR_ID<23:16>
0x13
CUS_PKT12
ADDR_ID<31:24>
0x14
CUS_PKT13
BIT_FORMAT<2:0>
ADDR_LENGTH<4:0>
0x15
CUS_PKT14
STOP_LENGTH<3:0>

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Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x16
CUS_PKT15
BIT_LOGIC_L<7:0>
0x17
CUS_PKT16
BIT_LOGIC_H<7:0>
0x18
CUS_PKT17
KEY<7:0>
0x19
~
0x21
CUS_PKT18
~
CUS_PKT26
0x22
CUS_PKT27
STOP_BIT_L<7:0>
0x23
CUS_PKT28
STOP_BIT_H<15:8>
0x24
CUS_PKT29
INTERVAL_LENGTH<7:0>
0x25
CUS_PKT30
PKT_NUM<7:0>
0x26
CUS_RESV1
0x27
CUS_RESV2
INTERVAL_STBY_DIS
STBY_PLLOFF_DIS
Note:
1. The gray area indicates that users do not need to understand, and is not without content. Users only need
to configure them according to the parameters exported from RFPDK, and users can set the individual bit
to 1 or 0 by the "read-modify-write" process.
2. The blue area indicates that users need to know, and the following will explain them one by one.
3. The CMT2189B built-in packet structure pattern is the same as CMT2157B.The user can select the
packet structure in the CMT2157B configuration interface through RFPDK, and generate the “exp”
parameter and configure them in the order of parameters.In the software implementation process, the
user only needs to fill the specific data content.
2.7.1 Tx Rate
The Tx rate is determined by SYMBOL_TIME<15:0> and can be generated by RFPDK.
Register Name
Bits
R/W
Bit Name
Function description
CUS_DIG1
(0x04)
7:0
RW
SYMBOL_TIME<7:0>
Packet format Tx data rate
CUS_DIG2
(0x05)
7:0
RW
SYMBOL_TIME<15:8>
2.7.2 Hardware Packet Format
The interior of the CMT2189B supports the hardware packet structure, and its data frame structure is as
follows:
Preamble Head/
Sync ID/ADDR Key Value LBD
Status
Stop
Bit
1 32 4 5 6
Pause/Interval
7
Figure 2-5. Packet Structure

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In the packet structure figure above, there are 7 main parts:
1. Preamble：Preamble code, optional, the value can be selected as 0x55 or 0xAA[1], range from
0~256 Bytes, arbitrary selection;
2. Head/Sync：Synchronous word, optional, range from 0~32 bits[2], arbitrary selection;
3. ID/ADDR：Sequence number, must be selected, range from 1~32 logic bits[3], arbitrary selection;
4. Key Value：Key value, optional, range from 0~8 logic bits[3], arbitrary selection;
5. LBD Status：Low battery detection status bit, optional, onlyone logic bit [3];
6. Stop Bit：Stop bit, optional, range from 0~16 bits[2], arbitrary selection;
7. Pause/Interval：Packet interval, fixed to send"0", range from 0~256 bits[2];
Note:
[1]. The preamble code does not need to be encoded, that is, using the NRZ format, such as the selection of
0x55, the data flow is 0b01010101 according to the setting rate (0 represents low level, 1 represents high
level).
[2]. Head/Sync, Stop Bit and Pause/Interval all do not need to be encoded and output according to the setting
rate, just like the preamble code.
[3]. The logic bit represents the encoded bit, which is described in detail below; the number 3~5 of the
message structure above all support the internal encoder for coding.
For example, the coding rules choose one symbol as one logical bit at least, that is, 0b0 is logic 0, and 0b1 is
logic 1 (NRZ encoding), sets as following:
Preamble：Set to open, the value is 0xAA, the length is 5 Bytes;
Head/Sync：Set to open, the value is 0x2DD4, the length is 2 Bytes;
ID/ADDR：The value is 0x12345678, the length is 4 Bytes;
Key Value：The value is 0x9A;
LBD Status：Set to close
Stop Bit：Set to open, the value is 0xBCDE, the length is 16 bits (2 Bytes);
Pause/Interval：Pause/Interval: set to open, the length is 32 bits (4 Bytes);
Then the data flow is as follows:
0xAA AA AA AA AA 2D D4 12 34 56 78 9A BC DE 00 00 00 00 AA AA AA AA AA 2D D4 12 34 56 78 9A BC
DE 00…
2.7.3 Preamble
Table 2-5. Preamble Configuration Register
Register
Name
Bits
R/W
Bit Name
Function Description
CUS_PKT1
(0x08)
2
RW
PREAMBLE_LOCATION
When enabling Tcycle, it represents the
Preamble location in the packet structure:
0：In one cycle, each packet contains 1

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Register
Name
Bits
R/W
Bit Name
Function Description
Preamble, i.e. there are N packets in the 1 cycle,
which contain N Preambles.
1：In one cycle, only contains 1 Preamble, and it
is only in the first packet.
Note: The concept of Tcycle is described in detail
later.
1
RW
PREAMBLE_SEL
Preamble Select bit:
0：0x55
1：0xAA
0
RW
PREAMBLE_EN
Preamble Enable bit:
0：Disable
1：Enable
CUS_PKT3
(0x0A)
7:0
RW
PREAMBLE_LENGTH<7:0>
The length of Preamble can be configured to be
0~255, and 0 represents that sending 1 Byte of
Preamble, and so on, and 255 represents that
sending 256 Bytes of Preamble.
For the user, if the PREAMBLE_EN is 0, the Preamble is not sent, and if the configuration is 1, the Preamble
of 1-256 Bytes is sent.
2.7.4 Head/Sync
Table 2-6. Head/Sync Configuration Register
Register
Name
Bits
R/W
Bit Name
Function Description
CUS_PKT1
(0x08)
3
RW
SYNC_EN
Sync Enable bit：
0：Disable
1：Enable
CUS_PKT4
(0x0B)
4:0
RW
SYNC_LENGTH<4:0>
The Sync length can be configured to 0~31, 0
represents that sending 1 Symbol of Sync, and so
on, 31 represents that sending 32 Symbols of
Sync, and the Symbol is random in length.
CUS_PKT5
(0x0C)
7:0
RW
SYNC_HEADER<7:0]>
The value of the Sync can be filled in different
registersaccording to the different
SYNC_LENGTH settings, please look at the next
table.
CUS_PKT6
(0x0D)
7:0
RW
SYNC_HEADER<15:8>
CUS_PKT7
(0x0E)
7:0
RW
SYNC_HEADER<23:16>
CUS_PKT8
(0x0F)
7:0
RW
SYNC_HEADER<31:24>

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Table 2-7. The Relationship Between Head/Sync Length Selection and Register
SYNC/HEADER
SYNC_LENGTH
<31:24>
<23:16>
<15:8>
<7:0>
0~7
√
8~15
√
√
16~23
√
√
√
24~31
√
√
√
√
The position of the tick in the table indicates the register to be filled. For example, if SYNC_LENGTH is set to
15, that is, the length is 16 Symbols, Sync value is 0x5678, then the user will fill the value into
SYNC_HEADER<31:24> and SYNC_HEADER<23:16> registers, MSB is corresponds to the thirty-first bit,
LSB is corresponding to the sixteenth bit, that is, 0x56 is filled into SYNC_HEADER<31:24> and 0x78 is filled
into SYNC_ HEADER<23:16>. For the user, if the Sync Enable bit is 0, the Sync is not sent, and if the Sync
Enable bit is 1, the Sync of 1-32 Symbols is sent.
2.7.5 Addr/ID
Table 2-8. Addr/ID Configuration Register
Register
Name
Bits
R/W
Bit Name
Function Description
CUS_PKT13
(0x14)
4:0
RW
ADDR_LENGTH<4:0>
The Addr ID length can be configured to 0~31,
and 0 represents that sending the Addr of 1 Logic
bit, and so on, 31 represents that sending the
Addr of 32 Logic bits, and the Logic bit length is
random.
7:5
RW
BIT_FORMAT<2:0>
The number of Symbol that is contained by 1
Logic bit can be configured to 0~7, 0 represents 1
Symbol, and so on, and 7 represents 8 Symbols.
CUS_PKT15
(0x16)
7:0
RW
BIT_LOGIC_L<7:0>
Logic 0 definition
CUS_PKT16
(0x17)
7:0
RW
BIT_LOGIC_H<7:0>
Logic 1definition
CUS_PKT9
(0x10)
7:0
RW
ADDR_ID<7:0>
Addr ID value
CUS_PKT10
(0x11)
7:0
RW
ADDR_ID<15:8>
CUS_PKT11
(0x12)
7:0
RW
ADDR_ID<23:16>
CUS_PKT12
(0x13)
7:0
RW
ADDR_ID<31:24>