Compal PEW76 Technical manual

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
155Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
155Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
155Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Champlain Processor with RS880M/SB820/Madison VGA
PEW76 Schematics Document
LA5911P REV: 1.0
Compal Confidential
2010-06-07
AMD Danube
ZZZ
X76244BOL05
Part Number = X76244BOL05
128M1G@
ZZZ
X76244BOL05
Part Number = X76244BOL05
128M1G@
ZZZ
X76244BOL01
Part Number = X76244BOL01
64M512@
ZZZ
X76244BOL01
Part Number = X76244BOL01
64M512@
ZZZ
X76244BOL06
Part Number = X76244BOL06
128M2G@
ZZZ
X76244BOL06
Part Number = X76244BOL06
128M2G@
ZZZ
X76244BOL03
Part Number = X76244BOL03
64M1G@
ZZZ
X76244BOL03
Part Number = X76244BOL03
64M1G@
ZZZ
PCB
Part Number = DAZ0FQ00100
ZZZ
PCB
Part Number = DAZ0FQ00100

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
255Tuesday, September 14, 2010
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
255Tuesday, September 14, 2010
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
255Tuesday, September 14, 2010
2008/10/06 2009/10/06
Compal Electronics, Inc.
Power On/Off CKT.
Touch Pad
LPC BUS
page 42
Compal Confidential
uFCBGA-528
page 43
Int.KBD
page 39
USB
conn
X 3
A link Express2
DC/DC Interface CKT.
AMD S1G4 Processor
page 38
3.3V 48MHz
Hyper Transport Link
16 x 16
page 38
EC I/O Buffer
Power Circuit
uPGA-638 Package
page 41
page 45
ATI RS880M
BIOS
page 4,5,6,7
page 39
HD Audio
page 10,11,12,13
ATI SB820M
page 27,28,29,30,31
page 39
ENE KB926
Bluetooth
Conn
3.3V 24.576MHz/48Mhz
Model Name : NEW75/85/95
RTC CKT.
page 26
page 43
page 46,47,48,49,50,51
52,53,54
S-ATA
page 32
SATA HDD
Conn.
port 0
CMOS
Camera
USB port 0,1,2
USB
CDROM
Conn.
page 32
Mini
card
(WL)X1
port 1
USB port 5 USB port 12 USB port 8
page 36,37 page 27 page 37 page 36
Dual Channel BANK 0, 1, 2, 3
204pin DDRIII-SO-DIMM X2
1.5V DDRIII 800~1333MHz
Memory BUS(DDR3)
page 8,9
Clock Generator
ICS9LPRS488
page 6 page 23
Thermal Sensor
ADM1032
ATI M97
Madisan/Park
VRAM 1GB
64M16 x 8
PCI-Express x 16
DDR3
page 19, 20
Page 14,15,16,17,18,21,22
uFCBGA-605
uFCBGA-962
HDA Codec
ALC272X
Audio AMP
Phone Jack x2
page 40
LED
page 39
LID SW / MEDIA/B
Gen2
Champlain
Danube
page 34
MINI Card 1
WLAN
page 36
GPP0GPP1
RJ45
page 35
Broadcom
BCM57780
LAN(GbE)
LVDS
page 24
CRT
page 26
HDMI Conn.
page 25
Fan Control
page 44
<Option>
Extend Card/B
1. USB X2
2. Cardreader
JM385
page 36
USB port 9
3G/GPS
WWAN
<Option>
page 36
USB port 6
Card
Reader
Gen1
Gen2

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
355Tuesday, September 14, 2010
2005/10/10 2010/03/12
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
355Tuesday, September 14, 2010
2005/10/10 2010/03/12
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
355Tuesday, September 14, 2010
2005/10/10 2010/03/12
GbE LAN
Broadcom
B57780
WLAN
Mini PCI Socket
A_SODIMM
S1G4
CPU SOCKET
NB
RS880M
SB
SB820M
Internal CLK GEN
CPU_HT_CLKP/N
200MHz
VGA
ATI
Madison/Park
B_SODIMM
MEM_MA_CLK7_P/N
1066MHz
1066MHz
MEM_MA_CLK1_P/N
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
AMD CLK_SBSRC_BCLK/#
100MHz
100MHz
NB_DISP_CLKP/N
100MHz
NB_HT_CLKP/N
AMD AMD
AMD
VGA_CLKP/N
100MHz
100MHz
100MHz
GPP_CLK1P/N
GPP_CLK3P
32.768KHz 25MHz
Compal Electronics, Inc.

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
455Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
455Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
B
455Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
STATE SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5% 0 V 0.216 V 0.250 V 0.289 V
0.436 V
0.712 V 0.503 V 0.819 V 0.538 V 0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5% 3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V 2.200 V 3.300 V 2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
BOARD ID Table BTO Option Table
BTO Item BOM Structure
1101 001Xb
OFF OFF
+0.9V 0.9V switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS 1.8V switched power rail
+2.5VS
+5VS
+3VS
+5VALW
+1.8V
2.5V for CPU_VDDA
+3VALW
1.8V power rail for CPU VDDIO and DDR
3.3V always on power rail
5V always on power rail
3.3V switched power rail
5V switched power rail
+VSB VSB always on power rail ON ON*
ONON
ON
ON
EC SM Bus1 address
Device
SB820
SM Bus 1 address
ON
OFF
OFF
DDR DIMM1
1001 000Xb
DDR DIMM2
1001 010Xb
1.5V power rail for PCIE Card
+CPU_CORE_0
SB820
SM Bus 0 address
Device
Clock Generator
(SILEGO SLG8SP626)
Address
Address Address
Voltage Rails
VIN
B+
+1.1VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
ON
+VGA_CORE OFFOFFON
1.1V switched power rail for NB VDDC & VGA
ON
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)
ON OFF OFF
ADI ADM1032 (CPU)
+1.2V_HT 1.2V switched power rail ON OFF OFF
ON ON*
ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON ON
S1 S3 S5
ON OFF
ON
N/A N/A N/A
N/AN/AN/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
ON
OFF
OFF
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
OFFON
ON
ON
ON
OFF
ON*
OFF
OFF
ON
Device Address
ON
1001 100X b0001 011X b
0.95-1.2V switched power rail
HEX
98H
9AH
GMT G781-1 (GPU)
1001 101X b
16H
HEX
D2
HEX
90
94
Mini card
98H
SB-Temp Sensor
Project ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
BOM Config
DIS ONLY:(Park) 3G@/BT@/DISO@/ VGA@/EXT@/EXTPW@/PARK@
PowerXpress SKU(Park): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/PARK@
UMA only SKU: 3G@/BT@/UMA@/ UMAO@/EXT@/VB@
DIS ONLY(PARK): 3G@/BT@/DISO@/VGA@/INT@/PARK@
PowerXpress SKU(Madison):3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/MAD@
UMA only SKU: 3G@/BT@/UMA@/UMAO@/INT@/VB@
EXT CLKGEN
INT CLKGEN
PowerXpress SKU(Madison): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/MAD@
PowerXpress SKU(Park): 3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/PARK@
No USB Patch
Add USB patch
NEW75/85/95
PEW76/86/96
PEW56
--For SSID define
--For TSI thermal math
Capilano w/ USB patch

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
555Tuesday, September 14, 2010
2009/3/8 2010/03/12
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
555Tuesday, September 14, 2010
2009/3/8 2010/03/12
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
555Tuesday, September 14, 2010
2009/3/8 2010/03/12
PU10
APL5913
EC
ENE KB926
1.5V
0.75V
+1.5VS 500mA
+3.3VS 1A+3.3VS 300mA +3.3VALW 330mA +3.3VS 3mA
+3.3VALW 30mA
SATA
+5V 45mA
+3.3VS 25mA +3.3VALW 201mA
Audio AMP
TPA6017A2
+5V 25mA
+3.3 350mA
B+ 300mA
LCD panel
15.6"
+5V 3A
+3.3V
BATTERY
12.6V PU5 CHARGER
ISL6261AHAZ-T
ICS9LPRS488B
+3.3V 400mA
AC ADAPTOR
19V 90W
LAN
Atheros AR8114
RAM DDRIII SODIMMX2
VDD_MEM 4A
FAN Control
APL5607
+5VS 500mA
Audio Codec
ALC272 RTC
Bettary
VTT_MEM 0.5A
+5V
Dual+1
2.5A
USB X3 Realtek
RTS5159 Mini Card
+1.1V
BATT+
VIN
VDD CORE 36A
VDDNB 4A
VDDIO 3A
VDDR 1.5A
VDDA 250mA
VLDT 1.5A
AMD CPU S1G4
0.7~1.3V
0.8~1.2V
2.5V
1.5V
1.05V
1.1V
VDDIO_AZ_S
VDDAN_11_PCIE 1A
SouthBridge AMD SB820M
VDDPL_33_PCIE 0.030A
VDDAN_33_USB_S 0.2A
VDDAN_11_SATA 0.8A
VDDIO_33_S
VDDIO_33_PCIGP 0.020A
VDDRF_GBE_S
VDDCR_11 1.1V 0.5A
VDDAN_11_USB_S 200mA
VDDIO_18_FC
VDDPL_33_SATA 0.020A
VDDAN_11_CLK 0.4A
VDDCR_11_USB_S 197mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDCR_11_S 113mA
VDDPL_11_SYS_S
VDDPL_33_SYS
VDDPL_33_USB_S
VDDAN_33_S
VDDXL_33_S
1.1V_S5
1.1V_S0
3.3V_S5
3.3V_S0
No Use
VDDBT_RTC_G2.5~3.6V
BAT
VGA ATI Madison / Park
TSVDD 5 mA
PCIE_VDDC 2 A
SPV10 100 mA
MPV18 150 mA
DPLL_VDDC 125 mA
SPV18 50 mA
DPLL_PVDD 75 mA
DP[F:A]_PVDD 20 mA
VDDCI 4 A
VDDR1 TBD A
PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
DP[F:A]_VDD18 330 mA
VDDC 29 A
VDD_CT 17 mA
VDDR3 60 mA
DP[F:A]_VDD10 230 mA
NorthBridge AMD RS880M
VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.1A
VDDC 1.0V-1.1V 7.6A
VDDHTRX+HT 0.68A
AVDD 0.125A
VDDA18 0.64A
VDDG33 0.06A
VDDG18 0.005A
VDD18_MEM 1.8V 0.005A
VDD_MEM 1.8V 0.23A
VDDLT18 0.22A
VDDLT33 0A
PLLs 0.23A
1.1V_S0
1.8V_S0
1.0~1.1V
3.3V_S0
No Use
VDD1DI 45 mA
VDD2DI 50 mA
AVDD 70 mA
VDDR4 TBD mA
A2VDDQ 1.5 mA
A2VDD 130 mA
1.0V
3.3V
0.85~1.1V
1.5V
1.8V
VRAM 1GB
64Mx16 (K4B1G1646E) * 8
1.5V 2.4 A
B+
PU15
ISL6265IRZ-T
+CPU_CORE
+NB_CORE
+CPU_CORE_NB
+GPU_CORE +VDDCI
+5VALW
+3VALW
PU4
SN0806081 RHBR
PU17
APW7138NITRL
PU8
RT8209BGQW
+1.5V
PU7
RT8209BGQW
+1.1VALW
PU6
RT8209BGQW
+1VSG
PU10
APL5913
+0.75VS
PU12
APL5915
+1.05VS
PU19
TSP51117RGYR U35 SI4800BDY
+1.5VS
+1.5V
+3VS
+5VS
U36
SI4800BDY
+1.1VS
+1.1VS
+1.1VALW
+1.1VALW
+1.8VSP1
+3VALW
+1.5VS
U37
SI1800BDY
+1.5V
+2.5VS
PU16
APL5508-25DC
+1.8VSP2
PU14
APL5913 PU11 MP2121DQ
+1.8VS
U34
SI4800BDY
+INVPWR_B+
+USB_VCCA
+USB_VCCB
U25/U40
TPS2061DRG4
+CPU_CORE
+CPU_CORE_NB
+1.1VS
+1.05VS
Delay +3VS_DELAY
Compal Electronics, Inc.

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3
H_CADIN2
H_CADIP2
H_CADIP1
H_CADIN3
H_CADIP4
H_CADIN5
H_CADIN4
H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIN10
H_CADIP10
H_CADIN11
H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15
H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
H_CADON[0..15] <12>H_CADIN[0..15]<12>
H_CADOP[0..15] <12>
H_CLKIN0<12>
H_CLKIN1<12> H_CLKIP1<12>
H_CTLIN1<12>
H_CLKIP0<12>
H_CTLIP1<12> H_CTLOP1 <12>
H_CLKOP1 <12>
H_CADIP[0..15]<12>
H_CLKOP0 <12>
H_CLKON0 <12>
H_CLKON1 <12>
H_CTLON1 <12>
H_CTLOP0 <12>
H_CTLON0 <12>H_CTLIN0<12> H_CTLIP0<12>
+1.1VS
+1.1VS
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
655Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
655Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
655Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
250 mil
Near CPU Socket
VLDT CAP.
TBD
C1
10U_0805_10V4Z
C1
10U_0805_10V4Z
1
2C5
180P_0402_50V8J
C5
180P_0402_50V8J
1
2
C3
0.22U_0603_16V4Z
C3
0.22U_0603_16V4Z
1
2
C6
180P_0402_50V8J
C6
180P_0402_50V8J
1
2
C4
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
1
2
C2
10U_0805_10V4Z
C2
10U_0805_10V4Z
1
2
C7
10U_0805_10V4Z
C7
10U_0805_10V4Z
12 HT LINK
JCPU1A
FOX_PZ6382A-284S-41F_Champlian
CONN@
HT LINK
JCPU1A
FOX_PZ6382A-284S-41F_Champlian
CONN@
VLDT_A3
D4 VLDT_A2
D3 VLDT_A1
D2 VLDT_A0
D1
VLDT_B3 AE5
VLDT_B2 AE4
VLDT_B1 AE3
VLDT_B0 AE2
L0_CADIN_H15
N5 L0_CADIN_L15
P5
L0_CADIN_H14
M3 L0_CADIN_L14
M4
L0_CADIN_H13
L5 L0_CADIN_L13
M5
L0_CADIN_H12
K3 L0_CADIN_L12
K4
L0_CADIN_H11
H3 L0_CADIN_L11
H4
L0_CADIN_H10
G5 L0_CADIN_L10
H5
L0_CADIN_H9
F3 L0_CADIN_L9
F4
L0_CADIN_H8
E5 L0_CADIN_L8
F5
L0_CADIN_H7
N3 L0_CADIN_L7
N2
L0_CADIN_H6
L1 L0_CADIN_L6
M1
L0_CADIN_H5
L3 L0_CADIN_L5
L2
L0_CADIN_H4
J1 L0_CADIN_L4
K1
L0_CADIN_H3
G1 L0_CADIN_L3
H1
L0_CADIN_H2
G3 L0_CADIN_L2
G2
L0_CADIN_H1
E1 L0_CADIN_L1
F1
L0_CADIN_H0
E3 L0_CADIN_L0
E2
L0_CADOUT_H15 T4
L0_CADOUT_L15 T3
L0_CADOUT_H14 V5
L0_CADOUT_L14 U5
L0_CADOUT_H13 V4
L0_CADOUT_L13 V3
L0_CADOUT_H12 Y5
L0_CADOUT_L12 W5
L0_CADOUT_H11 AB5
L0_CADOUT_L11 AA5
L0_CADOUT_H10 AB4
L0_CADOUT_L10 AB3
L0_CADOUT_H9 AD5
L0_CADOUT_L9 AC5
L0_CADOUT_H8 AD4
L0_CADOUT_L8 AD3
L0_CADOUT_H7 T1
L0_CADOUT_L7 R1
L0_CADOUT_H6 U2
L0_CADOUT_L6 U3
L0_CADOUT_H5 V1
L0_CADOUT_L5 U1
L0_CADOUT_H4 W2
L0_CADOUT_L4 W3
L0_CADOUT_H3 AA2
L0_CADOUT_L3 AA3
L0_CADOUT_H2 AB1
L0_CADOUT_L2 AA1
L0_CADOUT_H1 AC2
L0_CADOUT_L1 AC3
L0_CADOUT_H0 AD1
L0_CADOUT_L0 AC1
L0_CLKIN_H1
J5 L0_CLKIN_L1
K5
L0_CLKIN_H0
J3 L0_CLKIN_L0
J2
L0_CTLIN_H1
P3 L0_CTLIN_L1
P4
L0_CTLIN_H0
N1 L0_CTLIN_L0
P1
L0_CLKOUT_H1 Y4
L0_CLKOUT_L1 Y3
L0_CLKOUT_H0 Y1
L0_CLKOUT_L0 W1
L0_CTLOUT_H1 T5
L0_CTLOUT_L1 R5
L0_CTLOUT_H0 R2
L0_CTLOUT_L0 R3

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SMA10
DDRB_SMA7
DDRB_SMA1
DDRB_SMA12
DDRB_SMA6
DDRB_SMA11
DDRB_SMA0
DDRB_SMA9
DDRB_SMA15
DDRB_SMA3
DDRB_SMA5
DDRB_SMA8
DDRB_SMA13
DDRB_SMA2
DDRB_SMA4
DDRB_CKE1
DDRB_SDQ0
DDRB_CKE0
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQS3
DDRB_SDQS3#
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SDQS7
MEMZP
MEMZN
MEM_VREF
DDRB_ODT0
DDRB_ODT1
DDRA_ODT1
DDRA_ODT0
DDRA_CKE0
DDRA_CKE1
DDRB_SDM6
DDRB_SDM4
DDRB_SDM2
DDRB_SDM0
DDRB_SDM5
DDRB_SDM3
DDRB_SDM1
DDRB_SDM7 DDRA_SDM6
DDRA_SDM5
DDRA_SDM4
DDRA_SDM3
DDRA_SDM2
DDRA_SDM1
DDRA_SDM0
DDRA_SDM7
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS2#
DDRA_SBS1#
DDRA_SBS0#
DDRA_SMA15
DDRA_SMA12
DDRA_SMA14
DDRA_SMA13
DDRA_SMA11
DDRA_SMA10
DDRA_SMA6
DDRA_SMA1
DDRA_SMA7
DDRA_SMA2
DDRA_SMA3
DDRA_SMA8
DDRA_SMA5
DDRA_SMA4
DDRA_SMA9
DDRA_SMA0
DDRB_SMA14
DDRA_SCS1# DDRB_SCS0#
DDRB_SCS1#
DDRA_SCS0#
MEM_VREF
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
VTT_SENSE
DDRA_CLK0#
DDRA_CLK0
DDRA_CLK1#
DDRA_CLK1
DDRB_CLK0#
DDRB_CLK0
DDRB_CLK1
DDRB_CLK1#
MEM_MA_RST#
MEM_MB_RST#
DDRB_CKE1 <11>
DDRB_CKE0 <11>
DDRA_SCS0#<10> DDRA_SCS1#<10> DDRB_SCS0# <11>
DDRB_SCS1# <11>
DDRB_SDQ[63..0]<11>
DDRB_SDM[7..0]<11> DDRA_SDM[7..0] <10>
DDRA_SDQ[63..0] <10>
DDRB_SDQS7<11> DDRB_SDQS7#<11>
DDRB_SDQS6<11>
DDRB_SDQS5<11>
DDRB_SDQS4<11>
DDRB_SDQS3<11>
DDRB_SDQS2<11>
DDRB_SDQS1<11>
DDRB_SDQS0<11>
DDRB_SDQS6#<11>
DDRB_SDQS5#<11>
DDRB_SDQS4#<11>
DDRB_SDQS3#<11>
DDRB_SDQS2#<11>
DDRB_SDQS1#<11>
DDRB_SDQS0#<11>
DDRA_SDQS3 <10>
DDRA_SDQS2 <10>
DDRA_SDQS1 <10>
DDRA_SDQS0 <10>
DDRA_SDQS3# <10>
DDRA_SDQS2# <10>
DDRA_SDQS1# <10>
DDRA_SDQS0# <10>
DDRA_SDQS4 <10>
DDRA_SDQS4# <10>
DDRA_SDQS5 <10>
DDRA_SDQS5# <10>
DDRA_SDQS6 <10>
DDRA_SDQS6# <10>
DDRA_SDQS7 <10>
DDRA_SDQS7# <10>
DDRB_SRAS# <11>
DDRB_SCAS# <11>
DDRB_SWE# <11>
DDRB_SBS0# <11>
DDRB_SBS1# <11>
DDRB_SBS2# <11>
DDRA_SRAS#<10> DDRA_SCAS#<10> DDRA_SWE#<10>
DDRA_SBS0#<10> DDRA_SBS1#<10> DDRA_SBS2#<10>
DDRA_SMA[15..0]<10> DDRB_SMA[15..0] <11>
DDRB_ODT0 <11>
DDRB_ODT1 <11>
DDRA_ODT0<10> DDRA_ODT1<10>
DDRA_CKE0<10> DDRA_CKE1<10>
DDRA_CLK0<10>DDRA_CLK0#<10>
DDRA_CLK1<10>DDRA_CLK1#<10>
DDRB_CLK0 <11>
DDRB_CLK0# <11>
DDRB_CLK1 <11>
DDRB_CLK1# <11>
MEM_MA_RST#<10>
MEM_MB_RST# <11>
+1.5V
+CPU_VDDR+CPU_VDDR
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
755Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
755Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
755Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Place them
close to CPU
within 1"
Processor DDR3 Memory Interface
VDDR: DDR3 under 1033MHz
set to 0.9V to save power
1.5A
C8
1000P_0402_50V7K
C8
1000P_0402_50V7K
1
2
MEM:CMD/CTRL/CLK
JCPU1B
FOX_PZ6382A-284S-41F_Champlian
CONN@
MEM:CMD/CTRL/CLK
JCPU1B
FOX_PZ6382A-284S-41F_Champlian
CONN@
VDDR1
D10 VDDR2
C10 VDDR3
B10 VDDR4
AD10
VDDR5 W10
VDDR6 AC10
VDDR7 AB10
VDDR8 AA10
VDDR9 A10
MA1_ODT1
V19 MA1_ODT0
U21 MA0_ODT1
V22 MA0_ODT0
T19
MB1_ODT0 Y26
MB0_ODT1 W23
MB0_ODT0 W26
MB_RESET_L B18
MB1_CS_L0 U22
MB0_CS_L1 W25
MB0_CS_L0 V26 MA0_CS_L1
U19
MA1_CS_L1
V20 MA1_CS_L0
U20
MA0_CS_L0
T20
MA_ADD15
K19 MA_ADD14
K24 MA_ADD13
V24 MA_ADD12
K20 MA_ADD11
L22 MA_ADD10
R21 MA_ADD9
K22 MA_ADD8
L19 MA_ADD7
L21 MA_ADD6
M24 MA_ADD5
L20 MA_ADD4
M22 MA_ADD3
M19 MA_ADD2
N22 MA_ADD1
M20 MA_ADD0
N21
MA_BANK2
J21 MA_BANK1
R23 MA_BANK0
R20
MA_RAS_L
R19 MA_CAS_L
T22 MA_WE_L
T24
MEMZP
AF10 MEMZN
AE10 VDDR_SENSE Y10
MEMVREF W17
MA_CLK_H4
P19 MA_CLK_L4
P20
MA_CLK_H7
Y16 MA_CLK_L7
AA16
MA_CLK_H1
E16 MA_CLK_L1
F16
MA_CLK_H5
N19 MA_CLK_L5
N20
MB_CLK_H4 R26
MB_CLK_L4 R25
MB_CLK_H7 AF18
MB_CLK_L7 AF17
MB_CLK_H1 A17
MB_CLK_L1 A18
MB_CLK_H5 P22
MB_CLK_L5 R22
MA_CKE0
J22 MA_CKE1
J20 MB_CKE0 J25
MB_CKE1 H26
MB_ADD15 J24
MB_ADD14 J23
MB_ADD13 W24
MB_ADD12 L25
MB_ADD11 L26
MB_ADD10 T26
MB_ADD9 K26
MB_ADD8 M26
MB_ADD7 L24
MB_ADD6 N25
MB_ADD5 L23
MB_ADD4 N26
MB_ADD3 N23
MB_ADD2 P26
MB_ADD1 N24
MB_ADD0 P24
MB_BANK2 J26
MB_BANK1 U26
MB_BANK0 R24
MB_RAS_L U25
MB_CAS_L U24
MB_WE_L U23
MA_RESET_L
H16
R1
1K_0402_1%
R1
1K_0402_1%
1 2
R5 39.2_0402_1%R5 39.2_0402_1%
1 2
R2
1K_0402_1%
R2
1K_0402_1%
1 2
T1PAD T1PAD
C588
10U_0805_10V4Z
@
C588
10U_0805_10V4Z
@1
2
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
MEM:DATA
JCPU1C
FOX_PZ6382A-284S-41F_Champlian
CONN@
MEM:DATA
JCPU1C
FOX_PZ6382A-284S-41F_Champlian
CONN@
MB_DATA63
AD11 MB_DATA62
AF11 MB_DATA61
AF14 MB_DATA60
AE14 MB_DATA59
Y11 MB_DATA58
AB11 MB_DATA57
AC12 MB_DATA56
AF13 MB_DATA55
AF15 MB_DATA54
AF16 MB_DATA53
AC18 MB_DATA52
AF19 MB_DATA51
AD14 MB_DATA50
AC14 MB_DATA49
AE18 MB_DATA48
AD18 MB_DATA47
AD20 MB_DATA46
AC20 MB_DATA45
AF23 MB_DATA44
AF24 MB_DATA43
AF20 MB_DATA42
AE20 MB_DATA41
AD22 MB_DATA40
AC22 MB_DATA39
AE25 MB_DATA38
AD26 MB_DATA37
AA25 MB_DATA36
AA26 MB_DATA35
AE24 MB_DATA34
AD24 MB_DATA33
AA23 MB_DATA32
AA24 MB_DATA31
G24 MB_DATA30
G23 MB_DATA29
D26 MB_DATA28
C26 MB_DATA27
G26 MB_DATA26
G25 MB_DATA25
E24 MB_DATA24
E23 MB_DATA23
C24 MB_DATA22
B24 MB_DATA21
C20 MB_DATA20
B20 MB_DATA19
C25 MB_DATA18
D24 MB_DATA17
A21 MB_DATA16
D20 MB_DATA15
D18 MB_DATA14
C18 MB_DATA13
D14 MB_DATA12
C14 MB_DATA11
A20 MB_DATA10
A19 MB_DATA9
A16 MB_DATA8
A15 MB_DATA7
A13 MB_DATA6
D12 MB_DATA5
E11 MB_DATA4
G11 MB_DATA3
B14 MB_DATA2
A14 MB_DATA1
A11 MB_DATA0
C11
MA_DATA63 AA12
MA_DATA62 AB12
MA_DATA61 AA14
MA_DATA60 AB14
MA_DATA59 W11
MA_DATA58 Y12
MA_DATA57 AD13
MA_DATA56 AB13
MA_DATA55 AD15
MA_DATA54 AB15
MA_DATA53 AB17
MA_DATA52 Y17
MA_DATA51 Y14
MA_DATA50 W14
MA_DATA49 W16
MA_DATA48 AD17
MA_DATA47 Y18
MA_DATA46 AD19
MA_DATA45 AD21
MA_DATA44 AB21
MA_DATA43 AB18
MA_DATA42 AA18
MA_DATA41 AA20
MA_DATA40 Y20
MA_DATA39 AA22
MA_DATA38 Y22
MA_DATA37 W21
MA_DATA36 W22
MA_DATA35 AA21
MA_DATA34 AB22
MA_DATA33 AB24
MA_DATA32 Y24
MA_DATA31 H22
MA_DATA30 H20
MA_DATA29 E22
MA_DATA28 E21
MA_DATA27 J19
MA_DATA26 H24
MA_DATA25 F22
MA_DATA24 F20
MA_DATA23 C23
MA_DATA22 B22
MA_DATA21 F18
MA_DATA20 E18
MA_DATA19 E20
MA_DATA18 D22
MA_DATA17 C19
MA_DATA16 G18
MA_DATA15 G17
MA_DATA14 C17
MA_DATA13 F14
MA_DATA12 E14
MA_DATA11 H17
MA_DATA10 E17
MA_DATA9 E15
MA_DATA8 H15
MA_DATA7 E13
MA_DATA6 C13
MA_DATA5 H12
MA_DATA4 H11
MA_DATA3 G14
MA_DATA2 H14
MA_DATA1 F12
MA_DATA0 G12
MB_DM7
AD12 MB_DM6
AC16 MB_DM5
AE22 MB_DM4
AB26 MB_DM3
E25 MB_DM2
A22 MB_DM1
B16 MB_DM0
A12
MB_DQS_H7
AF12 MB_DQS_L7
AE12
MB_DQS_H6
AE16 MB_DQS_L6
AD16
MB_DQS_H5
AF21 MB_DQS_L5
AF22
MB_DQS_H4
AC25 MB_DQS_L4
AC26
MB_DQS_H3
F26 MB_DQS_L3
E26
MB_DQS_H2
A24 MB_DQS_L2
A23
MB_DQS_H1
D16 MB_DQS_L1
C16
MB_DQS_H0
C12 MB_DQS_L0
B12
MA_DM7 Y13
MA_DM6 AB16
MA_DM5 Y19
MA_DM4 AC24
MA_DM3 F24
MA_DM2 E19
MA_DM1 C15
MA_DM0 E12
MA_DQS_H7 W12
MA_DQS_L7 W13
MA_DQS_H6 Y15
MA_DQS_L6 W15
MA_DQS_H5 AB19
MA_DQS_L5 AB20
MA_DQS_H4 AD23
MA_DQS_L4 AC23
MA_DQS_H3 G22
MA_DQS_L3 G21
MA_DQS_H2 C22
MA_DQS_L2 C21
MA_DQS_H1 G16
MA_DQS_L1 G15
MA_DQS_H0 G13
MA_DQS_L0 H13
R368
0_0402_5%
R368
0_0402_5%
1 2
C9
0.01U_0402_25V7K
C9
0.01U_0402_25V7K
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_TDO
CPU_HTREF0
CPU_HTREF1
CPU_DBRDY
CPU_TMS
CPU_TEST19
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
LDT_RST#
H_PWRGD
LDT_STOP#
LDT_STOP#
CPU_SID
CPU_SIC
CPU_CLKIN_SC_N
CPU_TDI
CPU_TRST#
CPU_TCK CPU_DBREQ#
CPU_TDO
CPU_SVC
CPU_SVD
CPU_TEST20
CPU_TEST21
CPU_TEST24
CPU_TEST22
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST17
CPU_TEST16
CPU_TEST14
CPU_TEST15
LDT_RST#
H_PWRGD
LDT_RST#
CPU_SVC
CPU_SVD
CPU_TEST27
H_PROCHOT#
THERMDA_CPU
THERMDC_CPU
EC_SMB_CK2
EC_SMB_DA2
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_TEST18
HDT_RST#
CPU_TEST12
CPU_TEST25H
CPU_TEST25L
CPU_TEST20
CPU_TEST21
CPU_TRST#
CPU_TDI
CPU_TMS
CPU_TCK
CPU_DBRDY
THERMDA_CPU
THERMDC_CPU
H_PROCHOT#
CPU_TEST22
CPU_TEST24
CPU_SID
CPU_SIC
SB_SID
SB_SIC
EC_SMB_DA
EC_SMB_CK
EC_SMB_DA2
EC_SMB_CK2
CPU_DBREQ#
CPU_TEST25H
CPU_TEST25L
CPU_THERMTRIP#_R
CPU_TEST19
CPU_TEST18
CPU_TEST12
CPU_TEST27
CPU_VDD1_FB_L
CPU_VDD1_FB_H
CPU_TEST23
CPU_TEST23
H_PWRGD<26>
LDT_STOP#<13,26>
LDT_RST#<26>
SB_PWRGD <13,27,36>
CPU_VDDNB_FB_H <52>
CPU_VDDNB_FB_L <52>
CPU_VDD0_FB_H<52> CPU_VDD0_FB_L<52>
CLK_CPU_BCLK<22>
CLK_CPU_BCLK#<22>
EC_SMB_DA2 <16,36>
EC_SMB_CK2 <16,36>
CPU_SVD <52>
CPU_SVC <52>
H_PROCHOT_R# <26>
H_THERMTRIP# <27>
SB_SID <27>
SB_SIC <27>
MAINPWON <44,45,49>
CPU_VDD1_FB_H<52> CPU_VDD1_FB_L<52>
+1.1VS
+2.5VDDA
+2.5VS
+3VS
+1.5V
+1.5VS
+1.5VS
+1.5VS
+3VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+3VS
+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
855Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
855Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
855Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
VDDA=0.25A
Address
1001 100X b
CPU internal thermal sensor
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
2.09V for Gate
Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB
LDT_RES# / MEMHOT#
no support in S1g4
T0 SB
T0 SB
TO EC
TO EC
PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition
For SCAN connect use
change to SGA00002N80
C20
0.1U_0402_16V4Z
C20
0.1U_0402_16V4Z
1
2
R6
10K_0402_5%
R6
10K_0402_5%
12
R27 510_0402_5%R27 510_0402_5%
1 2
R30 1K_0402_5%R30 1K_0402_5%
1 2
R35 1K_0402_5%R35 1K_0402_5%
1 2
C14
0.22U_0603_16V4Z
C14
0.22U_0603_16V4Z
1
2
C16 3900P_0402_50V7K C16 3900P_0402_50V7K
1 2
G
D S
Q3
BSH111 1N_SOT23-3
G
D S
Q3
BSH111 1N_SOT23-3
2
13
R21
300_0402_5%
R21
300_0402_5%
1 2
R29 1K_0402_5%R29 1K_0402_5%
1 2
R14 1K_0402_5%R14 1K_0402_5%
1 2
R34 1K_0402_5%R34 1K_0402_5%
1 2
R16 44.2_0402_1%R16 44.2_0402_1%
1 2
R41
31.6K_0402_1%
R41
31.6K_0402_1%
12
R22 510_0402_5%R22 510_0402_5%
1 2
JCPU1D
FOX_PZ6382A-284S-41F_Champlian
CONN@
JCPU1D
FOX_PZ6382A-284S-41F_Champlian
CONN@
VDDA1
F8 VDDA2
F9
RESET_L
B7 PWROK
A7 LDTSTOP_L
F10
SIC
AF4 SID
AF5
HT_REF1
P6 HT_REF0
R6
VDD0_FB_H
F6 VDD0_FB_L
E6 VDDIO_FB_H W9
VDDIO_FB_L Y9
THERMTRIP_L AF6
PROCHOT_L AC7
RSVD2
A5
LDTREQ_L
C6
SVC A6
SVD A4
RSVD6 C5
RSVD4
B5
RSVD1
A3
CLKIN_H
A9 CLKIN_L
A8
DBRDY
G10 TMS
AA9 TCK
AC9 TRST_L
AD9 TDI
AF9
DBREQ_L E10
TDO AE9
TEST25_H
E9 TEST25_L
E8
TEST19
G9 TEST18
H10
RSVD8 AA7
TEST9
C2
TEST17 D7
TEST16 E7
TEST15 F7
TEST14 C7
TEST12
AC8
TEST7 C3
TEST6
AA6
THERMDC W7
THERMDA W8
VDD1_FB_H
Y6 VDD1_FB_L
AB6
TEST29_H C9
TEST29_L C8
TEST24
AE7
TEST23
AD7
TEST22
AE8
TEST21
AB8 TEST20
AF7
TEST28_H J7
TEST28_L H8
TEST27
AF8
ALERT_L
AE6
TEST10 K8
TEST8 C4
RSVD3
B3
RSVD5
C1
VDDNB_FB_H H6
VDDNB_FB_L G6
RSVD7 D5
RSVD11 W18
MEMHOT_L AA8
RSVD10 H18
RSVD9 H19
VSS M11
T2 PADT2 PAD
R19 1K_0402_5%R19 1K_0402_5%
1 2
C21
100P_0402_50V8J
@
C21
100P_0402_50V8J
@
1 2
R10
169_0402_1%
R10
169_0402_1%
12
U2
NC7SZ08P5X_NL_SC70-5
U2
NC7SZ08P5X_NL_SC70-5
B2
A1
Y
4
P5
G
3
T8PAD T8PAD
T5PAD T5PAD
R45 0_0402_5%R45 0_0402_5%
1 2
R265 1K_0402_5%R265 1K_0402_5%
1 2
R9 0_0402_5%@R9 0_0402_5%@
1 2
C17
0.01U_0402_25V4Z
@
C17
0.01U_0402_25V4Z
@
1
2
C15 3900P_0402_50V7KC15 3900P_0402_50V7K
1 2
R18
300_0402_5%
R18
300_0402_5%
1 2
R47 0_0402_5%R47 0_0402_5%
1 2
R37220_0402_5%
@
R37220_0402_5%
@
12
C22 0.1U_0402_16V4ZC22 0.1U_0402_16V4Z
1 2
R40300_0402_5% R40300_0402_5%
1 2
C19
0.01U_0402_25V4Z
@
C19
0.01U_0402_25V4Z
@
1
2
R32 1K_0402_5%R32 1K_0402_5%
1 2
R39300_0402_5%
@
R39300_0402_5%
@
12
R13 0_0402_5%R13 0_0402_5%
1 2
R8 0_0402_5%R8 0_0402_5%
1 2
L1
FBMA-L11-201209-221LMA30T_0805
L1
FBMA-L11-201209-221LMA30T_0805
1 2
C124.7U_0805_10V4Z C124.7U_0805_10V4Z
1
2
R20 1K_0402_5%R20 1K_0402_5%
1 2
R11 300_0402_5%R11 300_0402_5%
1 2
G
D S
Q2
BSH111 1N_SOT23-3
G
D S
Q2
BSH111 1N_SOT23-3
2
13
R38220_0402_5%
@
R38220_0402_5%
@
12
R23 510_0402_5%@R23 510_0402_5%@
1 2
R44 0_0402_5%
@
R44 0_0402_5%
@
1 2
R46 0_0402_5%
@
R46 0_0402_5%
@
1 2
T7PAD T7PAD
R12 1K_0402_5%R12 1K_0402_5%
1 2
U1
ADM1032ARMZ_MSOP8
@U1
ADM1032ARMZ_MSOP8
@
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
R43 0_0402_5%@ R43 0_0402_5%@
1 2
T3PAD T3PAD
R26 510_0402_5%@R26 510_0402_5%@
1 2
C13
3300P_0402_50V7K
C13
3300P_0402_50V7K
1
2
R17
300_0402_5%
R17
300_0402_5%
1 2
R15 44.2_0402_1%R15 44.2_0402_1%
1 2
E
B
C
Q1
MMBT3904_NL_SOT23-3
E
B
C
Q1
MMBT3904_NL_SOT23-3
2
3 1
R42
30K_0402_1%
R42
30K_0402_1%
12
R28 1K_0402_5%R28 1K_0402_5%
1 2
R25 80.6_0402_1%R25 80.6_0402_1%
12
SAMTEC_ASP-68200-07
JP2
CONN@ SAMTEC_ASP-68200-07
JP2
CONN@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
R36220_0402_5%
@
R36220_0402_5%
@
12
R24 0_0402_5%R24 0_0402_5%
1 2
+
C11
150U_B_6.3VM_R40M
+
C11
150U_B_6.3VM_R40M
1
2R7
1K_0402_5%
R7
1K_0402_5%
1 2
T6PAD T6PAD
C18
0.01U_0402_25V4Z
@
C18
0.01U_0402_25V4Z
@
1
2
R31 1K_0402_5%R31 1K_0402_5%
1 2
R33 1K_0402_5%R33 1K_0402_5%
1 2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+CPU_CORE
+CPU_VDDR
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.5V
+1.5V
+1.5V
+1.5V +1.5V
+CPU_VDDR
+CPU_VDDR
+CPU_CORE_NB
+1.5V
+1.5V
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
955Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
955Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
955Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Athlon 64 S1
Processor Socket
Near CPU Socket
VDDR decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling. +CPU_CORE_NB decoupling.
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Socket
4A
36A
TBD
change to SGA00002N80
JCPU1E
FOX_PZ6382A-284S-41F_Champlian
CONN@
JCPU1E
FOX_PZ6382A-284S-41F_Champlian
CONN@
VDD1_25 AC4
VDD1_26 AD2
VDD0_1
G4 VDD0_2
H2 VDD0_3
J9 VDD0_4
J11 VDD0_5
J13
VDD0_7
K6 VDD0_8
K10 VDD0_9
K12 VDD0_10
K14 VDD0_11
L4 VDD0_12
L7 VDD0_13
L9 VDD0_14
L11 VDD0_15
L13
VDD0_17
M2 VDD0_18
M6 VDD0_19
M8 VDD0_20
M10 VDD0_21
N7 VDD0_22
N9 VDD0_23
N11
VDD1_1 P8
VDD1_2 P10
VDD1_3 R4
VDD1_4 R7
VDD1_5 R9
VDD1_6 R11
VDD1_7 T2
VDD1_8 T6
VDD1_9 T8
VDD1_10 T10
VDD1_11 T12
VDD1_12 T14
VDD1_13 U7
VDD1_14 U9
VDD1_15 U11
VDD1_16 U13
VDD1_18 V6
VDD1_19 V8
VDD1_20 V10
VDD1_21 V12
VDD1_22 V14
VDD1_23 W4
VDD1_24 Y2
VDD0_6
J15
VDDNB_1
K16
VDD0_16
L15
VDDNB_2
M16 VDDNB_3
P16 VDDNB_4
T16
VDD1_17 U15
VDDNB_5
V16
VDDIO1
H25 VDDIO2
J17 VDDIO3
K18 VDDIO4
K21 VDDIO5
K23 VDDIO6
K25 VDDIO7
L17 VDDIO8
M18 VDDIO9
M21 VDDIO10
M23 VDDIO11
M25 VDDIO12
N17 VDDIO13 P18
VDDIO14 P21
VDDIO15 P23
VDDIO16 P25
VDDIO17 R17
VDDIO18 T18
VDDIO19 T21
VDDIO20 T23
VDDIO21 T25
VDDIO22 U17
VDDIO23 V18
VDDIO24 V21
VDDIO25 V23
VDDIO26 V25
VDDIO27 Y25
C41
180P_0402_50V8J
C41
180P_0402_50V8J
1
2
C46
0.22U_0603_16V4Z
C46
0.22U_0603_16V4Z
1
2
C51
0.22U_0603_16V4Z
C51
0.22U_0603_16V4Z
1
2
C61
1000P_0402_50V7K
C61
1000P_0402_50V7K
1
2
C78
0.22U_0603_16V4Z
C78
0.22U_0603_16V4Z
1
2
C65
0.01U_0402_25V4Z
C65
0.01U_0402_25V4Z
1
2
C58
4.7U_0805_10V4Z
C58
4.7U_0805_10V4Z
1
2
C32
22U_0805_6.3V6M
C32
22U_0805_6.3V6M
1
2
C28
22U_0805_6.3V6M
C28
22U_0805_6.3V6M
1
2
C355
0.22U_0603_16V4Z
C355
0.22U_0603_16V4Z
1
2
C49
22U_0805_6.3V6M
C49
22U_0805_6.3V6M
1
2
C79
0.22U_0603_16V4Z
C79
0.22U_0603_16V4Z
1
2
+
C25
330U_X_2VM_R6M
+
C25
330U_X_2VM_R6M
1
2
C34
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
1
2
C66
0.1U_0402_16V7K
C66
0.1U_0402_16V7K
1
2
C354
0.22U_0603_16V4Z
C354
0.22U_0603_16V4Z
1
2
C72
4.7U_0805_10V4Z
C72
4.7U_0805_10V4Z
1
2
+
C56
150U_B_6.3VM_R40M
+
C56
150U_B_6.3VM_R40M
1
2
C60
0.22U_0603_16V4Z
C60
0.22U_0603_16V4Z
1
2
+
C24
330U_X_2VM_R6M
+
C24
330U_X_2VM_R6M
1
2
C29
22U_0805_6.3V6M
C29
22U_0805_6.3V6M
1
2
C59
0.22U_0603_16V4Z
C59
0.22U_0603_16V4Z
1
2
C73
4.7U_0805_10V4Z
C73
4.7U_0805_10V4Z
1
2
C33
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
1
2
C67
0.1U_0402_16V7K
C67
0.1U_0402_16V7K
1
2
C55
22U_0805_6.3V6M
C55
22U_0805_6.3V6M
1
2
C76
4.7U_0805_10V4Z
C76
4.7U_0805_10V4Z
1
2
C77
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
1
2
C38
180P_0402_50V8J
C38
180P_0402_50V8J
1
2
C54
0.22U_0603_16V4Z
C54
0.22U_0603_16V4Z
1
2
C80
1000P_0402_50V7K
C80
1000P_0402_50V7K
1
2
C64
0.01U_0402_25V4Z
C64
0.01U_0402_25V4Z
1
2
C39
0.22U_0603_16V4Z
C39
0.22U_0603_16V4Z
1
2
C63
180P_0402_50V8J
C63
180P_0402_50V8J
1
2
C69
180P_0402_50V8J
C69
180P_0402_50V8J
1
2
C35
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
1
2
C57
4.7U_0805_10V4Z
C57
4.7U_0805_10V4Z
1
2
C48
180P_0402_50V8J
C48
180P_0402_50V8J
1
2
C68
180P_0402_50V8J
C68
180P_0402_50V8J
1
2
+
C27
330U_X_2VM_R6M
@
+
C27
330U_X_2VM_R6M
@
1
2
C70
180P_0402_50V8J
C70
180P_0402_50V8J
1
2
C52
0.22U_0603_16V4Z
C52
0.22U_0603_16V4Z
1
2
C30
22U_0805_6.3V6M
C30
22U_0805_6.3V6M
1
2
+
C75
330U_X_2VM_R6M
+
C75
330U_X_2VM_R6M
1
2
C43
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
1
2
C42
22U_0805_6.3V6M
C42
22U_0805_6.3V6M
1
2
C37
0.01U_0402_25V4Z
C37
0.01U_0402_25V4Z
1
2
C36
0.22U_0603_16V4Z
C36
0.22U_0603_16V4Z
1
2
C31
22U_0805_6.3V6M
C31
22U_0805_6.3V6M
1
2
C53
0.22U_0603_16V4Z
C53
0.22U_0603_16V4Z
1
2
C82
180P_0402_50V8J
C82
180P_0402_50V8J
1
2
C83
180P_0402_50V8J
C83
180P_0402_50V8J
1
2
C47
0.22U_0603_16V4Z
C47
0.22U_0603_16V4Z
1
2
C62
1000P_0402_50V7K
C62
1000P_0402_50V7K
1
2
+
C23
330U_X_2VM_R6M
+
C23
330U_X_2VM_R6M
1
2
C44
22U_0805_6.3V6M
C44
22U_0805_6.3V6M
1
2
+
C26
330U_X_2VM_R6M
+
C26
330U_X_2VM_R6M
1
2
C45
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
1
2
JCPU1F
FOX_PZ6382A-284S-41F_Champlian
CONN@
JCPU1F
FOX_PZ6382A-284S-41F_Champlian
CONN@
VSS1
AA4 VSS2
AA11 VSS3
AA13 VSS4
AA15 VSS5
AA17 VSS6
AA19 VSS7
AB2 VSS8
AB7 VSS9
AB9 VSS10
AB23 VSS11
AB25 VSS12
AC11 VSS13
AC13 VSS14
AC15 VSS15
AC17 VSS16
AC19 VSS17
AC21 VSS18
AD6 VSS19
AD8 VSS20
AD25 VSS21
AE11 VSS22
AE13 VSS23
AE15 VSS24
AE17 VSS25
AE19 VSS26
AE21 VSS27
AE23 VSS28
B4 VSS29
B6 VSS30
B8 VSS31
B9 VSS32
B11 VSS33
B13 VSS34
B15 VSS35
B17 VSS36
B19 VSS37
B21 VSS38
B23 VSS39
B25 VSS40
D6 VSS41
D8 VSS42
D9 VSS43
D11 VSS44
D13 VSS45
D15 VSS46
D17 VSS47
D19 VSS48
D21 VSS49
D23 VSS50
D25 VSS51
E4 VSS52
F2 VSS53
F11 VSS54
F13 VSS55
F15 VSS56
F17 VSS57
F19 VSS58
F21 VSS59
F23 VSS60
F25 VSS61
H7 VSS62
H9 VSS63
H21 VSS64
H23 VSS65
J4
VSS66 J6
VSS67 J8
VSS68 J10
VSS69 J12
VSS70 J14
VSS71 J16
VSS72 J18
VSS73 K2
VSS74 K7
VSS75 K9
VSS76 K11
VSS77 K13
VSS78 K15
VSS79 K17
VSS80 L6
VSS81 L8
VSS82 L10
VSS83 L12
VSS84 L14
VSS85 L16
VSS86 L18
VSS87 M7
VSS88 M9
VSS89 AC6
VSS90 M17
VSS91 N4
VSS92 N8
VSS93 N10
VSS94 N16
VSS95 N18
VSS96 P2
VSS97 P7
VSS98 P9
VSS99 P11
VSS100 P17
VSS101 R8
VSS102 R10
VSS103 R16
VSS104 R18
VSS105 T7
VSS106 T9
VSS107 T11
VSS108 T13
VSS109 T15
VSS110 T17
VSS111 U4
VSS112 U6
VSS113 U8
VSS114 U10
VSS115 U12
VSS116 U14
VSS117 U16
VSS118 U18
VSS119 V2
VSS120 V7
VSS121 V9
VSS122 V11
VSS123 V13
VSS124 V15
VSS125 V17
VSS126 W6
VSS127 Y21
VSS128 Y23
VSS129 N6
C81
1000P_0402_50V7K
C81
1000P_0402_50V7K
1
2
C74
4.7U_0805_10V4Z
C74
4.7U_0805_10V4Z
1
2
C50
180P_0402_50V8J
C50
180P_0402_50V8J
1
2
C40
0.01U_0402_25V4Z
C40
0.01U_0402_25V4Z
1
2
C71
4.7U_0805_10V4Z
C71
4.7U_0805_10V4Z
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ[0..63]
DDRA_SMA[0..15]
DDRA_SDM[0..7]
DDRA_SDQ36
DDRA_SDQ63
DDRA_SDQ26
DDRA_SDQS6
DDRA_SDQ2
DDRA_SDQ5
DDRA_SDQ22
DDRA_SDQ25
DDRA_SDQ35
DDRA_SMA12
DDRA_SDQ14
DDRA_SDQS0#
DDRA_SDQS4
DDRA_SDM6
DDRA_SDQ42
DDRA_CKE1
DDRA_SDQ27
DDRA_SMA15
DDRA_SDQ31
DDRA_CKE0
DDRA_SDQ12
DDRA_SDQ59
DDRA_SMA3
DDRA_SDQ6
DDRA_SCS1#
DDRA_SDQ39
DDRA_SBS1#
DDRA_SWE#
DDRA_SMA7
DDRA_SDQS0
DDRA_SMA0
DDRA_SDM2
DDRA_SDQS7
DDRA_SDM1
DDRA_SDQ57
DDRA_SDQ46
DDRA_SDQ0
DDRA_SDQ28
DDRA_SDM0
DDRA_SDQS5#
DDRA_SDQ51
DDRA_SDQ19
DDRA_SDM4
DDRA_SDQ4
DDRA_SDQ30
DDRA_SDQS2
DDRA_SDQ44
DDRA_SRAS#
DDRA_SDQ33
DDRA_SDQ58
DDRA_SDM5
DDRA_SDQS3
DDRA_SMA8
DDRA_SCS0#
DDRA_SDQ10
DDRA_SMA6
DDRA_SMA10
DDRA_SDQ3
MEM_MA_RST#
DDRA_SDQS7#
DDRA_SDQS6#
DDRA_SDQ1
DDRA_SDQ40
DDRA_SMA9
DDRA_SDQ16
DDRA_SDQ29
DDRA_SDQS4#
DDRA_SDQ52
DDRA_SDM3
DDRA_SDQS5
DDRA_SDQ54
DDRA_SDQ49
DDRA_SBS2#
DDRA_SDQ45
DDRA_SDQ9
DDRA_SDM7
DDRA_SMA1
DDRA_SDQ7
DDRA_SDQ13
DDRA_SDQ20
DDRA_SDQ60
DDRA_SBS0#
DDRA_SCAS# DDRA_ODT0
DDRA_SDQ37
DDRA_SMA5
DDRA_SDQS1#
DDRA_SMA14
DDRA_SDQ55
DDRA_SMA4
DDRA_SDQ21
DDRA_SDQ62
DDRA_SDQ24
DDRA_SDQ15
DDRA_SDQ56
DDRA_SDQ23
DDRA_SDQ53
DDRA_SDQ47
DDRA_ODT1
DDRA_SDQ18
DDRA_SDQ43
DDRA_SDQ34
DDRA_CLK1
DDRA_CLK1#
DDRA_SDQ48
DDRA_SDQS2#
DDRA_SDQ11
DDRA_SDQ38
DDRA_CLK0
DDRA_CLK0#
DDRA_SDQ32
DDRA_SDQS3#
DDRA_SMA13
DDRA_SMA11
DDRA_SDQ50
DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ61
DDRA_SMA2
DDRA_SDQ41
DDRA_SDQ17
+VREF_DQ +VREF_CA
DDRA_SMA[0..15] <7>
DDRA_SDQ[0..63] <7>
DDRA_SDM[0..7] <7>
DDRA_CKE0<7>
DDRA_SCS1#<7>
DDRA_SBS1# <7>
DDRA_SWE#<7>
DDRA_SRAS# <7>
DDRA_SCS0# <7>
MEM_MA_RST# <7>
DDRA_SBS2#<7>
DDRA_SBS0#<7>
DDRA_SCAS#<7> DDRA_ODT0 <7>
DDRA_ODT1 <7>
DDRA_CLK1# <7>
DDRA_CLK1 <7>
DDRA_CLK0<7> DDRA_CLK0#<7>
DDRA_CKE1 <7>
SB_SMDAT0 <11,22,27,34>
SB_SMCLK0 <11,22,27,34>
DDRA_SDQS3 <7>
DDRA_SDQS0 <7>
DDRA_SDQS3# <7>
DDRA_SDQS0# <7>
DDRA_SDQS5 <7>
DDRA_SDQS5# <7>
DDRA_SDQS7 <7>
DDRA_SDQS7# <7>
DDRA_SDQS1#<7> DDRA_SDQS1<7>
DDRA_SDQS2#<7> DDRA_SDQS2<7>
DDRA_SDQS4#<7> DDRA_SDQS4<7>
DDRA_SDQS6#<7> DDRA_SDQS6<7>
+1.5V
+0.75VS
+3VS
+1.5V +1.5V
+3VS
+VREF_DQ
+VREF_DQ
+VREF_CA
+1.5V
+0.75VS
+1.5V+VREF_CA
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
10 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
10 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
10 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
DIMM_A STD H:8mm
<Address: 00>
Place near DIMM1
C10
1000P_0402_50V7K
C10
1000P_0402_50V7K
1
2
R51
10K_0402_5%
R51
10K_0402_5%
12
R50 10K_0402_5% R50 10K_0402_5%
1 2
C961
4.7U_0603_6.3V6K
C961
4.7U_0603_6.3V6K
1
2
C643
0.1U_0402_16V4Z
C643
0.1U_0402_16V4Z
1
2
C644
0.1U_0402_16V4Z
C644
0.1U_0402_16V4Z
1
2
C84
4.7U_0805_10V4Z
@
C84
4.7U_0805_10V4Z
@
1
2
C91
0.1U_0402_16V4Z
C91
0.1U_0402_16V4Z
1
2
C645
0.1U_0402_16V4Z
C645
0.1U_0402_16V4Z
1
2
C85
0.01U_0402_25V7K
C85
0.01U_0402_25V7K
1
2C680
1000P_0402_50V7K
C680
1000P_0402_50V7K
1
2
T9PAD T9PAD
C235
4.7U_0805_10V4Z
@
C235
4.7U_0805_10V4Z
@
1
2
C89
1000P_0402_50V7K
C89
1000P_0402_50V7K
1
2
R310
1K_0402_1%
R310
1K_0402_1%
1 2
C88
0.1U_0402_16V4Z
C88
0.1U_0402_16V4Z
1
2
C646
0.1U_0402_16V4Z
C646
0.1U_0402_16V4Z
1
2
R49
1K_0402_1%
R49
1K_0402_1%
1 2
C640
0.1U_0402_16V4Z
C640
0.1U_0402_16V4Z
1
2
R48
1K_0402_1%
R48
1K_0402_1%
1 2
C90
2.2U_0603_6.3V4Z
C90
2.2U_0603_6.3V4Z
1
2
C647
0.1U_0402_16V4Z
C647
0.1U_0402_16V4Z
1
2
C641
0.1U_0402_16V4Z
C641
0.1U_0402_16V4Z
1
2
C664
0.1U_0402_16V4Z
C664
0.1U_0402_16V4Z
1
2
C351
0.01U_0402_25V7K
C351
0.01U_0402_25V7K
1
2
R315
1K_0402_1%
R315
1K_0402_1%
1 2
C87
0.1U_0402_16V4Z
C87
0.1U_0402_16V4Z
1
2
C642
0.1U_0402_16V4Z
C642
0.1U_0402_16V4Z
1
2
JDIMM1
FOX_AS0A626-U8SN-7F
CONN@
JDIMM1
FOX_AS0A626-U8SN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C665
0.1U_0402_16V4Z
C665
0.1U_0402_16V4Z
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SDQ[0..63]
DDRB_SMA[0..15]
DDRB_SDM[0..7]
+VREF_DQ
DDRB_SDQS6
DDRB_SDQ26
DDRB_SDQ63
DDRB_SDQ36
DDRB_SDQ35
DDRB_SDQ25
DDRB_SDQ22
DDRB_SDQ5
DDRB_SDQ2
DDRB_SDQS0#
DDRB_SDQ14
DDRB_SMA12
DDRB_CKE1
DDRB_SDQ42
DDRB_SDM6
DDRB_SDQS4
DDRB_SMA15
DDRB_SDQ27
DDRB_SDQ12
DDRB_CKE0
DDRB_SDQ31
DDRB_SMA3
DDRB_SDQ59
DDRB_SBS1#
DDRB_SDQ39
DDRB_SCS1#
DDRB_SDQ6
DDRB_SDQS0
DDRB_SMA7
DDRB_SWE#
DDRB_SMA0
DDRB_SDM2
DDRB_SDQ0
DDRB_SDQ46
DDRB_SDQ57
DDRB_SDM1
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQ28
DDRB_SDM4
DDRB_SDQ19
DDRB_SDQ51
DDRB_SDQS5#
DDRB_SDQS2
DDRB_SDQ30
DDRB_SDQ4
DDRB_SDQ33
DDRB_SRAS#
DDRB_SDQ44
DDRB_SDQS3
DDRB_SDM5
DDRB_SDQ58
DDRB_SMA8
DDRB_SCS0#
DDRB_SMA10
DDRB_SMA6
DDRB_SDQ10
DDRB_SDQS6#
DDRB_SDQS7#
MEM_MB_RST#
DDRB_SDQ3
DDRB_SDQ16
DDRB_SMA9
DDRB_SDQ1
DDRB_SDQS4#
DDRB_SDQ29
DDRB_SDQ49
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDM3
DDRB_SDQ9
DDRB_SDQ45
DDRB_SBS2#
DDRB_SDQ20
DDRB_SDQ13
DDRB_SDQ7
DDRB_SMA1
DDRB_SDM7
DDRB_SBS0#
DDRB_SDQ60
DDRB_SDQ37
DDRB_ODT0DDRB_SCAS#
DDRB_SDQ55
DDRB_SMA14
DDRB_SDQS1#
DDRB_SMA5
DDRB_SDQ21
DDRB_SMA4
DDRB_SDQ62
DDRB_SDQ15
DDRB_SDQ24
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ23
DDRB_SDQ56
DDRB_SDQ43
DDRB_SDQ18
DDRB_ODT1
DDRB_CLK1#
DDRB_CLK1
DDRB_SDQ34
DDRB_SDQS2#
DDRB_SDQ48
DDRB_CLK0#
DDRB_CLK0
DDRB_SDQ11
DDRB_SDQ50
DDRB_SMA11
DDRB_SMA13
DDRB_SDQS3#
DDRB_SDQ32
DDRB_SMA2
DDRB_SDQ61
DDRB_SDQS1
DDRB_SDQ8
DDRB_SDQ17
DDRB_SDQ41
DDRB_SDQ40
DDRB_SDQ38
DDRB_SDQ52
+VREF_CA
DDRB_SMA[0..15] <7>
DDRB_SDQ[0..63] <7>
DDRB_SDM[0..7] <7>
DDRB_SCS1#<7>
DDRB_CKE0<7>
DDRB_SCS0# <7>
DDRB_SRAS# <7>
DDRB_SWE#<7>
DDRB_SBS1# <7>
DDRB_SCAS#<7>
DDRB_SBS0#<7>
DDRB_SBS2#<7>
MEM_MB_RST# <7>
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_ODT1 <7>
DDRB_ODT0 <7>
DDRB_CKE1 <7>
DDRB_CLK0#<7> DDRB_CLK0<7>
DDRB_SDQS2<7> DDRB_SDQS2#<7>
DDRB_SDQS4<7> DDRB_SDQS4#<7>
DDRB_SDQS6<7> DDRB_SDQS6#<7>
DDRB_SDQS0# <7>
DDRB_SDQS0 <7>
DDRB_SDQS3# <7>
DDRB_SDQS3 <7>
DDRB_SDQS5 <7>
DDRB_SDQS5# <7>
DDRB_SDQS7 <7>
DDRB_SDQS7# <7>
SB_SMDAT0 <10,22,27,34>
SB_SMCLK0 <10,22,27,34>
DDRB_SDQS1#<7> DDRB_SDQS1<7>
+VREF_DQ
+0.75VS
+1.5V+1.5V
+3VS
+VREF_DQ
+VREF_CA
+1.5V
+1.5V
+0.75VS
+VREF_CA
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
11 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
11 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
11 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
DIMM_B STD H:4mm
<Address: 01>
Place near DIMM2
C353
0.1U_0402_16V4Z
C353
0.1U_0402_16V4Z
1
2
T10PAD T10PAD
C683
1000P_0402_50V7K
C683
1000P_0402_50V7K
1
2
R53
10K_0402_5%
R53
10K_0402_5%
12
C668
0.1U_0402_16V4Z
C668
0.1U_0402_16V4Z
1
2
C674
0.1U_0402_16V4Z
C674
0.1U_0402_16V4Z
1
2
C671
0.1U_0402_16V4Z
C671
0.1U_0402_16V4Z
1
2
C92
4.7U_0805_10V4Z
C92
4.7U_0805_10V4Z
1
2
R52 10K_0402_5% R52 10K_0402_5%
1 2
C93
0.1U_0402_16V4Z
C93
0.1U_0402_16V4Z
1
2
C676
0.1U_0402_16V4Z
C676
0.1U_0402_16V4Z
1
2
C94
1000P_0402_50V7K
C94
1000P_0402_50V7K
1
2
C682
1000P_0402_50V7K
C682
1000P_0402_50V7K
1
2
C670
0.1U_0402_16V4Z
C670
0.1U_0402_16V4Z
1
2
C673
0.1U_0402_16V4Z
C673
0.1U_0402_16V4Z
1
2
C667
0.1U_0402_16V4Z
C667
0.1U_0402_16V4Z
1
2
C352
4.7U_0805_10V4Z
C352
4.7U_0805_10V4Z
1
2
JDIMM2
FOX_AS0A626-U4SN-7F
CONN@
JDIMM2
FOX_AS0A626-U4SN-7F
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
C925
4.7U_0603_6.3V6K
C925
4.7U_0603_6.3V6K
1
2
C675
0.1U_0402_16V4Z
C675
0.1U_0402_16V4Z
1
2
C666
0.1U_0402_16V4Z
C666
0.1U_0402_16V4Z
1
2
C677
0.1U_0402_16V4Z
C677
0.1U_0402_16V4Z
1
2
C669
0.1U_0402_16V4Z
C669
0.1U_0402_16V4Z
1
2
C672
0.1U_0402_16V4Z
C672
0.1U_0402_16V4Z
1
2
+
C86
330U_X_2VM_R6M@
+
C86
330U_X_2VM_R6M@
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
H_CADIN0
H_CADIP1
H_CADIN1
HT_RXCALP
HT_RXCALN
H_CADIN2
H_CADIP2
H_CADIN3
H_CADIP3
HT_TXCALP
HT_TXCALN
H_CTLIN0
H_CTLIP0
H_CTLON0
H_CADIN4
H_CADIP4
H_CADIN5
H_CADIP5
H_CADIN6
H_CADIP6
H_CADIN7
H_CADIP7
H_CADIN8
H_CADIP8
H_CADIN9
H_CADIP9
H_CADIN10
H_CADIP10
H_CTLOP0
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIN13
H_CADIP13
H_CADIN14
H_CADIP14
H_CADIN15
H_CADIP15
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CTLIP1
H_CTLIN1
H_CADON2
H_CTLOP1
H_CADOP2
H_CTLON1
H_CADOP3
H_CADON3
H_CADON4
H_CADOP4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADON10
H_CADOP10
H_CADON9
H_CADOP9
H_CADOP8
H_CADON8
H_CADIP0
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P9 PCIE_MTX_C_GRX_N9
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11
PCIE_MTX_GRX_N10
PCIE_MTX_C_GRX_P13
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12
PCIE_MTX_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_GRX_P14
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0 PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_GRX_N4
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5
PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3 PCIE_ITX_C_PRX_N0 PCIE_ITX_C_PRX_P0PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
GPP0P
GPP0N
H_CADIP[0..15] <6>
H_CADON[0..15]<6> H_CADIN[0..15] <6>
H_CADOP[0..15]<6>
SB_RX1P<26> SB_RX1N<26>
SB_RX0P<26> SB_RX0N<26> SB_TX0P <26>
SB_TX1N <26>
SB_TX0N <26>
SB_TX1P <26>
SB_RX3P<26> SB_RX3N<26>
SB_RX2P<26> SB_RX2N<26> SB_TX2P <26>
SB_TX2N <26>
SB_TX3N <26>
SB_TX3P <26>
H_CLKIN0 <6>
H_CLKIP0 <6>
H_CTLIN0 <6>
H_CTLIP0 <6>
H_CLKON0<6> H_CLKOP0<6>
H_CLKOP1<6> H_CLKON1<6>
H_CTLOP0<6> H_CTLON0<6>
H_CLKIN1 <6>
H_CLKIP1 <6>
H_CTLIN1 <6>
H_CTLIP1 <6>H_CTLOP1<6> H_CTLON1<6>
PCIE_MTX_C_GRX_N[0..15] <15>
PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_GTX_C_MRX_P[0..15]<15>
PCIE_GTX_C_MRX_N[0..15]<15>
PCIE_ITX_C_PRX_P0 <32>
PCIE_ITX_C_PRX_N0 <32>
PCIE_ITX_C_PRX_P1 <34>
PCIE_ITX_C_PRX_N1 <34>
PCIE_PTX_C_IRX_P0<32> PCIE_PTX_C_IRX_N0<32> PCIE_PTX_C_IRX_P1<34> PCIE_PTX_C_IRX_N1<34>
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
12 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
12 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
12 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
GLAN
WLAN
0718 Place within 1"
layout 1:2 0718 Place within 1" layout 1:2
RS880 A11(SA000032710)
RS880 A11(SA000032710)
Reserve for LAN debug
R56,R57 close to R54,R55 C131,C132 close to C127,C128
C116 0.1U_0402_16V7KVGA@C116 0.1U_0402_16V7KVGA@
1 2
C98 0.1U_0402_16V7KVGA@C98 0.1U_0402_16V7KVGA@
1 2
C125 0.1U_0402_16V7KVGA@C125 0.1U_0402_16V7KVGA@
1 2
C117 0.1U_0402_16V7KVGA@C117 0.1U_0402_16V7KVGA@
1 2
C99 0.1U_0402_16V7KVGA@C99 0.1U_0402_16V7KVGA@
1 2
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U3A
RS780M_FCBGA528
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U3A
RS780M_FCBGA528
HT_RXCAD15P
U19 HT_RXCAD15N
U18
HT_RXCAD14P
U20 HT_RXCAD14N
U21
HT_RXCAD13P
V21 HT_RXCAD13N
V20
HT_RXCAD12P
W21 HT_RXCAD12N
W20
HT_RXCAD11P
Y22 HT_RXCAD11N
Y23
HT_RXCAD10P
AA24 HT_RXCAD10N
AA25
HT_RXCAD9P
AB25 HT_RXCAD9N
AB24
HT_RXCAD8P
AC24 HT_RXCAD8N
AC25
HT_RXCAD7P
N24 HT_RXCAD7N
N25
HT_RXCAD6P
P25 HT_RXCAD6N
P24
HT_RXCAD5P
P22 HT_RXCAD5N
P23
HT_RXCAD4P
T25 HT_RXCAD4N
T24
HT_RXCAD3P
U24 HT_RXCAD3N
U25
HT_RXCAD2P
V25 HT_RXCAD2N
V24
HT_RXCAD1P
V22 HT_RXCAD1N
V23
HT_RXCAD0P
Y25 HT_RXCAD0N
Y24
HT_RXCLK1P
AB23 HT_RXCLK1N
AA22
HT_RXCLK0P
T22 HT_RXCLK0N
T23
HT_RXCTL0P
M22 HT_RXCTL0N
M23 HT_RXCTL1P
R21 HT_RXCTL1N
R20
HT_RXCALP
C23 HT_RXCALN
A24
HT_TXCAD15P P18
HT_TXCAD15N M18
HT_TXCAD14P M21
HT_TXCAD14N P21
HT_TXCAD13P M19
HT_TXCAD13N L18
HT_TXCAD12P L19
HT_TXCAD12N J19
HT_TXCAD11P J18
HT_TXCAD11N K17
HT_TXCAD10P J20
HT_TXCAD10N J21
HT_TXCAD9P G20
HT_TXCAD9N H21
HT_TXCAD8P F21
HT_TXCAD8N G21
HT_TXCAD7P K23
HT_TXCAD7N K22
HT_TXCAD6P K24
HT_TXCAD6N K25
HT_TXCAD5P J25
HT_TXCAD5N J24
HT_TXCAD4P H23
HT_TXCAD4N H22
HT_TXCAD3P F23
HT_TXCAD3N F22
HT_TXCAD2P F24
HT_TXCAD2N F25
HT_TXCAD1P E24
HT_TXCAD1N E25
HT_TXCAD0P D24
HT_TXCAD0N D25
HT_TXCLK1P L21
HT_TXCLK1N L20
HT_TXCLK0P H24
HT_TXCLK0N H25
HT_TXCTL0P M24
HT_TXCTL0N M25
HT_TXCTL1P P19
HT_TXCTL1N R18
HT_TXCALP B24
HT_TXCALN B25
C107 0.1U_0402_16V7KVGA@C107 0.1U_0402_16V7KVGA@
1 2
R55 0_0402_5%R55 0_0402_5%
1 2
R58 2K_0402_1%R58 2K_0402_1%
1 2
C95 0.1U_0402_16V7KVGA@C95 0.1U_0402_16V7KVGA@
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
C121 0.1U_0402_16V7KVGA@C121 0.1U_0402_16V7KVGA@
1 2
C123 0.1U_0402_16V7KVGA@C123 0.1U_0402_16V7KVGA@
1 2
C126 0.1U_0402_16V7KVGA@C126 0.1U_0402_16V7KVGA@
1 2
R56 0_0402_5%
@
R56 0_0402_5%
@
1 2
C104 0.1U_0402_16V7KVGA@C104 0.1U_0402_16V7KVGA@
1 2 C103 0.1U_0402_16V7KVGA@C103 0.1U_0402_16V7KVGA@
1 2
C120 0.1U_0402_16V7KVGA@C120 0.1U_0402_16V7KVGA@
1 2
R57 0_0402_5%
@
R57 0_0402_5%
@
1 2
C108 0.1U_0402_16V7KVGA@C108 0.1U_0402_16V7KVGA@
1 2
C112 0.1U_0402_16V7KVGA@C112 0.1U_0402_16V7KVGA@
1 2
C132 0.1U_0402_16V7K@C132 0.1U_0402_16V7K@1 2
C109 0.1U_0402_16V7KVGA@C109 0.1U_0402_16V7KVGA@
1 2
C97 0.1U_0402_16V7KVGA@C97 0.1U_0402_16V7KVGA@
1 2
C127 0.1U_0402_16V7KC127 0.1U_0402_16V7K
1 2
C122 0.1U_0402_16V7KVGA@C122 0.1U_0402_16V7KVGA@
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1%
1 2
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C124 0.1U_0402_16V7KVGA@C124 0.1U_0402_16V7KVGA@
1 2
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C102 0.1U_0402_16V7KVGA@C102 0.1U_0402_16V7KVGA@
1 2
C106 0.1U_0402_16V7KVGA@C106 0.1U_0402_16V7KVGA@
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
C118 0.1U_0402_16V7KVGA@C118 0.1U_0402_16V7KVGA@
1 2
C100 0.1U_0402_16V7KVGA@C100 0.1U_0402_16V7KVGA@
1 2
R54 0_0402_5%R54 0_0402_5%
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C113 0.1U_0402_16V7KVGA@C113 0.1U_0402_16V7KVGA@
1 2
C105 0.1U_0402_16V7KVGA@C105 0.1U_0402_16V7KVGA@
1 2
R61
301_0402_1%~D
R61
301_0402_1%~D
1 2
C111 0.1U_0402_16V7KVGA@C111 0.1U_0402_16V7KVGA@
1 2
C119 0.1U_0402_16V7KVGA@C119 0.1U_0402_16V7KVGA@
1 2
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528
SB_TX3P AD5
SB_TX3N AE5
GPP_TX2P AA2
GPP_TX2N AA1
GPP_TX3P Y1
GPP_TX3N Y2
SB_RX3P
W5 SB_RX3N
Y5
GPP_RX2P
AD1 GPP_RX2N
AD2 GPP_RX3P
V5 GPP_RX3N
W6
SB_TX0P AD7
SB_TX0N AE7
SB_TX1P AE6
SB_TX1N AD6
SB_RX0P
AA8 SB_RX0N
Y8 SB_RX1P
AA7 SB_RX1N
Y7
PCE_CALRP(PCE_BCALRP) AC8
PCE_CALRN(PCE_BCALRN) AB8
SB_TX2N AC6
SB_RX2P
AA5 SB_RX2N
AA6 SB_TX2P AB6
GPP_RX0P
AE3 GPP_RX0N
AD4 GPP_RX1P
AE2 GPP_RX1N
AD3
GPP_TX0P AC1
GPP_TX0N AC2
GPP_TX1P AB4
GPP_TX1N AB3
GFX_RX0P
D4 GFX_RX0N
C4 GFX_RX1P
A3 GFX_RX1N
B3 GFX_RX2P
C2 GFX_RX2N
C1 GFX_RX3P
E5 GFX_RX3N
F5 GFX_RX4P
G5 GFX_RX4N
G6 GFX_RX5P
H5 GFX_RX5N
H6 GFX_RX6P
J6 GFX_RX6N
J5 GFX_RX7P
J7 GFX_RX7N
J8 GFX_RX8P
L5 GFX_RX8N
L6 GFX_RX9P
M8 GFX_RX9N
L8 GFX_RX10P
P7 GFX_RX10N
M7 GFX_RX11P
P5 GFX_RX11N
M5 GFX_RX12P
R8 GFX_RX12N
P8 GFX_RX13P
R6 GFX_RX13N
R5 GFX_RX14P
P4 GFX_RX14N
P3 GFX_RX15P
T4 GFX_RX15N
T3
GFX_TX0P A5
GFX_TX0N B5
GFX_TX1P A4
GFX_TX1N B4
GFX_TX2P C3
GFX_TX2N B2
GFX_TX3P D1
GFX_TX3N D2
GFX_TX4P E2
GFX_TX4N E1
GFX_TX5P F4
GFX_TX5N F3
GFX_TX6P F1
GFX_TX6N F2
GFX_TX7P H4
GFX_TX7N H3
GFX_TX8P H1
GFX_TX8N H2
GFX_TX9P J2
GFX_TX9N J1
GFX_TX10P K4
GFX_TX10N K3
GFX_TX11P K1
GFX_TX11N K2
GFX_TX12P M4
GFX_TX12N M3
GFX_TX13P M1
GFX_TX13N M2
GFX_TX14P N2
GFX_TX14N N1
GFX_TX15P P1
GFX_TX15N P2
GPP_TX4P Y4
GPP_TX4N Y3
GPP_TX5P V1
GPP_TX5N V2
GPP_RX4P
U5 GPP_RX4N
U6 GPP_RX5P
U8 GPP_RX5N
U7
C110 0.1U_0402_16V7KVGA@C110 0.1U_0402_16V7KVGA@
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
R60
301_0402_1%~D
R60
301_0402_1%~D
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C128 0.1U_0402_16V7KC128 0.1U_0402_16V7K
1 2
C96 0.1U_0402_16V7KVGA@C96 0.1U_0402_16V7KVGA@
1 2
C101 0.1U_0402_16V7KVGA@C101 0.1U_0402_16V7KVGA@
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C131 0.1U_0402_16V7K@C131 0.1U_0402_16V7K@
1 2
C115 0.1U_0402_16V7KVGA@C115 0.1U_0402_16V7KVGA@
1 2
C114 0.1U_0402_16V7KVGA@C114 0.1U_0402_16V7KVGA@
1 2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NB_RESET#
NB_REFCLK_N
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
+VDDLTP18
+VDDLT18
+VDDLT18
+AVDDDI
+NB_HTPVDD
DAC_RSET
+NB_PLLVDD
GMCH_LCD_CLK
GMCH_LCD_CLK
GMCH_LCD_DATA GMCH_LCD_DATA
POWER_SEL
+VDDLTP18
+AVDDQ
NB_PWRGD_R
+AVDD1
NB_PWRGD_R
VARY_ENBKL GMCH_ENBKL
CLK_NB_14.318M
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_R
GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA
NB_PWRGD
GMCH_ENBKL
VGA_ENBKL
AUX0N
NB_LDTSTOP#
CLK_NBGFX
CLK_NBGFX#
NB_REFCLK_P
NB_PWRGD<27>
CLK_NBGFX<22> CLK_NBGFX#<22>
CLK_SBLINK_BCLK<22> CLK_SBLINK_BCLK#<22>
CLK_NBHT<22> CLK_NBHT#<22>
A_RST#<14,26,36>
SUS_STAT# <27>
SUS_STAT_R# <14>
ALLOW_LDTSTOP<26>
POWER_SEL<48>
SB_PWRGD<8,27,36>
GMCH_LCD_DATA<23,38> GMCH_LCD_CLK<23>
GMCH_ENVDD <23>
GMCH_INVT_PWM <23>
GMCH_CRT_R<25>
GMCH_CRT_G<25>
GMCH_CRT_B<25>
GMCH_CRT_HSYNC<14,25> GMCH_CRT_VSYNC<14,25>
GMCH_TXOUT0+ <23>
GMCH_TXOUT0- <23>
GMCH_TXOUT1+ <23>
GMCH_TXOUT1- <23>
GMCH_TXOUT2+ <23>
GMCH_TXOUT2- <23>
GMCH_TXCLK+ <23>
GMCH_TXCLK- <23>
GMCH_CRT_DATA<25> GMCH_CRT_CLK<25>
AUX0N<38>
VGA_ENBKL<16>
ENBKL <36>
LDT_STOP#<8,26>
NB_DISP_CLKP<26> NB_DISP_CLKN<26>
CLK_NB_14.318M<22>
+1.8VS
+1.8VS
+VDDA18HTPLL
+VDDA18PCIEPLL
+1.1VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+1.8VS
+1.8VS
+NB_PLLVDD
+NB_HTPVDD
+VDDA18PCIEPLL
+VDDA18HTPLL
+NB_HTPVDD+1.8VS
+1.1VS
+3VS
+NB_PLLVDD
+1.8VS
+3VS
+3VS
+1.8VS+1.8VS +1.8VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
13 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Strap pin
POWER_SEL
HIGH 0.95V
1.1VLOW
RS880
To SB
EMI
125mA
20mA
4mA
65mA
20mA
20mA
120mA
15mA
300mA
RS880 A11(SA000032710)
If support VB, pop VB@ and reserve R71
PD on chip side
Wire-OR
AMD suggest Check if needed?
R80 4.7K_0402_5%R80 4.7K_0402_5%
1 2
C150
2.2U_0603_6.3V4Z
C150
2.2U_0603_6.3V4Z
1
2
C684
0.1U_0402_16V4Z
C684
0.1U_0402_16V4Z
1 2
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
VDDA18HTPLL
H17
SYSRESETb
D8 POWERGOOD
A10 LDTSTOPb
C10 ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC) D10
DDC_CLK0/AUX0P(NC)
A8 DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P AE8
THERMALDIODE_N AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2 GFX_REFCLKN
T1
GPP_REFCLKP
U1 GPP_REFCLKN
U2
PLLVDD18(NC)
D14 PLLVSS(NC)
B12
TXOUT_L0P(NC) A22
TXOUT_L0N(NC) B22
TXOUT_L1P(NC) A21
TXOUT_L1N(NC) B21
TXOUT_L2P(NC) B20
TXOUT_L2N(DBG_GPIO0) A20
TXOUT_L3P(NC) A19
TXOUT_U0P(NC) B18
TXOUT_L3N(DBG_GPIO2) B19
TXOUT_U0N(NC) A18
TXOUT_U1P(PCIE_RESET_GPIO3) A17
TXOUT_U1N(PCIE_RESET_GPIO2) B17
TXOUT_U2P(NC) D20
TXOUT_U2N(NC) D21
TXOUT_U3P(PCIE_RESET_GPIO5) D18
TXOUT_U3N(NC) D19
TXCLK_LP(DBG_GPIO1) B16
TXCLK_LN(DBG_GPIO3) A16
TXCLK_UP(PCIE_RESET_GPIO4) D16
TXCLK_UN(PCIE_RESET_GPIO1) D17
VDDLTP18(NC) A13
VSSLTP18(NC) B13
C_Pr(DFT_GPIO5)
E17 Y(DFT_GPIO2)
F17 COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC) D9 I2C_DATA
A9
TESTMODE D13
HT_REFCLKN
C24 HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5) D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11 DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12 AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14 AVSSDI(NC)
G15 AVDDQ(NC)
H15 AVSSQ(NC)
H14
VDDLT18_2(NC) B15
VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
VSSLT1(VSS) C14
VSSLT2(VSS) D15
VDDLT18_1(NC) A15
VSSLT3(VSS) C16
VSSLT4(VSS) C18
VSSLT5(VSS) C20
LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
LVDS_ENA_BL(PWM_GPIO2) G12
VSSLT6(VSS) E20
VDDA18PCIEPLL1
D7 VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4 GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7 DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8 DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS) C22
RSVD
G11
R64 0_0402_5%@R64 0_0402_5%@
1 2
L4
FBMA-L11-160808-221LMT 0603
L4
FBMA-L11-160808-221LMT 0603
1 2
L5
FBMA-L11-160808-221LMT 0603
L5
FBMA-L11-160808-221LMT 0603
1 2
C144
2.2U_0603_6.3V4Z
C144
2.2U_0603_6.3V4Z
1
2
C142
1U_0402_6.3V4Z
C142
1U_0402_6.3V4Z
1
2
R71 0_0402_5%@R71 0_0402_5%@
1 2
C147
1U_0402_6.3V4Z
C147
1U_0402_6.3V4Z
1
2
R69
4.7K_0402_5%
EXT@
R69
4.7K_0402_5%
EXT@
1 2
U4
NC7SZ08P5X_NL_SC70-5
@
U4
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1Y4
P5
G
3
L2
FBMA-L11-160808-221LMT 0603
L2
FBMA-L11-160808-221LMT 0603
1 2
L6
FBMA-L11-160808-221LMT 0603
L6
FBMA-L11-160808-221LMT 0603
1 2
R456 0_0402_5%
INT@
R456 0_0402_5%
INT@
1 2
L7
FBMA-L11-160808-221LMT 0603
L7
FBMA-L11-160808-221LMT 0603
1 2
R90
1K_0402_5%
R90
1K_0402_5%
12
R85 150_0402_1%R85 150_0402_1%
1 2
G
D
S
Q62
2N7002_SOT23
VGA@
G
D
S
Q62
2N7002_SOT23
VGA@
2
13
L3
FBMA-L11-160808-221LMT 0603
L3
FBMA-L11-160808-221LMT 0603
1 2 U8
NC7SZ08P5X_NL_SC70-5
U8
NC7SZ08P5X_NL_SC70-5
B
2
A
1Y4
P5
G
3
L9
FBMA-L11-160808-221LMT 0603
L9
FBMA-L11-160808-221LMT 0603
1 2
C143
1U_0402_6.3V4Z
C143
1U_0402_6.3V4Z
1
2
C145
0.1U_0402_16V4Z
C145
0.1U_0402_16V4Z
1
2
R149
4.7K_0402_5%
R149
4.7K_0402_5%
12
R506 4.7K_0402_5%
INT@
R506 4.7K_0402_5%
INT@ 12
C157
4.7U_0805_10V4Z
C157
4.7U_0805_10V4Z
1
2
R79 4.7K_0402_5%R79 4.7K_0402_5%
1 2
R536 0_0402_5%
EXT@
R536 0_0402_5%
EXT@
1 2
R439 0_0402_5%
INT@
R439 0_0402_5%
INT@
1 2
R67 0_0402_5%R67 0_0402_5%
1 2
C158
100P_0402_25V8K
@C158
100P_0402_25V8K
@
1 2
R73
4.7K_0402_5%
R73
4.7K_0402_5%
12
C151
1U_0402_6.3V4Z
C151
1U_0402_6.3V4Z
1
2
L10
BLM18AG601SN1D_2P
L10
BLM18AG601SN1D_2P
1 2
G
D
S
Q63
2N7002_SOT23
G
D
S
Q63
2N7002_SOT23
2
13
C146
2.2U_0603_6.3V4Z
C146
2.2U_0603_6.3V4Z
1
2
R89 150_0402_1%R89 150_0402_1%
1 2
R66 0_0402_5%R66 0_0402_5%
1 2
R75
4.7K_0402_5%
R75
4.7K_0402_5%
12
C149
1U_0402_6.3V4Z
C149
1U_0402_6.3V4Z
1
2
C154
2.2U_0603_6.3V4Z
C154
2.2U_0603_6.3V4Z
1
2
R72 0_0402_5%VB@R72 0_0402_5%VB@
1 2
R82 2K_0402_5%R82 2K_0402_5%
1 2
R86
100_0402_5%
@ R86
100_0402_5%
@
1 2
L8
FBMA-L11-160808-221LMT 0603
L8
FBMA-L11-160808-221LMT 0603
1 2
C148
2.2U_0603_6.3V4Z
C148
2.2U_0603_6.3V4Z
1
2
R78 4.7K_0402_5%R78 4.7K_0402_5%
1 2
R81 0_0402_5%R81 0_0402_5%
1 2
C155
1U_0402_6.3V4Z
C155
1U_0402_6.3V4Z
1
2
C152
1U_0402_6.3V4Z
C152
1U_0402_6.3V4Z
1
2
R63
2.2K_0402_5%
R63
2.2K_0402_5%
1 2
R70
4.7K_0402_5%
EXT@
R70
4.7K_0402_5%
EXT@
1 2
R84
1.8K_0402_5%
R84
1.8K_0402_5%
1 2
R504 4.7K_0402_5%
INT@
R504 4.7K_0402_5%
INT@ 12
G
D
S
Q41
2N7002_SOT23
UMA@
G
D
S
Q41
2N7002_SOT23
UMA@
2
13
R65 715_0402_1%R65 715_0402_1%
1 2
R88 150_0402_1%R88 150_0402_1%
1 2
R68 300_0402_5%R68 300_0402_5%
12
R417
300_0402_5%
@
R417
300_0402_5%
@
1 2
R77 4.7K_0402_5%R77 4.7K_0402_5%
1 2
C141
2.2U_0603_6.3V4Z
C141
2.2U_0603_6.3V4Z
1
2
R173 4.7K_0402_5%@R173 4.7K_0402_5%@ 12
R74
4.7K_0402_5%
R74
4.7K_0402_5%
12
R76 0_0402_5%VB@R76 0_0402_5%VB@
1 2
C156
0.1U_0402_16V4Z
C156
0.1U_0402_16V4Z
1
2
C679
22U_0805_6.3V6M
C679
22U_0805_6.3V6M
1
2
R91 0_0402_5%R91 0_0402_5%
1 2
R106 4.7K_0402_5%R106 4.7K_0402_5%
12
R87 140_0402_1%R87 140_0402_1%
1 2
C153
2.2U_0603_6.3V4Z
C153
2.2U_0603_6.3V4Z
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTTX
+VDDHT
+VDDA18PCIE
+VDDHTRX
GMCH_CRT_VSYNC<13,25>
A_RST# <13,26,36>
GMCH_CRT_HSYNC<13,25>
SUS_STAT_R#<13>
+1.1VS
+1.8VS
+1.8VS
+1.1VS
+1.1VS
+3VS
+1.1VS
+1.8VS
+NB_CORE
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
14 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
14 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
14 55Tuesday, September 14, 2010
2008/10/06 2010/03/12
Compal Electronics, Inc.
1.3A
10mA
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable
0 : Enable
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
DFT_GPIO1: LOAD_EEPROM_STRAPS
Load EEPROM Strap
RS880: HSYNC#
0: Enable
1 : Disable
Enable Side Port Memory
Side port and Strap setting
Enable Side Port Memory
Register Readback of strap:
NB_CLKCFG:CLK_TOP_SPARE_D[1]
Debug Mode
600mA
700mA
680mA
700mA
60mA
10A
2.5A
5mA
23mA
15mA
26mA
RS880 A11(SA000032710)
RS880 A11(SA000032710)
RS880 A11(SA000032710)
L14
FBMA-L11-201209-221LMA30T_0805
L14
FBMA-L11-201209-221LMA30T_0805
12
C1910.1U_0402_16V4Z C1910.1U_0402_16V4Z
1
2
D1
CH751H-40PT_SOD323-2
@D1
CH751H-40PT_SOD323-2
@
2 1
R264 3K_0402_5%@R264 3K_0402_5%@ 12
C261
10U_0603_6.3V6M
@
C261
10U_0603_6.3V6M
@
1
2
C175
0.1U_0402_16V4Z
C175
0.1U_0402_16V4Z
1
2
C167
1U_0402_6.3V4Z
C167
1U_0402_6.3V4Z
1
2
C199 0.1U_0402_16V4Z C199 0.1U_0402_16V4Z
1
2
C192
0.1U_0402_16V4Z
C192
0.1U_0402_16V4Z
1
2
C181
4.7U_0805_10V4Z
C181
4.7U_0805_10V4Z
1
2
R93 3K_0402_5%@R93 3K_0402_5%@ 12
C163 4.7U_0805_10V4ZC163 4.7U_0805_10V4Z
1 2
C1950.1U_0402_16V4Z C1950.1U_0402_16V4Z
1
2
L15
FBMA-L11-201209-221LMA30T_0805
L15
FBMA-L11-201209-221LMA30T_0805
12
C18410U_0805_10V4Z C18410U_0805_10V4Z
1
2
C165
4.7U_0805_10V4Z
C165
4.7U_0805_10V4Z
1
2
C172 0.1U_0402_16V4ZC172 0.1U_0402_16V4Z
1 2
C160 10U_0805_10V4ZC160 10U_0805_10V4Z
1 2
C198
0.1U_0402_16V4Z
C198
0.1U_0402_16V4Z
1
2
C171 1U_0402_6.3V4ZC171 1U_0402_6.3V4Z
1 2
C19610U_0805_10V4Z C19610U_0805_10V4Z
1
2
L12
FBMA-L11-201209-221LMA30T_0805
L12
FBMA-L11-201209-221LMA30T_0805
1 2
C1820.1U_0402_16V4Z C1820.1U_0402_16V4Z
1
2
R94 3K_0402_5%R94 3K_0402_5%
12
C166
0.1U_0402_16V4Z
C166
0.1U_0402_16V4Z
1
2
L28
FBMA-L11-201209-221LMA30T_0805
L28
FBMA-L11-201209-221LMA30T_0805
1 2
L13
FBMA-L11-201209-221LMA30T_0805
L13
FBMA-L11-201209-221LMA30T_0805
12
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528
MEM_A0(NC)
AB12 MEM_A1(NC)
AE16 MEM_A2(NC)
V11 MEM_A3(NC)
AE15 MEM_A4(NC)
AA12 MEM_A5(NC)
AB16 MEM_A6(NC)
AB14 MEM_A7(NC)
AD14 MEM_A8(NC)
AD13 MEM_A9(NC)
AD15 MEM_A10(NC)
AC16 MEM_A11(NC)
AE13 MEM_A12(NC)
AC14 MEM_A13(NC)
Y14
MEM_BA0(NC)
AD16 MEM_BA1(NC)
AE17 MEM_BA2(NC)
AD17
MEM_RASb(NC)
W12 MEM_CASb(NC)
Y12 MEM_WEb(NC)
AD18 MEM_CSb(NC)
AB13 MEM_CKE(NC)
AB18 MEM_ODT(NC)
V14
MEM_CKP(NC)
V15 MEM_CKN(NC)
W14
MEM_DM0(NC) W17
MEM_DM1/DVO_D8(NC) AE19
MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
MEM_DQS1P(NC) AD20
MEM_DQS1N(NC) AE21
MEM_DQ0/DVO_VSYNC(NC) AA18
MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_DQ2/DVO_DE(NC) AA19
MEM_DQ3/DVO_D0(NC) Y19
MEM_DQ4(NC) V17
MEM_DQ5/DVO_D1(NC) AA17
MEM_DQ6/DVO_D2(NC) AA15
MEM_DQ7/DVO_D4(NC) Y15
MEM_DQ8/DVO_D3(NC) AC20
MEM_DQ9/DVO_D5(NC) AD19
MEM_DQ10/DVO_D6(NC) AE22
MEM_DQ11/DVO_D7(NC) AC18
MEM_DQ12(NC) AB20
MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
MEM_DQ15/DVO_D11(NC) AD21
MEM_COMPP(NC)
AE12 MEM_COMPN(NC)
AD12 MEM_VREF(NC) AE18
IOPLLVDD18(NC) AE23
IOPLLVSS(NC) AD23
IOPLLVDD(NC) AE24
C174
4.7U_0805_10V4Z
C174
4.7U_0805_10V4Z
1
2
C177
0.1U_0402_16V4Z
C177
0.1U_0402_16V4Z
1
2
C179
4.7U_0805_10V4Z
C179
4.7U_0805_10V4Z
1
2
C162 10U_0805_10V4ZC162 10U_0805_10V4Z
1 2
C170
0.1U_0402_16V4Z
C170
0.1U_0402_16V4Z
1
2C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z
1 2
C1870.1U_0402_16V4Z C1870.1U_0402_16V4Z
1
2
C178
1U_0402_6.3V4Z
C178
1U_0402_6.3V4Z
1
2
C159
0.1U_0402_16V4Z
C159
0.1U_0402_16V4Z
1
2
L11
FBMA-L11-201209-221LMA30T_0805
L11
FBMA-L11-201209-221LMA30T_0805
12
C1800.1U_0402_16V4Z C1800.1U_0402_16V4Z
1
2
C1830.1U_0402_16V4Z C1830.1U_0402_16V4Z
1
2
+
C189 330U_D2E_2.5VM
+
C189 330U_D2E_2.5VM
1
2
C1930.1U_0402_16V4Z C1930.1U_0402_16V4Z
1
2
C161
1U_0402_6.3V4Z
C161
1U_0402_6.3V4Z
1
2
C186
0.1U_0402_16V4Z
C186
0.1U_0402_16V4Z
1
2
C176
0.1U_0402_16V4Z
C176
0.1U_0402_16V4Z
1
2
C169
0.1U_0402_16V4Z
C169
0.1U_0402_16V4Z
1
2
PART 5/6
POWER
U3E
RS780M_FCBGA528
PART 5/6
POWER
U3E
RS780M_FCBGA528
VDDHT_1
J17 VDDHT_2
K16 VDDHT_3
L16 VDDHT_4
M16 VDDHT_5
P16 VDDHT_6
R16 VDDHT_7
T16
VDDHTTX_1
AE25 VDDHTTX_2
AD24 VDDHTTX_3
AC23 VDDHTTX_4
AB22 VDDHTTX_5
AA21 VDDHTTX_6
Y20 VDDHTTX_7
W19 VDDHTTX_8
V18
VDDHTRX_1
H18 VDDHTRX_2
G19 VDDHTRX_3
F20 VDDHTRX_4
E21 VDDHTRX_5
D22
VDD18_1
F9 VDD18_2
G9 VDD18_MEM1(NC)
AE11 VDD18_MEM2(NC)
AD11
VDDA18PCIE_1
J10 VDDA18PCIE_2
P10 VDDA18PCIE_3
K10
VDDA18PCIE_10
Y9 VDDA18PCIE_11
AA9 VDDA18PCIE_12
AB9 VDDA18PCIE_13
AD9 VDDA18PCIE_14
AE9
VDDA18PCIE_6
W9 VDDA18PCIE_7
H9
VDDPCIE_1 A6
VDDPCIE_2 B6
VDDPCIE_3 C6
VDDPCIE_4 D6
VDDPCIE_5 E6
VDDPCIE_6 F6
VDDPCIE_7 G7
VDDPCIE_8 H8
VDDPCIE_9 J9
VDDA18PCIE_4
M10 VDDA18PCIE_5
L10
VDDC_1 K12
VDDC_2 J14
VDDC_3 U16
VDDPCIE_11 M9
VDDC_4 J11
VDDC_5 K15
VDDPCIE_10 K9
VDDC_6 M12
VDDC_7 L14
VDDC_8 L11
VDDC_9 M13
VDDC_10 M15
VDDC_11 N12
VDDC_12 N14
VDDC_13 P11
VDDC_14 P13
VDDC_15 P14
VDDC_16 R12
VDDC_17 R15
VDDC_18 T11
VDDC_19 T15
VDDC_20 U12
VDDC_21 T14
VDD33_1(NC) H11
VDD33_2(NC) H12
VDD_MEM1(NC) AE10
VDD_MEM2(NC) AA11
VDD_MEM3(NC) Y11
VDD_MEM4(NC) AD10
VDD_MEM6(NC) AC10
VDD_MEM5(NC) AB10
VDDA18PCIE_8
T10
VDDC_22 J16
VDDPCIE_12 L9
VDDA18PCIE_9
R10
VDDPCIE_13 P9
VDDPCIE_14 R9
VDDPCIE_15 T9
VDDPCIE_16 V9
VDDPCIE_17 U9
VDDA18PCIE_15
U10
VDDHTRX_6
B23 VDDHTRX_7
A23
VDDHTTX_9
U17 VDDHTTX_10
T17 VDDHTTX_11
R17 VDDHTTX_12
P17 VDDHTTX_13
M17
C197
1U_0402_6.3V4Z
C197
1U_0402_6.3V4Z
1
2
C1880.1U_0402_16V4Z C1880.1U_0402_16V4Z
1
2
C1940.1U_0402_16V4Z C1940.1U_0402_16V4Z
1
2
C185
0.1U_0402_16V4Z
C185
0.1U_0402_16V4Z
1
2
C190
0.1U_0402_16V4Z
C190
0.1U_0402_16V4Z
1
2
R95 3K_0402_5%
@
R95 3K_0402_5%
@12
PART 6/6
GROUND
U3F
RS780M_FCBGA528
PART 6/6
GROUND
U3F
RS780M_FCBGA528
VSSAHT1
A25 VSSAHT2
D23 VSSAHT3
E22 VSSAHT4
G22 VSSAHT5
G24 VSSAHT6
G25 VSSAHT7
H19 VSSAHT8
J22 VSSAHT9
L17 VSSAHT10
L22 VSSAHT11
L24 VSSAHT12
L25 VSSAHT13
M20 VSSAHT14
N22 VSSAHT15
P20 VSSAHT16
R19 VSSAHT17
R22 VSSAHT18
R24 VSSAHT19
R25
VSSAHT21
U22 VSSAHT22
V19 VSSAHT23
W22 VSSAHT24
W24 VSSAHT25
W25 VSSAHT26
Y21 VSSAHT27
AD25
VSS2 D11
VSS3 G8
VSS4 E14
VSS5 E15
VSS7 J12
VSS8 K14
VSS9 M11
VSS10 L15
VSS11
L12 VSS12
M14 VSS13
N13 VSS14
P12 VSS15
P15 VSS16
R11 VSS17
R14 VSS18
T12 VSS19
U14 VSS20
U11 VSS21
U15 VSS22
V12 VSS23
W11 VSS24
W15 VSS25
AC12 VSS26
AA14 VSS27
Y18 VSS28
AB11 VSS29
AB15 VSS30
AB17 VSS31
AB19 VSS32
AE20
VSSAPCIE1 A2
VSSAPCIE2 B1
VSSAPCIE3 D3
VSSAPCIE4 D5
VSSAPCIE5 E4
VSSAPCIE6 G1
VSSAPCIE7 G2
VSSAPCIE8 G4
VSSAPCIE9 H7
VSSAPCIE10 J4
VSSAPCIE11 R7
VSSAPCIE12 L1
VSSAPCIE13 L2
VSSAPCIE14 L4
VSSAPCIE15 L7
VSS34
K11
VSSAPCIE16 M6
VSSAPCIE17 N4
VSSAPCIE18 P6
VSSAPCIE19 R1
VSSAPCIE20 R2
VSSAPCIE21 R4
VSSAPCIE22 V7
VSSAPCIE23 U4
VSSAPCIE24 V8
VSSAPCIE25 V6
VSSAPCIE26 W1
VSSAPCIE27 W2
VSSAPCIE28 W4
VSSAPCIE29 W7
VSSAPCIE30 W8
VSSAPCIE31 Y6
VSSAPCIE32 AA4
VSSAPCIE33 AB5
VSSAPCIE34 AB1
VSSAPCIE35 AB7
VSSAPCIE36 AC3
VSSAPCIE37 AC4
VSSAPCIE38 AE1
VSSAPCIE39 AE4
VSSAPCIE40 AB2
VSS1 AE14
VSSAHT20
H20
VSS33
AB21
VSS6 J15
C164
4.7U_0805_10V4Z
C164
4.7U_0805_10V4Z
1
2
C168 1U_0402_6.3V4ZC168 1U_0402_6.3V4Z
1 2
R92 3K_0402_5%R92 3K_0402_5%
12

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA_RST#
VGA_TXOUT0-
VGA_TXOUT0+
VGA_TXOUT1+
VGA_TXOUT1-
VGA_TXCLK-
VGA_TXCLK+
VGA_TXOUT2+
VGA_TXOUT2-
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_N7 PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7PCIE_GTX_MRX_P7
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P1
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N5 PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10 PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N15 PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
VGA_RST#
CLK_PEG_VGA<22> CLK_PEG_VGA#<22>
VGA_ENVDD <23>
VGA_PNL_PWM <23>
VGA_TXCLK+ <23>
VGA_TXCLK- <23>
VGA_TXOUT0- <23>
VGA_TXOUT0+ <23>
VGA_TXOUT1- <23>
VGA_TXOUT1+ <23>
VGA_TXOUT2+ <23>
VGA_TXOUT2- <23>
PCIE_MTX_C_GRX_N[0..15] <12>
PCIE_MTX_C_GRX_P[0..15] <12>
PCIE_GTX_C_MRX_P[0..15]<12>
PCIE_GTX_C_MRX_N[0..15]<12>
PLT_RST#<26,32,34>
PE_GPIO0<26>
+1.0VSG
+3VSG
+3VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
15 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
15 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
15 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
MAD A12 (SA00003M300)
add for VB support.
For M96, AH16 is NC
For Mahatten need PD
GFX PCIE LANE REVERSAL
Pop for PX verify
PARK A11 (SA00003MC10)
PCI EXPRESS INTERFACE
CLOCK
CALIBRATION
216-0729002 A12 M96_BGA962
U5A
MAD@
PCI EXPRESS INTERFACE
CLOCK
CALIBRATION
216-0729002 A12 M96_BGA962
U5A
MAD@
NC#1
AJ21 NC#2
AK21 NC_PWRGOOD
AH16 PCIE_CALRN Y29
PCIE_CALRP Y30
PCIE_REFCLKN
AA36 PCIE_REFCLKP
AB35
PCIE_RX0N
Y37 PCIE_RX0P
AA38
PCIE_RX10N
K37 PCIE_RX10P
L38
PCIE_RX11N
J36 PCIE_RX11P
K35
PCIE_RX12N
H37 PCIE_RX12P
J38
PCIE_RX13N
G36 PCIE_RX13P
H35
PCIE_RX14N
F37 PCIE_RX14P
G38
PCIE_RX15N
E37 PCIE_RX15P
F35
PCIE_RX1N
W36 PCIE_RX1P
Y35
PCIE_RX2N
V37 PCIE_RX2P
W38
PCIE_RX3N
U36 PCIE_RX3P
V35
PCIE_RX4N
T37 PCIE_RX4P
U38
PCIE_RX5N
R36 PCIE_RX5P
T35
PCIE_RX6N
P37 PCIE_RX6P
R38
PCIE_RX7N
N36 PCIE_RX7P
P35
PCIE_RX8N
M37 PCIE_RX8P
N38
PCIE_RX9N
L36 PCIE_RX9P
M35
PERSTB
AA30
PCIE_TX0N Y32
PCIE_TX0P Y33
PCIE_TX10N L32
PCIE_TX10P L33
PCIE_TX11N L29
PCIE_TX11P L30
PCIE_TX12N K32
PCIE_TX12P K33
PCIE_TX13N J32
PCIE_TX13P J33
PCIE_TX14N K29
PCIE_TX14P K30
PCIE_TX15N H32
PCIE_TX15P H33
PCIE_TX1N W32
PCIE_TX1P W33
PCIE_TX2N U32
PCIE_TX2P U33
PCIE_TX3N U29
PCIE_TX3P U30
PCIE_TX4N T32
PCIE_TX4P T33
PCIE_TX5N T29
PCIE_TX5P T30
PCIE_TX6N P32
PCIE_TX6P P33
PCIE_TX7N P29
PCIE_TX7P P30
PCIE_TX8N N32
PCIE_TX8P N33
PCIE_TX9N N29
PCIE_TX9P N30
C202 0.1U_0402_16V7K
VGA@
C202 0.1U_0402_16V7K
VGA@
1 2
C205 0.1U_0402_16V7K
VGA@
C205 0.1U_0402_16V7K
VGA@
1 2
LVTMDP
LVDS CONTROL
216-0729002 A12 M96_BGA962
U5G
MAD@
LVTMDP
LVDS CONTROL
216-0729002 A12 M96_BGA962
U5G
MAD@
DIGON AJ27
TXCLK_LN_DPE3N AR34
TXCLK_LP_DPE3P AP34
TXCLK_UN_DPF3N AL36
TXCLK_UP_DPF3P AK35
TXOUT_L0N_DPE2N AU35
TXOUT_L0P_DPE2P AW37
TXOUT_L1N_DPE1N AU39
TXOUT_L1P_DPE1P AR37
TXOUT_L2N_DPE0N AR35
TXOUT_L2P_DPE0P AP35
TXOUT_L3N AP37
TXOUT_L3P AN36
TXOUT_U0N_DPF2N AK37
TXOUT_U0P_DPF2P AJ38
TXOUT_U1N_DPF1N AJ36
TXOUT_U1P_DPF1P AH35
TXOUT_U2N_DPF0N AH37
TXOUT_U2P_DPF0P AG38
TXOUT_U3N AG36
TXOUT_U3P AF35
VARY_BL AK27
R96
10K_0402_5%
R96
10K_0402_5%
1 2
C219 0.1U_0402_16V7K
VGA@
C219 0.1U_0402_16V7K
VGA@
1 2
R98 1.27K_0402_1%VGA@R98 1.27K_0402_1%VGA@
1 2
C201 0.1U_0402_16V7K
VGA@
C201 0.1U_0402_16V7K
VGA@
1 2
R100 2K_0402_1%VGA@R100 2K_0402_1%VGA@
1 2
C208 0.1U_0402_16V7K
VGA@
C208 0.1U_0402_16V7K
VGA@
1 2
C230 0.1U_0402_16V7K
VGA@
C230 0.1U_0402_16V7K
VGA@
1 2
R97
10K_0402_5%
R97
10K_0402_5%
1 2
C204 0.1U_0402_16V7K
VGA@
C204 0.1U_0402_16V7K
VGA@
1 2
C218 0.1U_0402_16V7K
VGA@
C218 0.1U_0402_16V7K
VGA@
1 2
C226 0.1U_0402_16V7K
VGA@
C226 0.1U_0402_16V7K
VGA@
1 2
U5
PARK XT-M2 A11
PARK@U5
PARK XT-M2 A11
PARK@C222 0.1U_0402_16V7K
VGA@
C222 0.1U_0402_16V7K
VGA@
1 2
C210 0.1U_0402_16V7K
VGA@
C210 0.1U_0402_16V7K
VGA@
1 2
C217 0.1U_0402_16V7K
VGA@
C217 0.1U_0402_16V7K
VGA@
1 2
C209 0.1U_0402_16V7K
VGA@
C209 0.1U_0402_16V7K
VGA@
1 2
D45 RB751V_SOD323
VGA@
D45 RB751V_SOD323
VGA@ 21
C200 0.1U_0402_16V7K
VGA@
C200 0.1U_0402_16V7K
VGA@
1 2
C223 0.1U_0402_16V7K
VGA@
C223 0.1U_0402_16V7K
VGA@
1 2
C220 0.1U_0402_16V7K
VGA@
C220 0.1U_0402_16V7K
VGA@
1 2
C231 0.1U_0402_16V7K
VGA@
C231 0.1U_0402_16V7K
VGA@
1 2
C206 0.1U_0402_16V7K
VGA@
C206 0.1U_0402_16V7K
VGA@
1 2
C215 0.1U_0402_16V7K
VGA@
C215 0.1U_0402_16V7K
VGA@
1 2
R491
10K_0402_5%
VGA@
R491
10K_0402_5%
VGA@
12
C224 0.1U_0402_16V7K
VGA@
C224 0.1U_0402_16V7K
VGA@
1 2
C216 0.1U_0402_16V7K
VGA@
C216 0.1U_0402_16V7K
VGA@
1 2
C225 0.1U_0402_16V7K
VGA@
C225 0.1U_0402_16V7K
VGA@
1 2
C221 0.1U_0402_16V7K
VGA@
C221 0.1U_0402_16V7K
VGA@
1 2
C211 0.1U_0402_16V7K
VGA@
C211 0.1U_0402_16V7K
VGA@
1 2
C207 0.1U_0402_16V7K
VGA@
C207 0.1U_0402_16V7K
VGA@
1 2
C227 0.1U_0402_16V7K
VGA@
C227 0.1U_0402_16V7K
VGA@
1 2
C228 0.1U_0402_16V7K
VGA@
C228 0.1U_0402_16V7K
VGA@
1 2
D44 RB751V_SOD323
SG@
D44 RB751V_SOD323
SG@
21
R492
2.2K_0402_5%
@
R492
2.2K_0402_5%
@
12
C203 0.1U_0402_16V7K
VGA@
C203 0.1U_0402_16V7K
VGA@
1 2
C213 0.1U_0402_16V7K
VGA@
C213 0.1U_0402_16V7K
VGA@
1 2
R99 10K_0402_5%VGA@R99 10K_0402_5%VGA@ 12
C214 0.1U_0402_16V7K
VGA@
C214 0.1U_0402_16V7K
VGA@
1 2
C212 0.1U_0402_16V7K
VGA@
C212 0.1U_0402_16V7K
VGA@
1 2
C229 0.1U_0402_16V7K
VGA@
C229 0.1U_0402_16V7K
VGA@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VDD2DI
+AVDD
VGA_GPIO1
VGA_GPIO2
GENERICC
THM_ALERT#
SOUT_GPIO8
SIN_GPIO9
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
+DPLL_VDDC
GPU_THERM_D+
+VDD1DI
ROMSE_GPIO22
GPU_VID0
+DPLL_PVDD
VGA_GPIO0
GPU_VID1
XTALOUT
27MCLK
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
ROMSE_GPIO22
GENERICC
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
SOUT_GPIO8
SIN_GPIO9
+VGA_VREF
VGA_ENBKL
GPU_THERM_D-
+TSVDD
VGA_AC_DET
VGA_SMB_DA2
GPU_THERM_D-
VGA_SMB_CK2
GPU_THERM_D+
VRAM_ID3
VRAM_ID1
VRAM_ID2
VRAM_ID0
TRSTB
TCK
TMS
+A2VDDQ
27MCLKXTALOUT
ACIN_BUF VGA_AC_DET
THM_ALERT#
EC_SMB_DA2
EC_SMB_CK2
VGA_SMB_DA2
VGA_SMB_CK2
H2SYNC
V2SYNC
VGA_CRT_B
VGA_CRT_VSYNC
VGA_CRT_HSYNC
VGA_CRT_DATA
VGA_HDMI_SCLK
VGA_HDMI_SDATA
VGA_CRT_G
VGA_CRT_CLK
V2SYNC
H2SYNC
VGA_CRT_R
VGA_HDMI_SDATA
VGA_HDMI_SCLK
VGA_CRT_CLK
VGA_CRT_DATA
VGA_LCD_DAT
VGA_LCD_CLK
VGA_HDMI_DET
+A2VDD
TCK
ACIN
VRAM_ID1
VRAM_ID2
VRAM_ID3
VRAM_ID0
ACIN_BUF
TRSTB
TMS
TESTEN
GPU_VID0<51>
VGA_ENBKL<13>
GPU_VID1<51>
EC_SMB_CK2 <8,36>
EC_SMB_DA2 <8,36>
VGA_CRT_R <25>
VGA_CRT_G <25>
VGA_CRT_B <25>
VGA_CRT_HSYNC <25>
VGA_CRT_VSYNC <25>
VGA_HDMI_TXC+ <24>
VGA_HDMI_TXC- <24>
VGA_HDMI_TXD0+ <24>
VGA_HDMI_TXD0- <24>
VGA_HDMI_TXD1+ <24>
VGA_HDMI_TXD1- <24>
VGA_HDMI_TXD2- <24>
VGA_HDMI_TXD2+ <24>
VGA_HDMI_SCLK <24>
VGA_HDMI_SDATA <24>
VGA_CRT_CLK <25>
VGA_CRT_DATA <25>
VGA_LCD_CLK<23> VGA_LCD_DAT<23>
VGA_HDMI_DET<24,27>
27M_NSSC<22>
ACIN <36,37,42,43>
TESTEN <17>
+1.8VSG
+1.8VSG
+1.0VSG
+1.8VSG
+1.8VSG
+3VSG
+1.8VSG
+3VSG
+3VSG
+3VSG
+3VSG
+3VSG
+3VSG
+3VSG
+1.8VSG
+1.8VSG
+3VALW
+1.8VSG
+3VSG
+3VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
C
16 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
C
16 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
C
16 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
GPIO11
GPIO12
GPIO13 GPIO13,12,11 (config 2,1,0) :
VIP_DEVICE_EN
1
VIP Device Strap Enable indicates to the software driver
Strap Name Pin Straps description <all internal PD>
001
50mA
BIOS_ROM_EN
Setting
GPIO22 Enable external BIOS ROM device
0: Diable, 1: Enable
00: No audio function; 10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0
1
0: Driver would ignore the value sampled on VHAD_0 during reset
a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.
b) If BIOS_ROM_EN = 0, then Config[2:0] defines
the primary memory aperture size.
120mA
150mA
20mA
70mA
45mA
AUD[1]
130mA
AUD(0)
memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010
HSYNC
VSYNC
GPIO9
11
VGA Disable determines
V2SYNC
CONFIG[2]
0: VGA Controller capacity enabled
CONFIG[1]
1: The device will not be recognized as the system’s VGA controller
CONFIG[0]
0
0
External VGA Thermal Sensor
NC on Park FLASH ROM
HDMI
CRT
20mA
Not share via for other GND
Strap
Check If needed?
1: VHAD_0 to determine whether or not a VIP slave device
VGA_DIS
TX_PWRS_ENB GPIO0 Transmitter Power Saving Enable 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO1TX_DEEMPH_EN PCI Express Transmitter De-emphasis Enable 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
BIF_GEN2_EN GPIO2 0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
5.0 GT/s capability will be controlled by software
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0
RESERVED H2SYNC GPIO8
GPIO21
Internal use only. THIS PAD HAS AN INTERNAL
PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
NC on Park
NC on Park
NC on Park
Park NC pins
PD-Reset
NC on Park
Internal PD
1001 101X b
Address
A 1-Mbit serial EEPROM is
required on GDDR5 designs
DDR3 can be removed
For VGA boot unstable issue
<vandor> <size> 64MX16
VRAM_ID2 VRAM_ID1 VRAM_ID0
VRAM
O O
Location VRAM_ID3
OO
1
1
1
<4 pcs>
1
<vendor2>
O
1O O
Park
(XT)
1
Madsion
(Pro)
Hynix(128MbX16)
<8 pcs>
AMD
<size>
Hynix(128MbX16)
OO
<4 pcs>
1
1O
O
<4 pcs>
1
<8 pcs>
O
<8 pcs>
Samsung
Hynix
<8 pcs>
1
<vendor1> <pcs>
<4 pcs>
64MX16
VRAM_ID2 VRAM_ID1 VRAM_ID0
VRAM
Samsung O 1 O O
Location VRAM_ID3
OO1Hynix
AMD 1 1 O
R1481M_0603_5%
VGA@
R1481M_0603_5%
VGA@
R127 0_0402_5%
VGA@
R127 0_0402_5%
VGA@
1 2
L23
BLM18AG121SN1D_0603
VGA@
L23
BLM18AG121SN1D_0603
VGA@
12
R137 10K_0402_5%VGA@ R137 10K_0402_5%VGA@
1 2
R130 10K_0402_5%
@
R130 10K_0402_5%
@
12
R113 10K_0402_5%@R113 10K_0402_5%@
1 2
C241
10U_0603_6.3V6M
VGA@
C241
10U_0603_6.3V6M
VGA@
1
2
R111 10K_0402_5%@R111 10K_0402_5%@
1 2
R108 4.7K_0402_5%VGA@R108 4.7K_0402_5%VGA@
1 2
R103
4.7K_0402_5%
VGA@
R103
4.7K_0402_5%
VGA@
1 2
R116 10K_0402_5%@R116 10K_0402_5%@
1 2
C257 10U_0603_6.3V6M
VGA@
C257 10U_0603_6.3V6M
VGA@
1
2
C236
1U_0402_6.3V4Z
VGA@
C236
1U_0402_6.3V4Z
VGA@
1
2
R136 10K_0402_5%VGA@ R136 10K_0402_5%VGA@
1 2
R128 10K_0402_5%
@
R128 10K_0402_5%
@
12
C249
10U_0603_6.3V6M
VGA@
C249
10U_0603_6.3V6M
VGA@
1
2
C237
0.1U_0402_16V4Z
VGA@
C237
0.1U_0402_16V4Z
VGA@
1
2
C252 10U_0603_6.3V6M
VGA@
C252 10U_0603_6.3V6M
VGA@
1
2
C259 1U_0402_6.3V4Z
VGA@
C259 1U_0402_6.3V4Z
VGA@
1
2
U6
ADM1032ARMZ-2REEL_MSOP8
VGA@U6
ADM1032ARMZ-2REEL_MSOP8
VGA@
VDD
1
ALERT# 6
THERM#
4GND 5
D+
2
D-
3
SCLK 8
SDATA 7
C247
0.1U_0402_16V4Z
VGA@
C247
0.1U_0402_16V4Z
VGA@
1
2
C240
1U_0402_6.3V4Z
VGA@
C240
1U_0402_6.3V4Z
VGA@
1
2
R141 10K_0402_5%VGA@ R141 10K_0402_5%VGA@
1 2
R145 150_0402_1%VGA@ R145 150_0402_1%VGA@
1 2
R135 249_0402_1%VGA@R135 249_0402_1%VGA@
1 2
R119 10K_0402_5%@R119 10K_0402_5%@
1 2
R144 150_0402_1%VGA@ R144 150_0402_1%VGA@
1 2
C233
2200P_0402_50V7K
VGA@
C233
2200P_0402_50V7K
VGA@
1 2
C239
0.1U_0402_16V4Z
VGA@
C239
0.1U_0402_16V4Z
VGA@
1
2
R125 10K_0402_5%
@
R125 10K_0402_5%
@
12
T12T12
R107 10K_0402_5%VGA@ R107 10K_0402_5%VGA@
1 2
R120
10K_0402_5%
VGA@R120
10K_0402_5%
VGA@
12
C250 0.1U_0402_16V4Z
VGA@
C250 0.1U_0402_16V4Z
VGA@
1
2
C242
1U_0402_6.3V4Z
VGA@
C242
1U_0402_6.3V4Z
VGA@
1
2
C232
0.1U_0402_16V4Z
VGA@
C232
0.1U_0402_16V4Z
VGA@
1
2
R131 10K_0402_5%
@
R131 10K_0402_5%
@
12
L21
BLM18AG121SN1D_0603
VGA@
L21
BLM18AG121SN1D_0603
VGA@
12
R133 499_0402_1%VGA@R133 499_0402_1%VGA@
1 2
L19
BLM18AG121SN1D_0603
VGA@
L19
BLM18AG121SN1D_0603
VGA@
12
R102
4.7K_0402_5%
VGA@
R102
4.7K_0402_5%
VGA@
1 2
L22
BLM18AG121SN1D_0603
VGA@L22
BLM18AG121SN1D_0603
VGA@
12
R138 10K_0402_5%VGA@ R138 10K_0402_5%VGA@
1 2
R123 10K_0402_5%
@
R123 10K_0402_5%
@
12
C255 0.1U_0402_16V4Z
VGA@
C255 0.1U_0402_16V4Z
VGA@
1
2
R597
0_0402_5%
VGA@
R597
0_0402_5%
VGA@
12
C262
18P_0402_50V8J
VGA@
C262
18P_0402_50V8J
VGA@
R115 10K_0402_5%VGA@ R115 10K_0402_5%VGA@
1 2
R118 3K_0402_5%@R118 3K_0402_5%@
1 2
R105 4.7K_0402_5%VGA@R105 4.7K_0402_5%VGA@
1 2
C251 1U_0402_6.3V4Z
VGA@
C251 1U_0402_6.3V4Z
VGA@
1
2
R147 10K_0402_5%
VGAOPT@
R147 10K_0402_5%
VGAOPT@
1 2
C258 10U_0603_6.3V6M
VGA@
C258 10U_0603_6.3V6M
VGA@
1
2
L16
BLM18AG121SN1D_0603
VGA@
L16
BLM18AG121SN1D_0603
VGA@
12
R129 10K_0402_5%
@
R129 10K_0402_5%
@
12
C245 0.1U_0402_16V4Z
VGA@
C245 0.1U_0402_16V4Z
VGA@
1 2
R420 10K_0402_5%
VGAOPT@
R420 10K_0402_5%
VGAOPT@
1 2
C263
18P_0402_50V8J
VGA@
C263
18P_0402_50V8J
VGA@
C246
1U_0402_6.3V4Z
VGA@
C246
1U_0402_6.3V4Z
VGA@
1
2
C256
1U_0402_6.3V4Z
VGA@
C256
1U_0402_6.3V4Z
VGA@
1
2
R132 10K_0402_5%@R132 10K_0402_5%@
1 2
R122 499_0402_1%VGA@R122 499_0402_1%VGA@
1 2
L17
BLM18AG121SN1D_0603
VGA@
L17
BLM18AG121SN1D_0603
VGA@
12
T17T17
R101 4.7K_0402_5%
VGA@
R101 4.7K_0402_5%
VGA@
1 2
R143 150_0402_1%VGA@ R143 150_0402_1%VGA@
1 2
C260 0.1U_0402_16V4Z
VGA@
C260 0.1U_0402_16V4Z
VGA@
1
2
T14T14
R421 10K_0402_5%
VGAOPT@
R421 10K_0402_5%
VGAOPT@
1 2
C253 0.1U_0402_16V4Z
VGA@
C253 0.1U_0402_16V4Z
VGA@
1
2
Q5A DMN66D0LDW-7_SOT363-6
VGA@
Q5A DMN66D0LDW-7_SOT363-6
VGA@
61
2
R134 10K_0402_5%@R134 10K_0402_5%@
1 2
R142 10K_0402_5%VGA@ R142 10K_0402_5%VGA@
1 2
L20
BLM18AG121SN1D_0603
VGA@
L20
BLM18AG121SN1D_0603
VGA@
12
R117 10K_0402_5%@R117 10K_0402_5%@
1 2
D2
CH751H-40PT_SOD323-2
@D2
CH751H-40PT_SOD323-2
@
21
R124 10K_0402_5%
@
R124 10K_0402_5%
@
12
R104 10K_0402_5%VGA@ R104 10K_0402_5%VGA@
1 2
C238
22U_0805_6.3V6M
VGA@
C238
22U_0805_6.3V6M
VGA@
1
2
R110 10K_0402_5%@R110 10K_0402_5%@
1 2
C254 1U_0402_6.3V4Z
VGA@
C254 1U_0402_6.3V4Z
VGA@
1
2
R126 10K_0402_5%
@
R126 10K_0402_5%
@
12
Y1
27MHZ_16PF_X5H027000FG1H
VGA@Y1
27MHZ_16PF_X5H027000FG1H
VGA@
2 1
C248
10U_0603_6.3V6M
VGA@
C248
10U_0603_6.3V6M
VGA@
1
2
C243
0.1U_0402_16V4Z
VGA@
C243
0.1U_0402_16V4Z
VGA@
1
2
R139 10K_0402_5%VGA@ R139 10K_0402_5%VGA@
1 2
T11T11
C244
10U_0603_6.3V6M
VGA@
C244
10U_0603_6.3V6M
VGA@
1
2
Q5B
DMN66D0LDW-7_SOT363-6
VGA@Q5B
DMN66D0LDW-7_SOT363-6
VGA@
3
5
4
L18
BLM18AG121SN1D_0603
VGA@
L18
BLM18AG121SN1D_0603
VGA@
12
R140
715_0402_1%
VGA@
R140
715_0402_1%
VGA@
1 2
DPA
DPB
DPC
DPD
MUTI GFX
I2C
GENERAL PURPOSE I/O
DAC1
DAC2
DDC/AUX
THERMAL
PLL/CLOCK
216-0729002 A12 M96_BGA962
U5B
MAD@
DPA
DPB
DPC
DPD
MUTI GFX
I2C
GENERAL PURPOSE I/O
DAC1
DAC2
DDC/AUX
THERMAL
PLL/CLOCK
216-0729002 A12 M96_BGA962
U5B
MAD@
DMINUS
AG29
DPLL_PVDD
AM32 DPLL_PVSS
AN32
DPLL_VDDC
AN31
DPLUS
AF29
DVPCLK
AR1
DVPCNTL_0
AP8 DVPCNTL_1
AW8 DVPCNTL_2
AR3
DVPCNTL_MVP_0
AR8 DVPCNTL_MVP_1
AU8
DVPDATA_0
AU1 DVPDATA_1
AU3
DVPDATA_10
AV7 DVPDATA_11
AN7 DVPDATA_12
AV9 DVPDATA_13
AT9 DVPDATA_14
AR10 DVPDATA_15
AW10 DVPDATA_16
AU10 DVPDATA_17
AP10 DVPDATA_18
AV11 DVPDATA_19
AT11
DVPDATA_2
AW3
DVPDATA_20
AR12 DVPDATA_21
AW12 DVPDATA_22
AU12 DVPDATA_23
AP12
DVPDATA_3
AP6 DVPDATA_4
AW5 DVPDATA_5
AU5 DVPDATA_6
AR6 DVPDATA_7
AW6 DVPDATA_8
AU6 DVPDATA_9
AT7
GENERICA
AJ19 GENERICB
AK19 GENERICC
AJ20 GENERICD
AK20 GENERICE_HPD4
AJ24 GENERICF
AH26 GENERICG
AH24
GPIO_0
AH20 GPIO_1
AH18
GPIO_10_ROMSCK
AJ16 GPIO_11
AK16 GPIO_12
AL16 GPIO_13
AM16 GPIO_14_HPD2
AM14 GPIO_15_PWRCNTL_0
AM13 GPIO_16_SSIN
AK14 GPIO_17_THERMAL_INT
AG30 GPIO_18_HPD3
AN14 GPIO_19_CTF
AM17
GPIO_2
AN16
GPIO_20_PWRCNTL_1
AL13 GPIO_21_BB_EN
AJ14 GPIO_22_ROMCSB
AK13 GPIO_23_CLKREQB
AN13
GPIO_3_SMBDATA
AH23 GPIO_4_SMBCLK
AJ23 GPIO_5_AC_BATT
AH17 GPIO_6
AJ17 GPIO_7_BLON
AK17 GPIO_8_ROMSO
AJ13 GPIO_9_ROMSI
AH15
H2SYNC AD29
HPD1
AK24
HSYNC AC36
JTAG_TCK
AK23 JTAG_TDI
AN23
JTAG_TDO
AM24 JTAG_TMS
AL24
JTAG_TRSTB
AM23
NC_DDCDATA_AUX7N AK29
NC_DDCCLK_AUX7P AK30
TS_FDO
AK32 TSVDD
AJ32 TSVSS
AJ33
VREFG
AH13
VSS1DI AC34
VSS2DI AG32
XTALIN
AV33 XTALOUT
AU34
A2VDD AG33
A2VDDQ AD33
A2VSSQ AF33
AUX1N AL27
AUX1P AM27
AUX2N AM20
AUX2P AN20
AVDD AD34
AVSSQ AE34
BAF37
B2 AF30
B2B AF31
BB AE38
CAC32
COMP AF32
DDC1CLK AM26
DDC1DATA AN26
DDC2CLK AM19
DDC2DATA AL19
DDC6CLK AJ30
DDC6DATA AJ31
DDCDATA_AUX3N AM30
DDCCLK_AUX3P AL30
DDCDATA_AUX4N AM29
DDCCLK_AUX4P AL29
DDCDATA_AUX5N AM21
DDCCLK_AUX5P AN21
GAE36
G2 AD30
G2B AD31
GB AD35
RAD39
R2 AC30
R2B AC31
R2SET AA29
RB AD37
RSET AB34
SCL
AK26 SDA
AJ26
TX0M_DPA2N AR24
TX0M_DPC2N AR14
TX0P_DPA2P AT25
TX0P_DPC2P AT15
TX1M_DPA1N AV25
TX1M_DPC1N AV15
TX1P_DPA1P AU26
TX1P_DPC1P AU16
TX2M_DPA0N AR26
TX2M_DPC0N AR16
TX2P_DPA0P AT27
TX2P_DPC0P AT17
TX3M_DPB2N AU30
TX3M_DPD2N AR20
TX3P_DPB2P AV31
TX3P_DPD2P AT21
TX4M_DPB1N AT31
TX4M_DPD1N AV21
TX4P_DPB1P AR32
TX4P_DPD1P AU22
TX5M_DPB0N AU32
TX5M_DPD0N AR22
TX5P_DPB0P AT33
TX5P_DPD0P AT23
TXCAM_DPA3N AV23
TXCAP_DPA3P AU24
TXCBM_DPB3N AT29
TXCBP_DPB3P AR30
TXCCM_DPC3N AV13
TXCCP_DPC3P AU14
TXCDM_DPD3N AT19
TXCDP_DPD3P AU20
V2SYNC AC29
VDD1DI AC33
VDD2DI AG31
VSYNC AC38
YAD32
U7
NC7SZ08P5X_NL_SC70-5@
U7
NC7SZ08P5X_NL_SC70-5@
B2
A1
Y
4
P5
G
3
R109 10K_0402_5%@R109 10K_0402_5%@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAB12
DQMA#7
DQMB#5
CASA0#
B_BA2
QSA1
CKEA0
QSA#2
CKEB1
DQMA#1
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
CASB0#
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
QSA#3
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MVREFDA
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
CKEA1
QSA2
DQMB#6
B_BA0
QSA#4
CLKA0
CASB1#
QSA3
TEST_MCLK
A_BA2
MVREFSA
QSA#5
CASA1#
DQMA#2
MVREFDB
B_BA1
QSA4
CLKA0#
QSA#6
DQMB#7
QSA5
RASB0#
TEST_YCLK
QSB#1
QSA#7
MVREFSB
RASA0#
QSA6
DQMA#3
WEA0#
RASB1#
CLKB1
QSA7
MVREFSB
MDB51
MDB15
MDB16
MDB52
MDB17
MDB53
MDB18
MDB54
MDB19
MDB55
MDB20
MDB56
MDB21
MDB57
MDB22
MDB58
MDB23
MDB59
MDB24
MDB60
MDB25
MDB61
MDB26
MDB27
MDB62
MDB28
MDB63
MDB[0..63]
WEA1#
MDB29
MDB30
MDB31
MDB32
MDB0
MDB33
MDB34
MDB35
MDB36
MDB37
MDB1
MDB38
MDB39
MDB2
MDB40
MDB3
MDB41
MDB4
MDB42
MDB5
MDB6
MDB43
MDB7
MDB44
MDB8
MDB45
MDB9
MDB46
MDB10
MDB47
MDB11
MDB48
MDB12
MDB49
MDB13
MDB50
MDB14
MAB0
QSB#2
CLKB1#
DQMA#4
MAB[0..12]
QSB#3
A_BA0
RASA1#
QSB#4
MAA0
DQMA#5
DQMB#1
QSB#5
MVREFDA
MAB1
WEB0#
QSB#6
QSB#[0..7]
MAA1
CSB0#_0
MAB2
B_BA[0..2]
TESTEN
DQMB#2
MVREFSA
QSB#7
MAB3
WEB1#
MAA2
MAB4
MAA3
A_BA1
DQMB#0
CLKA1
CSA1#_0
MAA4 MAB5
CSB1#_0
QSA#0
DQMB#3
MAA5 MAB6
CLKB0
MAA6
CLKA1#
DQMB#[0..7]
QSA0
MAB7
CSA0#_0
MAA7 MAB8MAA8
CLKB0#
DQMA#6
DQMB#4
MAB9MAA9
DQMA#0
QSA#1
MAB10MAA10
QSB#0
MAA11 MAB11
CKEB0
MAA12
ODTA0
ODTA1 ODTB0 ODTB1
MAA[0..12]
A_BA[0..2]
DQMA#[0..7]
QSA[0..7]
MDA[0..63]
QSA#[0..7]
QSB1
QSB2
QSB[0..7]
QSB7
QSB3
QSB0
QSB4
QSB6
QSB5
MVREFDBMVREFDB
GCORE_SEN TESTEN
MDA[0..63]<20> MDB[0..63]<21>
MAA[0..12] <20>
A_BA[0..2] <20>
DQMA#[0..7] <20>
QSA[0..7] <20>
QSA#[0..7] <20>
ODTA0 <20>
ODTA1 <20>
CLKA0 <20>
CLKA0# <20>
CLKA1 <20>
CLKA1# <20>
RASA0# <20>
RASA1# <20>
CASA1# <20>
CASA0# <20>
CSA0#_0 <20>
CSA1#_0 <20>
CKEA0 <20>
CKEA1 <20>
WEA1# <20>
WEA0# <20>
QSB#[0..7] <21>
QSB[0..7] <21>
MAB[0..12] <21>
B_BA[0..2] <21>
DQMB#[0..7] <21>
ODTB0 <21>
ODTB1 <21>
CLKB0 <21>
CLKB0# <21>
CLKB1 <21>
CLKB1# <21>
RASB1# <21>
RASB0# <21>
CSB1#_0 <21>
CASB1# <21>
CASB0# <21>
CSB0#_0 <21>
WEB1# <21>
CKEB1 <21>
CKEB0 <21>
WEB0# <21>
VRAM_RST# <20,21>MAA13 <20>
MAB13 <21>
GCORE_SEN <51>
TESTEN<16>
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
17 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
17 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
17 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
M96 no support
In M97, Medison and Park, AF28 is
FB_VDDC, AG28 is FB_VDDCI, AH29 is
FB_GND. GCORE_SEN and FB_GND
should route as differential pair Same
as VDDCI_SEN and FB_GND
M96 use 4.7K to
PD directly.
M96 Broadway
10k Ohm
SD028100280
680 Ohm
SD028680080
R168
R166
C270 68 pF
SE071680J80
DNI
4.7k Ohm
SD028470180
0 Ohm
SD028000080
1000 pF
SE074102K80
4.7k Ohm
SD028470180
R163
If use M96 upper resistor will
change to 100ohm for
MVREFDA/B and MVREFSA/B
If use M96 upper resistor will
change to 100ohm for
MVREFDA/B and MVREFSA/B
Park only support single channel
memory (channel B only)
Mahatten upper resistor use 40.2ohm Mahatten upper resistor use
40.2ohm
Modify for ATI suggestion
R151
40.2_0402_1%
VGA@
R151
40.2_0402_1%
VGA@
12
C267
0.1U_0402_16V4Z
VGA@
C267
0.1U_0402_16V4Z
VGA@
1
2R168
10K_0402_5%
VGA@
R168
10K_0402_5%
VGA@
1 2
R156
40.2_0402_1%
VGA@
R156
40.2_0402_1%
VGA@
12
R164 240_0402_1%
VGA@
R164 240_0402_1%
VGA@
1 2
R159 240_0402_1%
VGA@
R159 240_0402_1%
VGA@
1 2
MEMORY INTERFACE A
216-0729002 A12 M96_BGA962
U5C
MAD@
MEMORY INTERFACE A
216-0729002 A12 M96_BGA962
U5C
MAD@
DQA_0
C37 DQA_1
C35
DQA_10
C30 DQA_11
A30 DQA_12
F28 DQA_13
C28 DQA_14
A28 DQA_15
E28 DQA_16
D27 DQA_17
F26 DQA_18
C26 DQA_19
A26
DQA_2
A35
DQA_20
F24 DQA_21
C24 DQA_22
A24 DQA_23
E24 DQA_24
C22 DQA_25
A22 DQA_26
F22 DQA_27
D21 DQA_28
A20 DQA_29
F20
DQA_3
E34
DQA_30
D19 DQA_31
E18 DQA_32
C18 DQA_33
A18 DQA_34
F18 DQA_35
D17 DQA_36
A16 DQA_37
F16 DQA_38
D15 DQA_39
E14
DQA_4
G32
DQA_40
F14 DQA_41
D13 DQA_42
F12 DQA_43
A12 DQA_44
D11 DQA_45
F10 DQA_46
A10 DQA_47
C10 DQA_48
G13 DQA_49
H13
DQA_5
D33
DQA_50
J13 DQA_51
H11 DQA_52
G10 DQA_53
G8 DQA_54
K9 DQA_55
K10 DQA_56
G9 DQA_57
A8 DQA_58
C8 DQA_59
E8
DQA_6
F32
DQA_60
A6 DQA_61
C6 DQA_62
E6 DQA_63
A5
DQA_7
E32 DQA_8
D31 DQA_9
F30
MEM_CALRP1
M12
MVREFDA
L18 MVREFSA
L20
NC_MEM_CALRN0
L27 NC_MEM_CALRN1
N12 NC_MEM_CALRN2
AG12
NC_MEM_CALRP0
M27 NC_MEM_CALRP2
AH12
CASA0B K20
CASA1B K17
CKEA0 K21
CKEA1 J20
CLKA0 H27
CLKA0B G27
CLKA1 J14
CLKA1B H14
CSA0B_0 K24
CSA0B_1 K27
CSA1B_0 M13
CSA1B_1 K16
DQMA_0 A32
DQMA_1 C32
DQMA_2 D23
DQMA_3 E22
DQMA_4 C14
DQMA_5 A14
DQMA_6 E10
DQMA_7 D9
MAA_0 G24
MAA_1 J23
MAA_10 L13
MAA_11 G16
MAA_12 J16
MAA_13/BA2 H16
MAA_14/BA0 J17
MAA_15/BA1 H17
MAA_2 H24
MAA_3 J24
MAA_4 H26
MAA_5 J26
MAA_6 H21
MAA_7 G21
MAA_8 H19
MAA_9 H20
ODTA0 J21
ODTA1 G19
RASA0B K23
RASA1B K19
QSA_0/RDQSA_0 C34
QSA_1/RDQSA_1 D29
QSA_2/RDQSA_2 D25
QSA_3/RDQSA_3 E20
QSA_4/RDQSA_4 E16
QSA_5/RDQSA_5 E12
QSA_6/RDQSA_6 J10
QSA_7/RDQSA_7 D7
RSVD#1 AF28
RSVD#9 T8
RSVD#11 W8
RSVD#2 AG28
RSVD#3 AL31
RSVD#5 H23
RSVD#6 J19
QSA_0B/WDQSA_0 A34
QSA_1B/WDQSA_1 E30
QSA_2B/WDQSA_2 E26
QSA_3B/WDQSA_3 C20
QSA_4B/WDQSA_4 C16
QSA_5B/WDQSA_5 C12
QSA_6B/WDQSA_6 J11
QSA_7B/WDQSA_7 F8
WEA0B K26
WEA1B L15
R167
100_0402_1%
VGA@
R167
100_0402_1%
VGA@
12
C268
0.1U_0402_16V4Z
VGA@C268
0.1U_0402_16V4Z
VGA@
1
2
R158 240_0402_1%
VGA@
R158 240_0402_1%
VGA@
1 2
C270
68P_0402_50V8J
VGA@
C270
68P_0402_50V8J
VGA@
1
2
R157
40.2_0402_1%
VGA@
R157
40.2_0402_1%
VGA@
12
R154
100_0402_1%
VGA@
R154
100_0402_1%
VGA@
12
R170
51.1_0402_1%
VGA@
R170
51.1_0402_1%
VGA@
12
C264
0.1U_0402_16V4Z
VGA@
C264
0.1U_0402_16V4Z
VGA@
1
2
R169
51.1_0402_1%
VGA@
R169
51.1_0402_1%
VGA@
12
C265
0.1U_0402_16V4Z
VGA@
C265
0.1U_0402_16V4Z
VGA@
1
2
R155 240_0402_1%
VGA@
R155 240_0402_1%
VGA@
1 2
R152
40.2_0402_1%
VGA@
R152
40.2_0402_1%
VGA@
12
C269
0.1U_0402_16V4Z
VGA@C269
0.1U_0402_16V4Z
VGA@
1
2
R163
4.7K_0402_5%@R163 4.7K_0402_5%@
1 2
R166
51.1_0402_1%
VGA@R166
51.1_0402_1%
VGA@
1 2
R162 240_0402_1%
VGA@
R162 240_0402_1%
VGA@
1 2
R153
100_0402_1%
VGA@
R153
100_0402_1%
VGA@
12
R161 10K_0402_5%R161 10K_0402_5%
1 2
C266 0.1U_0402_16V4Z
VGA@
C266 0.1U_0402_16V4Z
VGA@
1
2
R165
100_0402_1%
VGA@
R165
100_0402_1%
VGA@
12
MEMORY INTERFACE B
216-0729002 A12 M96_BGA962
U5D
MAD@
MEMORY INTERFACE B
216-0729002 A12 M96_BGA962
U5D
MAD@
DQB_0
C5 DQB_1
C3
DQB_10
J4 DQB_11
K6 DQB_12
K5 DQB_13
L4 DQB_14
M6 DQB_15
M1 DQB_16
M3 DQB_17
M5 DQB_18
N4 DQB_19
P6
DQB_2
E3
DQB_20
P5 DQB_21
R4 DQB_22
T6 DQB_23
T1 DQB_24
U4 DQB_25
V6 DQB_26
V1 DQB_27
V3 DQB_28
Y6 DQB_29
Y1
DQB_3
E1
DQB_30
Y3 DQB_31
Y5 DQB_32
AA4 DQB_33
AB6 DQB_34
AB1 DQB_35
AB3 DQB_36
AD6 DQB_37
AD1 DQB_38
AD3 DQB_39
AD5
DQB_4
F1
DQB_40
AF1 DQB_41
AF3 DQB_42
AF6 DQB_43
AG4 DQB_44
AH5 DQB_45
AH6 DQB_46
AJ4 DQB_47
AK3 DQB_48
AF8 DQB_49
AF9
DQB_5
F3
DQB_50
AG8 DQB_51
AG7 DQB_52
AK9 DQB_53
AL7 DQB_54
AM8 DQB_55
AM7 DQB_56
AK1 DQB_57
AL4 DQB_58
AM6 DQB_59
AM1
DQB_6
F5
DQB_60
AN4 DQB_61
AP3 DQB_62
AP1 DQB_63
AP5
DQB_7
G4 DQB_8
H5 DQB_9
H6
MVREFDB
Y12 MVREFSB
AA12
TESTEN
AD28
CASB0B W10
CASB1B AA10
CKEB0 U10
CKEB1 AA11
CLKB0 L9
CLKB0B L8
CLKB1 AD8
CLKB1B AD7
CLKTESTA
AK10 CLKTESTB
AL10
CSB0B_0 P10
CSB0B_1 L10
CSB1B_0 AD10
CSB1B_1 AC10
DQMB_0 H3
DQMB_1 H1
DQMB_2 T3
DQMB_3 T5
DQMB_4 AE4
DQMB_5 AF5
DQMB_6 AK6
DQMB_7 AK5
DRAM_RST AH11
MAB_0 P8
MAB_1 T9
MAB_10 AC8
MAB_11 AC9
MAB_12 AA7
MAB_13/BA2 AA8
MAB_14/BA0 Y8
MAB_15/BA1 AA9
MAB_2 P9
MAB_3 N7
MAB_4 N8
MAB_5 N9
MAB_6 U9
MAB_7 U8
MAB_8 Y9
MAB_9 W9
ODTB0 T7
ODTB1 W7
RASB0B T10
RASB1B Y10
QSB_0/RDQSB_0 F6
QSB_1/RDQSB_1 K3
QSB_2/RDQSB_2 P3
QSB_3/RDQSB_3 V5
QSB_4/RDQSB_4 AB5
QSB_5/RDQSB_5 AH1
QSB_6/RDQSB_6 AJ9
QSB_7/RDQSB_7 AM5
QSB_0B/WDQSB_0 G7
QSB_1B/WDQSB_1 K1
QSB_2B/WDQSB_2 P1
QSB_3B/WDQSB_3 W4
QSB_4B/WDQSB_4 AC4
QSB_5B/WDQSB_5 AH3
QSB_6B/WDQSB_6 AJ8
QSB_7B/WDQSB_7 AM3
WEB0B N10
WEB1B AB11
R160 240_0402_1%
VGA@
R160 240_0402_1%
VGA@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VDDR4_5
+VDD_CT
+SPV10
+VDDR3
+PCIE_VDDR
+PCIE_PVDD
+SPV_18
+MPV_18
+VDDCI
+1.5VSG
+1.8VSG
+3VSG
+1.8VSG
+1.8VSG
+VGA_CORE
+1.0VSG
+1.8VSG
+VGA_CORE
+1.8VSG
+1.8VSG
+1.0VSG
+VGA_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
18 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
18 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
18 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
60mA
5A
136mA
68mA
2A
400mA
136mA
170mA
2900mA
TBD
170mA
32mA
34.6A
For M96 SPV10=+GPU_CORE
For M97,Nahattan SPV10=+1.0VS
MPV18 For
Mahattan only M97 and Mahattan VDDC and
VDDCI ball assignments are
different from M96, If M96 is
populated on this
design,VDDC and VDDCI
shoudl be shorted.
150mA
50mA
For M96 only,
Manhattan are NC pin
SPV18 For
Mahattan only Confirm ATI, for
Mahattan, it could be
connected to VGA_CORE
BIF_VDDCI (T27,N27) need
isolate VGA_CORE
*Confirm with AMD
Reserve for PWR test
C332 1U_0402_6.3V4Z
VGA@C332
1U_0402_6.3V4Z
VGA@
1
2
C331 1U_0402_6.3V4Z
VGA@C331
1U_0402_6.3V4Z
VGA@
1
2
C326 1U_0402_6.3V4Z
VGA@C326
1U_0402_6.3V4Z
VGA@
1
2
C337 1U_0402_6.3V4Z
VGA@C337
1U_0402_6.3V4Z
VGA@
1
2
C317 1U_0402_6.3V4Z
VGA@C317
1U_0402_6.3V4Z
VGA@
1
2
L96
FBMA-L11-201209-221LMA30T_0805
VGA@L96
FBMA-L11-201209-221LMA30T_0805
VGA@
12
C277 1U_0402_6.3V4Z
VGA@C277
1U_0402_6.3V4Z
VGA@
1
2
C381 0.1U_0402_16V4Z
VGA@C381
0.1U_0402_16V4Z
VGA@
1
2
C338 0.1U_0402_16V4Z
VGA@C338
0.1U_0402_16V4Z
VGA@
1
2
C309 10U_0805_6.3V6M
VGA@C309
10U_0805_6.3V6M
VGA@
1
2
C328 1U_0402_6.3V4Z
VGA@C328
1U_0402_6.3V4Z
VGA@
1
2
L34
BLM18AG121SN1D_0603
VGA@L34
BLM18AG121SN1D_0603
VGA@ 12
C375 1U_0402_6.3V4Z
VGA@C375
1U_0402_6.3V4Z
VGA@
1
2
C275 1U_0402_6.3V4Z
VGA@C275
1U_0402_6.3V4Z
VGA@
1
2
C383 10U_0805_6.3V6M
VGA@C383
10U_0805_6.3V6M
VGA@
1
2
C370 1U_0402_6.3V4Z
VGA@C370
1U_0402_6.3V4Z
VGA@
1
2
C343 10U_0805_6.3V6M
VGA@C343
10U_0805_6.3V6M
VGA@
1
2
C315 0.1U_0402_16V4Z
VGA@C315
0.1U_0402_16V4Z
VGA@
1
2
C374 1U_0402_6.3V4Z
VGA@C374
1U_0402_6.3V4Z
VGA@
1
2
C361 0.1U_0402_16V4Z
VGA@C361
0.1U_0402_16V4Z
VGA@
1
2
C367 1U_0402_6.3V4Z
VGA@C367
1U_0402_6.3V4Z
VGA@
1
2
C278 1U_0402_6.3V4Z
VGA@C278
1U_0402_6.3V4Z
VGA@
1
2
C350 0.1U_0402_16V4Z
VGA@C350
0.1U_0402_16V4Z
VGA@
1
2
C282 0.1U_0402_16V4Z
VGA@C282
0.1U_0402_16V4Z
VGA@
1
2
C335 1U_0402_6.3V4Z
VGA@C335
1U_0402_6.3V4Z
VGA@
1
2
C322 1U_0402_6.3V4Z
VGA@C322
1U_0402_6.3V4Z
VGA@
1
2
C359 10U_0603_6.3V6M
VGA@C359
10U_0603_6.3V6M
VGA@
1
2
C297 1U_0402_6.3V4Z
VGA@C297
1U_0402_6.3V4Z
VGA@
1
2
C290 1U_0402_6.3V4Z
VGA@C290
1U_0402_6.3V4Z
VGA@
1
2
C356 10U_0603_6.3V6M
VGA@C356
10U_0603_6.3V6M
VGA@
1
2
C339 10U_0805_6.3V6M
VGA@C339
10U_0805_6.3V6M
VGA@
1
2
C329 1U_0402_6.3V4Z
VGA@C329
1U_0402_6.3V4Z
VGA@
1
2
R569 0_0603_5%
VGA@
R569 0_0603_5%
VGA@ 12
C293 1U_0402_6.3V4Z
VGA@C293
1U_0402_6.3V4Z
VGA@
1
2
C384 10U_0805_6.3V6M
VGA@C384
10U_0805_6.3V6M
VGA@
1
2
C368 1U_0402_6.3V4Z
VGA@C368
1U_0402_6.3V4Z
VGA@
1
2
C304 10U_0805_6.3V6M
VGA@C304
10U_0805_6.3V6M
VGA@
1
2
C285 1U_0402_6.3V4Z
VGA@C285
1U_0402_6.3V4Z
VGA@
1
2
C280 1U_0402_6.3V4Z
VGA@C280
1U_0402_6.3V4Z
VGA@
1
2
L26
BLM18AG121SN1D_0603
VGA@L26
BLM18AG121SN1D_0603
VGA@12
C357 1U_0402_6.3V4Z
VGA@C357
1U_0402_6.3V4Z
VGA@
1
2
C310 1U_0402_6.3V4Z
VGA@C310
1U_0402_6.3V4Z
VGA@
1
2
C307 10U_0805_6.3V6M
VGA@C307
10U_0805_6.3V6M
VGA@
1
2
C341 10U_0805_6.3V6M
VGA@C341
10U_0805_6.3V6M
VGA@
1
2
C365 0.1U_0402_16V4Z
VGA@C365
0.1U_0402_16V4Z
VGA@
1
2
C363 0.1U_0402_16V4Z
VGA@C363
0.1U_0402_16V4Z
VGA@
1
2
C377 10U_0603_6.3V6M
VGA@C377
10U_0603_6.3V6M
VGA@
1
2
C376 1U_0402_6.3V4Z
VGA@C376
1U_0402_6.3V4Z
VGA@
1
2
C312 1U_0402_6.3V4Z
VGA@C312
1U_0402_6.3V4Z
VGA@
1
2
C272 1U_0402_6.3V4Z
VGA@C272
1U_0402_6.3V4Z
VGA@
1
2
C276 1U_0402_6.3V4Z
VGA@C276
1U_0402_6.3V4Z
VGA@
1
2
C313 10U_0603_6.3V6M
VGA@C313
10U_0603_6.3V6M
VGA@
1
2
C358 0.1U_0402_16V4Z
VGA@C358
0.1U_0402_16V4Z
VGA@
1
2
C284 1U_0402_6.3V4Z
VGA@C284
1U_0402_6.3V4Z
VGA@
1
2
C279 1U_0402_6.3V4Z
VGA@C279
1U_0402_6.3V4Z
VGA@
1
2
+
C693
330U_D2_2V_Y
@
+
C693
330U_D2_2V_Y
@
1
2
C373 1U_0402_6.3V4Z
VGA@C373
1U_0402_6.3V4Z
VGA@
1
2
C299 1U_0402_6.3V4Z
VGA@C299
1U_0402_6.3V4Z
VGA@
1
2
L32
BLM18AG121SN1D_0603
VGA@L32
BLM18AG121SN1D_0603
VGA@12
C324 1U_0402_6.3V4Z
VGA@C324
1U_0402_6.3V4Z
VGA@
1
2
C334 1U_0402_6.3V4Z
VGA@C334
1U_0402_6.3V4Z
VGA@
1
2
C294 1U_0402_6.3V4Z
VGA@C294
1U_0402_6.3V4Z
VGA@
1
2
C300 1U_0402_6.3V4Z
VGA@C300
1U_0402_6.3V4Z
VGA@
1
2
C319 1U_0402_6.3V4Z
VGA@C319
1U_0402_6.3V4Z
VGA@
1
2
C320 1U_0402_6.3V4Z
VGA@C320
1U_0402_6.3V4Z
VGA@
1
2
C286 1U_0402_6.3V4Z
VGA@C286
1U_0402_6.3V4Z
VGA@
1
2
C380 1U_0402_6.3V4Z
VGA@C380
1U_0402_6.3V4Z
VGA@
1
2
C291 1U_0402_6.3V4Z
VGA@C291
1U_0402_6.3V4Z
VGA@
1
2
C283 0.1U_0402_16V4Z
VGA@C283
0.1U_0402_16V4Z
VGA@
1
2
C345 10U_0805_6.3V6M
VGA@C345
10U_0805_6.3V6M
VGA@
1
2
C316 1U_0402_6.3V4Z
VGA@C316
1U_0402_6.3V4Z
VGA@
1
2
C369 1U_0402_6.3V4Z
VGA@C369
1U_0402_6.3V4Z
VGA@
1
2
C305 10U_0603_6.3V6M
MAD@C305
10U_0603_6.3V6M
MAD@
1
2
C306 10U_0603_6.3V6M
VGA@C306
10U_0603_6.3V6M
VGA@
1
2
+
C340
330U_D2_2V_Y
VGA@
+
C340
330U_D2_2V_Y
VGA@
1
2
C301 1U_0402_6.3V4Z
VGA@C301
1U_0402_6.3V4Z
VGA@
1
2
C292 1U_0402_6.3V4Z
VGA@C292
1U_0402_6.3V4Z
VGA@
1
2
C333 1U_0402_6.3V4Z
VGA@C333
1U_0402_6.3V4Z
VGA@
1
2
L27
BLM18AG601SN1D_2P
VGA@L27
BLM18AG601SN1D_2P
VGA@12
C346 10U_0805_6.3V6M
VGA@C346
10U_0805_6.3V6M
VGA@
1
2
C308 10U_0805_6.3V6M
VGA@C308
10U_0805_6.3V6M
VGA@
1
2
C271 1U_0402_6.3V4Z
VGA@C271
1U_0402_6.3V4Z
VGA@
1
2
C349 1U_0402_6.3V4Z
VGA@C349
1U_0402_6.3V4Z
VGA@
1
2
C321 1U_0402_6.3V4Z
VGA@C321
1U_0402_6.3V4Z
VGA@
1
2
C379 0.1U_0402_16V4Z
VGA@C379
0.1U_0402_16V4Z
VGA@
1
2
C366 10U_0603_6.3V6M
VGA@C366
10U_0603_6.3V6M
VGA@
1
2
C288 1U_0402_6.3V4Z
VGA@C288
1U_0402_6.3V4Z
VGA@
1
2
C273 1U_0402_6.3V4Z
VGA@C273
1U_0402_6.3V4Z
VGA@
1
2
C323 1U_0402_6.3V4Z
VGA@C323
1U_0402_6.3V4Z
VGA@
1
2
C281 1U_0402_6.3V4Z
VGA@C281
1U_0402_6.3V4Z
VGA@
1
2
C314 1U_0402_6.3V4Z
VGA@C314
1U_0402_6.3V4Z
VGA@
1
2
C342 10U_0805_6.3V6M
VGA@C342
10U_0805_6.3V6M
VGA@
1
2
L31
BLM18AG121SN1D_0603
VGA@L31
BLM18AG121SN1D_0603
VGA@ 12
C336 10U_0603_6.3V6M
VGA@C336
10U_0603_6.3V6M
VGA@
1
2
C364 1U_0402_6.3V4Z
VGA@C364
1U_0402_6.3V4Z
VGA@
1
2
C287 1U_0402_6.3V4Z
VGA@C287
1U_0402_6.3V4Z
VGA@
1
2
C295 1U_0402_6.3V4Z
VGA@C295
1U_0402_6.3V4Z
VGA@
1
2
C378 1U_0402_6.3V4Z
VGA@C378
1U_0402_6.3V4Z
VGA@
1
2
C327 1U_0402_6.3V4Z
VGA@C327
1U_0402_6.3V4Z
VGA@
1
2
C344 10U_0805_6.3V6M
VGA@C344
10U_0805_6.3V6M
VGA@
1
2
L24
BLM18AG601SN1D_2P
VGA@L24
BLM18AG601SN1D_2P
VGA@
12
C372 1U_0402_6.3V4Z
VGA@C372
1U_0402_6.3V4Z
VGA@
1
2
POWER
PLL
PCIE
CORE
MEM I/O
MEM CLK
I/O
BACK BIAS
LEVEL
TRANSLATION
ISOLATED
CORE I/O
216-0729002 A12 M96_BGA962
U5E
MAD@
POWER
PLL
PCIE
CORE
MEM I/O
MEM CLK
I/O
BACK BIAS
LEVEL
TRANSLATION
ISOLATED
CORE I/O
216-0729002 A12 M96_BGA962
U5E
MAD@
PCIE_PVDD
AB37
NC_MPV18#1
H7 NC_MPV18#2
H8
NC_SPV18
AM10
PCIE_VDDC#1 G30
PCIE_VDDC#10 R28
PCIE_VDDC#11 T28
PCIE_VDDC#12 U28
PCIE_VDDC#2 G31
PCIE_VDDC#3 H29
PCIE_VDDC#4 H30
PCIE_VDDC#5 J29
PCIE_VDDC#6 J30
PCIE_VDDC#7 L28
PCIE_VDDC#8 M28
PCIE_VDDC#9 N28
PCIE_VDDR#1 AA31
PCIE_VDDR#2 AA32
PCIE_VDDR#3 AA33
PCIE_VDDR#4 AA34
PCIE_VDDR#5 V28
PCIE_VDDR#6 W29
PCIE_VDDR#7 W30
PCIE_VDDR#8 Y31
SPV10
AN9
SPVSS
AN10
VDDR1#1
AC7
VDDR1#10
G17 VDDR1#11
G20 VDDR1#12
G23 VDDR1#13
G26 VDDR1#14
G29 VDDR1#15
H10 VDDR1#16
J7 VDDR1#17
J9 VDDR1#18
K11 VDDR1#19
K13
VDDR1#2
AD11
VDDR1#20
K8 VDDR1#21
L12 VDDR1#22
L16 VDDR1#23
L21 VDDR1#24
L23 VDDR1#25
L26 VDDR1#26
L7 VDDR1#27
M11 VDDR1#28
N11 VDDR1#29
P7
VDDR1#3
AF7
VDDR1#30
R11 VDDR1#31
U11 VDDR1#32
U7 VDDR1#33
Y11 VDDR1#34
Y7
VDDR1#4
AG10 VDDR1#5
AJ7 VDDR1#6
AK8 VDDR1#7
AL9 VDDR1#8
G11 VDDR1#9
G14
VDDR3#1
AF23 VDDR3#2
AF24 VDDR3#3
AG23 VDDR3#4
AG24
VDDR5#1
AF13 VDDR5#2
AF15 VDDR5#3
AG13 VDDR5#4
AG15
VDDR4#1
AD12 VDDR4#2
AF11 VDDR4#3
AF12 VDDR4#4
AG11
VDDRHA
M20
VDDRHB
V12
VSSRHA
M21
VSSRHB
U12
VDD_CT#1
AF26 VDD_CT#2
AF27 VDD_CT#3
AG26 VDD_CT#4
AG27
VDDC#1 AA15
VDDC#10 AB21
VDDC#11 AB23
VDDC#12 AB26
VDDC#13 AB28
VDDC#14 AC12
VDDC#15 AC15
VDDC#16 AC17
VDDC#17 AC20
VDDC#18 AC22
VDDC#19 AC24
VDDC#2 AA17
VDDC#20 AC27
VDDC#21 AD13
VDDC#22 AD16
VDDC#23 AD18
VDDC#24 AD21
VDDC#25 AD23
VDDC#26 AD26
VDDC#27 AF17
VDDC#28 AF20
VDDC#29 AF22
VDDC#3 AA20
VDDC#30 AG16
VDDC#31 AG18
VDDC#32 AG21
VDDC#33 AH22
VDDC#34 M16
VDDC#35 M18
VDDC#36 M23
VDDC#37 M26
VDDC#38 N15
VDDC#39 N17
VDDC#4 AA22
VDDC#40 N20
VDDC#41 N22
VDDC#42 N24
VDDC#43 N27
VDDC#44 R13
VDDC#45 R16
VDDC#46 R18
VDDC#47 R21
VDDC#48 R23
VDDC#49 R26
VDDC#5 AA24
VDDC#50 T15
VDDC#51 T17
VDDC#52 T20
VDDC#53 T22
VDDC#54 T24
VDDC#55 T27
VDDC#56 U16
VDDC#57 U18
VDDC#58 U21
VDDC#59 U23
VDDC#6 AA27
VDDC#60 U26
VDDC#61 V15
VDDC#62 V17
VDDC#63 V20
VDDC#64 V22
VDDC#65 V24
VDDC#66 V27
VDDC#67 Y16
VDDC#68 Y18
VDDC#69 Y21
VDDC#7 AB13
VDDC#70 Y23
VDDC#71 Y26
VDDC#72 Y28
VDDC#8 AB16
VDDC#9 AB18
VDDCI#1 M15
VDDCI#2 N13
VDDCI#3 R12
VDDCI#4 T12
BBP#1
AA13 BBP#2
Y13 VDDC#73 AH27
VDDC#74 AH28
C348 10U_0603_6.3V6M
VGA@C348
10U_0603_6.3V6M
VGA@
1
2
C325 1U_0402_6.3V4Z
VGA@C325
1U_0402_6.3V4Z
VGA@
1
2
C296 1U_0402_6.3V4Z
VGA@C296
1U_0402_6.3V4Z
VGA@
1
2
C311 1U_0402_6.3V4Z
VGA@C311
1U_0402_6.3V4Z
VGA@
1
2
C302 1U_0402_6.3V4Z
VGA@C302
1U_0402_6.3V4Z
VGA@
1
2
C298 1U_0402_6.3V4Z
VGA@C298
1U_0402_6.3V4Z
VGA@
1
2
C289 10U_0805_6.3V6M
VGA@C289
10U_0805_6.3V6M
VGA@
1
2
C371 1U_0402_6.3V4Z
VGA@C371
1U_0402_6.3V4Z
VGA@
1
2
L35
BLM18AG121SN1D_0603
VGA@L35
BLM18AG121SN1D_0603
VGA@12
C303 1U_0402_6.3V4Z
VGA@C303
1U_0402_6.3V4Z
VGA@
1
2
C360 1U_0402_6.3V4Z
VGA@C360
1U_0402_6.3V4Z
VGA@
1
2
+
C347
330U_D2_2V_Y
VGA@
+
C347
330U_D2_2V_Y
VGA@
1
2
C362 1U_0402_6.3V4Z
VGA@C362
1U_0402_6.3V4Z
VGA@
1
2
C330 1U_0402_6.3V4Z
VGA@C330
1U_0402_6.3V4Z
VGA@
1
2
+
C274
330U_D2_2V_Y
VGA@
+
C274
330U_D2_2V_Y
VGA@
1
2
C382 10U_0805_6.3V6M
VGA@C382
10U_0805_6.3V6M
VGA@
1
2
L25
BLM18AG121SN1D_0603
VGA@L25
BLM18AG121SN1D_0603
VGA@12
L97
FBMA-L11-201209-221LMA30T_0805
VGA@L97
FBMA-L11-201209-221LMA30T_0805
VGA@
12
C318 1U_0402_6.3V4Z
VGA@C318
1U_0402_6.3V4Z
VGA@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+DPE_PVDD
+DPD_PVDD
+DPF_PVDD
+DPA_VDD10
+DPE_VDD18
+DPD_VDD10
+DPE_VDD10
+DPB_VDD10
+DPB_PVDD
+DPA_PVDD
+DPC_VDD18
+DPA_VDD18
+DPB_VDD18
FB_GND
+DPD_VDD18
+DPF_VDD10
+DPC_PVDD
+DPC_VDD10
+DPF_VDD18
+1.0VSG
+1.0VSG
+1.0VSG
+1.8VSG +1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.8VSG
+1.0VSG
+1.0VSG
+1.0VSG
+1.8VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
19 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
19 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
19 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Ball AW34 and AW35
are GND ball in M96,
but have another ball
name in Broadway,
that is XO_IN and
X0_IN2.
200mA
200mA
200mA
200mA
120mA
120mA
20mA
20mA
20mA
20mA
20mA
200mA
200mA
130mA
130mA
130mA
130mA
20mA
For M96 are NC pins
For M96 are NC pins For M96 are NC pins
For M96 are NC pins
For M96 are NC pins
For PX, leave NC when
SBIOS control PWR on/off
L51
BLM18AG121SN1D_0603
VGA@L51
BLM18AG121SN1D_0603
VGA@
12
C420 1U_0402_6.3V4Z
VGA@C420
1U_0402_6.3V4Z
VGA@
1
2
C438 10U_0603_6.3V6M
VGA@C438
10U_0603_6.3V6M
VGA@
1
2
C404 0.1U_0402_16V4Z
VGA@C404
0.1U_0402_16V4Z
VGA@
1
2
C402 10U_0603_6.3V6M
VGA@C402
10U_0603_6.3V6M
VGA@
1
2
C426 10U_0603_6.3V6M
VGA@C426
10U_0603_6.3V6M
VGA@
1
2
L46
BLM18AG121SN1D_0603
VGA@L46
BLM18AG121SN1D_0603
VGA@
12
R178
0_0402_5%
@ R178
0_0402_5%
@
12
C412 0.1U_0402_16V4Z
VGA@C412
0.1U_0402_16V4Z
VGA@
1
2
C432 10U_0603_6.3V6M
VGA@C432
10U_0603_6.3V6M
VGA@
1
2
L44
BLM18AG121SN1D_0603
VGA@L44
BLM18AG121SN1D_0603
VGA@
12
R176
150_0402_1%
R176
150_0402_1%
1 2
C437 1U_0402_6.3V4Z
VGA@C437
1U_0402_6.3V4Z
VGA@
1
2
C414 10U_0603_6.3V6M
VGA@C414
10U_0603_6.3V6M
VGA@
1
2
C417 10U_0603_6.3V6M
VGA@C417
10U_0603_6.3V6M
VGA@
1
2
L37
BLM18AG121SN1D_0603
VGA@L37
BLM18AG121SN1D_0603
VGA@
12
C436 0.1U_0402_16V4Z
VGA@C436
0.1U_0402_16V4Z
VGA@
1
2
C425 1U_0402_6.3V4Z
VGA@C425
1U_0402_6.3V4Z
VGA@
1
2
C416 1U_0402_6.3V4Z
VGA@C416
1U_0402_6.3V4Z
VGA@
1
2
C400 0.1U_0402_16V4Z
VGA@C400
0.1U_0402_16V4Z
VGA@
1
2
C434 0.1U_0402_16V4Z
VGA@C434
0.1U_0402_16V4Z
VGA@
1
2
C396 1U_0402_6.3V4Z
VGA@C396
1U_0402_6.3V4Z
VGA@
1
2
C387 1U_0402_6.3V4Z
VGA@C387
1U_0402_6.3V4Z
VGA@
1
2
GND
216-0729002 A12 M96_BGA962
U5F
MAD@
GND
216-0729002 A12 M96_BGA962
U5F
MAD@
PCIE_VSS#1
AB39
PCIE_VSS#10
J31 PCIE_VSS#11
J34 PCIE_VSS#12
K31 PCIE_VSS#13
K34 PCIE_VSS#14
K39 PCIE_VSS#15
L31 PCIE_VSS#16
L34 PCIE_VSS#17
M34 PCIE_VSS#18
M39 PCIE_VSS#19
N31
PCIE_VSS#2
E39
PCIE_VSS#20
N34 PCIE_VSS#21
P31 PCIE_VSS#22
P34 PCIE_VSS#23
P39 PCIE_VSS#24
R34 PCIE_VSS#25
T31 PCIE_VSS#26
T34 PCIE_VSS#27
T39 PCIE_VSS#28
U31 PCIE_VSS#29
U34
PCIE_VSS#3
F34
PCIE_VSS#30
V34 PCIE_VSS#31
V39 PCIE_VSS#32
W31 PCIE_VSS#33
W34 PCIE_VSS#34
Y34 PCIE_VSS#35
Y39
PCIE_VSS#4
F39 PCIE_VSS#5
G33 PCIE_VSS#6
G34 PCIE_VSS#7
H31 PCIE_VSS#8
H34 PCIE_VSS#9
H39
VSS_MECH#1 A39
VSS_MECH#2 AW1
VSS_MECH#3 AW39
GND#1 A3
GND#10 AA6
GND#100 F13
GND#101
F15 GND#102
F17 GND#103
F19 GND#104
F21 GND#105
F23 GND#106
F25 GND#107
F27 GND#108
F29 GND#109
F31
GND#11 AB12
GND#110
F33 GND#111
F7 GND#112
F9 GND#113
G2 GND#114
G6 GND#115
H9 GND#116
J2 GND#117
J27 GND#118
J6 GND#119
J8
GND#12 AB15
GND#120
K14 GND#121
K7 GND#122
L11 GND#123
L17 GND#124
L2 GND#125
L22 GND#126
L24 GND#127
L6 GND#128
M17 GND#129
M22
GND#13 AB17
GND#130
M24 GND#131
N16 GND#132
N18 GND#133
N2 GND#134
N21 GND#135
N23 GND#136
N26 GND#137
N6 GND#138
R15 GND#139
R17
GND#14 AB20
GND#140
R2 GND#141
R20 GND#142
R22 GND#143
R24 GND#144
R27 GND#145
R6 GND#146
T11 GND#147
T13 GND#148
T16 GND#149
T18
GND#15 AB22
GND#150
T21 GND#151
T23 GND#152
T26 GND#153
U15 GND#154
U17 GND#155
U2 GND#156
U20 GND#157
U22 GND#158
U24 GND#159
U27
GND#16 AB24
GND#160
U6 GND#161
V11 GND#162
V16 GND#163
V18 GND#164
V21 GND#165
V23 GND#166
V26 GND#167
W2 GND#168
W6 GND#169
Y15
GND#17 AB27
GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173
Y24 GND#174
Y27
GND#18 AC11
GND#19 AC13
GND#2 A37
GND#20 AC16
GND#21 AC18
GND#22 AC2
GND#23 AC21
GND#24 AC23
GND#25 AC26
GND#26 AC28
GND#27 AC6
GND#28 AD15
GND#29 AD17
GND#3 AA16
GND#30 AD20
GND#31 AD22
GND#32 AD24
GND#33 AD27
GND#34 AD9
GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18
GND#4 AA18
GND#40 AF21
GND#41 AG17
GND#42 AG2
GND#43 AG20
GND#44 AG22
GND#45 AG6
GND#46 AG9
GND#47 AH21
GND#48 AH29
GND#49 AJ10
GND#5 AA2
GND#50 AJ11
GND#51 AJ2
GND#52 AJ28
GND#53 AJ6
GND#54 AK11
GND#55 AK31
GND#56 AK7
GND#57 AL11
GND#58 AL14
GND#59 AL17
GND#6 AA21
GND#60 AL2
GND#61 AL20
GND#62 AL21
GND#63 AL23
GND#64 AL26
GND#65 AL32
GND#66 AL6
GND#67 AL8
GND#68 AM11
GND#69 AM31
GND#7 AA23
GND#70 AM9
GND#71 AN11
GND#72 AN2
GND#73 AN30
GND#74 AN6
GND#75 AN8
GND#76 AP11
GND#77 AP7
GND#78 AP9
GND#79 AR5
GND#8 AA26
GND#80 AW34
GND#81 B11
GND#82 B13
GND#83 B15
GND#84 B17
GND#85 B19
GND#86 B21
GND#87 B23
GND#88 B25
GND#89 B27
GND#9 AA28
GND#90 B29
GND#91 B31
GND#92 B33
GND#93 B7
GND#94 B9
GND#95 C1
GND#96 C39
GND#97 E35
GND#98 E5
GND#99 F11
GND#175
U13 GND#176
V13
C386 0.1U_0402_16V4Z
VGA@C386
0.1U_0402_16V4Z
VGA@
1
2
L53
BLM18AG121SN1D_0603
VGA@L53
BLM18AG121SN1D_0603
VGA@
12
C421 0.1U_0402_16V4Z
VGA@C421
0.1U_0402_16V4Z
VGA@
1
2
C408 10U_0603_6.3V6M
VGA@C408
10U_0603_6.3V6M
VGA@
1
2
C401 1U_0402_6.3V4Z
VGA@C401
1U_0402_6.3V4Z
VGA@
1
2
C413 1U_0402_6.3V4Z
VGA@C413
1U_0402_6.3V4Z
VGA@
1
2
C398
0.1U_0402_16V4Z
VGA@C398
0.1U_0402_16V4Z
VGA@
1
2
L39
BLM18AG121SN1D_0603
VGA@L39
BLM18AG121SN1D_0603
VGA@
12
C405 1U_0402_6.3V4Z
VGA@C405
1U_0402_6.3V4Z
VGA@
1
2
C435 1U_0402_6.3V4Z
VGA@C435
1U_0402_6.3V4Z
VGA@
1
2
C433 10U_0603_6.3V6M
VGA@C433
10U_0603_6.3V6M
VGA@
1
2
L47
BLM18AG121SN1D_0603
VGA@L47
BLM18AG121SN1D_0603
VGA@
12
C423 10U_0603_6.3V6M
VGA@C423
10U_0603_6.3V6M
VGA@
1
2
L38
BLM18AG121SN1D_0603
VGA@L38
BLM18AG121SN1D_0603
VGA@
12
L43
BLM18AG121SN1D_0603
VGA@L43
BLM18AG121SN1D_0603
VGA@
12
C385 10U_0603_6.3V6M
VGA@C385
10U_0603_6.3V6M
VGA@
1
2
R175
150_0402_1%
R175
150_0402_1%
12
R174
0_0402_5%
VGA@
R174
0_0402_5%
VGA@
12
R402 0_0402_5%
@
R402 0_0402_5%
@
1 2
C419 0.1U_0402_16V4Z
VGA@C419
0.1U_0402_16V4Z
VGA@
1
2
C394
10U_0603_6.3V6M
VGA@C394
10U_0603_6.3V6M
VGA@
1
2
L40
BLM18AG121SN1D_0603
VGA@L40
BLM18AG121SN1D_0603
VGA@
12
C395 0.1U_0402_16V4Z
VGA@C395
0.1U_0402_16V4Z
VGA@
1
2
L36
BLM18AG121SN1D_0603
VGA@L36
BLM18AG121SN1D_0603
VGA@
12
L41
BLM18AG121SN1D_0603
VGA@L41
BLM18AG121SN1D_0603
VGA@
12
C407 1U_0402_6.3V4Z
VGA@C407
1U_0402_6.3V4Z
VGA@
1
2
C418 10U_0603_6.3V6M
VGA@C418
10U_0603_6.3V6M
VGA@
1
2
L45
BLM18AG121SN1D_0603
VGA@L45
BLM18AG121SN1D_0603
VGA@
12
C427 10U_0603_6.3V6M
VGA@C427
10U_0603_6.3V6M
VGA@
1
2
C390 1U_0402_6.3V4Z
VGA@C390
1U_0402_6.3V4Z
VGA@
1
2
C393 1U_0402_6.3V4Z
VGA@C393
1U_0402_6.3V4Z
VGA@
1
2
R177 0_0402_5%
@
R177 0_0402_5%
@
1 2
C397 10U_0603_6.3V6M
VGA@C397
10U_0603_6.3V6M
VGA@
1
2
C429 1U_0402_6.3V4Z
VGA@C429
1U_0402_6.3V4Z
VGA@
1
2
DP PLL POWER
DP A/B POWERDP C/D POWER
DP E/F POWER
U5H
216-0729002 A12 M96_BGA962
MAD@
DP PLL POWER
DP A/B POWERDP C/D POWER
DP E/F POWER
U5H
216-0729002 A12 M96_BGA962
MAD@
DPA_PVDD AU28
DPA_PVSS AV27
DPA_VDD10#1 AP31
DPA_VDD10#2 AP32
NC_DPA_VDD18#1 AN24
NC_DPA_VDD18#2 AP24
DPA_VSSR#1 AN27
DPA_VSSR#2 AP27
DPA_VSSR#3 AP28
DPA_VSSR#4 AW24
DPA_VSSR#5 AW26
DPAB_CALR AW28
DPB_PVDD AV29
DPB_PVSS AR28
DPB_VDD10#1 AN33
DPB_VDD10#2 AP33
NC_DPB_VDD18#1 AP25
NC_DPB_VDD18#2 AP26
DPB_VSSR#1 AN29
DPB_VSSR#2 AP29
DPB_VSSR#3 AP30
DPB_VSSR#4 AW30
DPB_VSSR#5 AW32
DPC_PVDD AU18
DPC_PVSS AV17
DPC_VDD10#1
AP13 DPC_VDD10#2
AT13
NC_DPC_VDD18#1
AP20 NC_DPC_VDD18#2
AP21
DPC_VSSR#1
AN17 DPC_VSSR#2
AP16 DPC_VSSR#3
AP17 DPC_VSSR#4
AW14 DPC_VSSR#5
AW16
DPCD_CALR
AW18
DPD_PVDD AV19
DPD_PVSS AR18
DPD_VDD10#1
AP14 DPD_VDD10#2
AP15
NC_DPD_VDD18#1
AP22 NC_DPD_VDD18#2
AP23
DPD_VSSR#1
AN19 DPD_VSSR#2
AP18 DPD_VSSR#3
AP19 DPD_VSSR#4
AW20 DPD_VSSR#5
AW22
DPE_PVDD AM37
DPE_PVSS AN38
DPE_VDD10#1
AL33 DPE_VDD10#2
AM33
DPE_VDD18#1
AH34 DPE_VDD18#2
AJ34
DPE_VSSR#1
AN34 DPE_VSSR#2
AP39 DPE_VSSR#3
AR39 DPE_VSSR#4
AU37 DPE_VSSR#5
AW35
DPEF_CALR
AM39
NC_DPF_PVDD AL38
NC_DPF_PVSS AM35
DPF_VDD10#1
AK33 DPF_VDD10#2
AK34
DPF_VDD18#1
AF34 DPF_VDD18#2
AG34
DPF_VSSR#1
AF39 DPF_VSSR#2
AH39 DPF_VSSR#3
AK39 DPF_VSSR#4
AL34 DPF_VSSR#5
AM34
C410 0.1U_0402_16V4Z
VGA@C410
0.1U_0402_16V4Z
VGA@
1
2
C389 0.1U_0402_16V4Z
VGA@C389
0.1U_0402_16V4Z
VGA@
1
2
C431 1U_0402_6.3V4Z
VGA@C431
1U_0402_6.3V4Z
VGA@
1
2
C388 10U_0603_6.3V6M
VGA@C388
10U_0603_6.3V6M
VGA@
1
2
C428 0.1U_0402_16V4Z
VGA@C428
0.1U_0402_16V4Z
VGA@
1
2
C411 1U_0402_6.3V4Z
VGA@C411
1U_0402_6.3V4Z
VGA@
1
2
L48
BLM18AG121SN1D_0603
VGA@L48
BLM18AG121SN1D_0603
VGA@
12
L50
BLM18AG121SN1D_0603
VGA@L50
BLM18AG121SN1D_0603
VGA@
12
C399
1U_0402_6.3V4Z
VGA@C399
1U_0402_6.3V4Z
VGA@
1
2
C430 0.1U_0402_16V4Z
VGA@C430
0.1U_0402_16V4Z
VGA@
1
2
R179
150_0402_1%
R179
150_0402_1%
12
C422 1U_0402_6.3V4Z
VGA@C422
1U_0402_6.3V4Z
VGA@
1
2
L52
BLM18AG121SN1D_0603
VGA@L52
BLM18AG121SN1D_0603
VGA@
12
C403 10U_0603_6.3V6M
VGA@C403
10U_0603_6.3V6M
VGA@
1
2
C409 10U_0603_6.3V6M
VGA@C409
10U_0603_6.3V6M
VGA@
1
2
C424 0.1U_0402_16V4Z
VGA@C424
0.1U_0402_16V4Z
VGA@
1
2
C392 0.1U_0402_16V4Z
VGA@C392
0.1U_0402_16V4Z
VGA@
1
2
C391 10U_0603_6.3V6M
VGA@C391
10U_0603_6.3V6M
VGA@
1
2
C415 0.1U_0402_16V4Z
VGA@C415
0.1U_0402_16V4Z
VGA@
1
2
C406 0.1U_0402_16V4Z
VGA@C406
0.1U_0402_16V4Z
VGA@
1
2
L49
BLM18AG121SN1D_0603
VGA@L49
BLM18AG121SN1D_0603
VGA@
12
L42
BLM18AG121SN1D_0603
VGA@L42
BLM18AG121SN1D_0603
VGA@
12

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DQMA#3
QSA#1
QSA#3
QSA3
QSA1
DQMA#1
A_BA0
A_BA1
ODTA0_1
CLKA0#
WEA0#
CKEA0
RASA0#
CASA0#
CSA0#_0
CLKA0
MAA11
MAA9
MAA10
MAA8
MAA7
MAA6
MAA3
MAA4
MAA5
MAA1
MAA2
MAA0
VRAM_RST#
VREFDA_Q2
VREFCA_A2
MAA12
A_BA2
MDA[0..63]
MAA6
DQMA#0
MAA11
CASA1#
MAA5
MAA12
MAA4
MAA1
DQMA#7
A_BA0
MAA2
QSA4
MAA1
MAA0
QSA#2
MAA7
QSA#7
VREFDA_Q3
MAA9
MAA7
MAA0
CLKA1#
A_BA2
VREFDA_Q4
MAA5
RASA1#
MAA11
MAA4
VRAM_RST#
MAA10
MAA12
QSA7
VRAM_RST#
MAA8
DQMA#4
MAA8
A_BA1
DQMA#2
MAA2
MAA0
ODTA1_1
VRAM_RST#
ODTA1_1
MAA4
MAA7
QSA#0
VREFCA_A4
DQMA#6
QSA6
CKEA1
MAA12
MAA3MAA3
A_BA2
MAA10
MAA1
QSA#4
DQMA#5
QSA#5
VREFDA_Q1
MAA9 MAA9
CLKA1
CSA1#_0
MAA10
ODTA0_1
MAA3
MAA2
QSA2
MAA8
QSA#6
MAA11
A_BA1
A_BA0
VREFCA_A1
MAA5
WEA1#
VREFCA_A3
QSA5
MAA6
QSA0
MAA6
MDA18
MDA20
MDA16
MDA19
MDA23
MDA17
MDA21
MDA0
MDA22
MDA4
MDA6
MDA7
MDA2
MDA3
MDA1
MDA5
MDA24
MDA28
MDA29
MDA26
MDA25
MDA30
MDA27
MDA31
MDA13
MDA11
MDA12
MDA9
MDA15
MDA14
MDA10
MDA8
MDA40
MDA35
MDA47
MDA38
MDA32
MDA45
MDA37
MDA46
MDA43
MDA41
MDA34
MDA44
MDA36
MDA33
MDA39
MDA42
MDA63
MDA54
MDA56
MDA55
MDA48
MDA62
MDA57
MDA53
MDA52
MDA58
MDA49
MDA61
MDA60
MDA51
MDA50
MDA59
MAA13 MAA13 MAA13 MAA13
VREFCA_A2 VREFCA_A4 VREFDA_Q4 VREFCA_A1 VREFDA_Q1 VREFDA_Q3VREFCA_A3
CLKA1#
CLKA1CLKA0
CLKA0#
ODTA1
ODTA0
ODTA0_1
ODTA1_1
VREFDA_Q2
MDA[0..63]<17>
VRAM_RST#<17,21>
CLKA0<17>
CLKA0#<17>
CLKA1<17>
CLKA1#<17>
CKEA1<17>
CSA1#_0<17> RASA1#<17> CASA1#<17> WEA1#<17>
A_BA0<17>
A_BA2<17> A_BA1<17>
CKEA0<17>
CSA0#_0<17> RASA0#<17> CASA0#<17> WEA0#<17>
MAA[13..0]<17>
QSA#[7..0]<17>
QSA[7..0]<17>
DQMA#[7..0]<17>
ODTA0<17>
ODTA1<17>
+1.5VSG
+1.5VSG
+1.5VSG +1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG+1.5VSG +1.5VSG+1.5VSG +1.5VSG+1.5VSG
+1.5VSG
+1.5VSG
+1.5VSG+1.5VSG +1.5VSG
+1.5VSG
+1.5VSG
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
20 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
20 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401827
D
SCHEMATIC, MB A5911
Custom
20 55Tuesday, September 14, 2010
2009/7/14 2010/03/12
Compal Electronics, Inc.
VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
Pull high for Madison and Park...
C442
0.1U_0402_16V4Z
VGA@
C442
0.1U_0402_16V4Z
VGA@
1
2
R194 0_0402_5%
VGA@
R194 0_0402_5%
VGA@ 12
C448 1U_0402_6.3V6K
VGA@C448
1U_0402_6.3V6K
VGA@
1
2
R189
4.99K_0402_1%
VGA@
R189
4.99K_0402_1%
VGA@
12
C455 1U_0402_6.3V6K
VGA@C455
1U_0402_6.3V6K
VGA@
1
2
C470
10U_0603_6.3V6M
VGA@C470
10U_0603_6.3V6M
VGA@
1
2
C456 1U_0402_6.3V6K
VGA@C456
1U_0402_6.3V6K
VGA@
1
2
C464 1U_0402_6.3V6K
VGA@C464
1U_0402_6.3V6K
VGA@
1
2
R200
4.99K_0402_1%
VGA@
R200
4.99K_0402_1%
VGA@
12
R192 0_0402_5%
VGA@
R192 0_0402_5%
VGA@ 12
R202
4.99K_0402_1%
VGA@
R202
4.99K_0402_1%
VGA@
12
R198
4.99K_0402_1%
VGA@
R198
4.99K_0402_1%
VGA@
12
C440
0.1U_0402_16V4Z
VGA@
C440
0.1U_0402_16V4Z
VGA@
1
2
R190 56_0402_1%
VGA@
R190 56_0402_1%
VGA@
1 2
C447 1U_0402_6.3V6K
VGA@C447
1U_0402_6.3V6K
VGA@
1
2
R180
243_0402_1%
VGA@R180
243_0402_1%
VGA@
12
R196
4.99K_0402_1%
VGA@
R196
4.99K_0402_1%
VGA@
12
R182
243_0402_1%
VGA@R182
243_0402_1%
VGA@
12
R195 56_0402_1%
VGA@
R195 56_0402_1%
VGA@
1 2
R204
56_0402_1%
VGA@R204
56_0402_1%
VGA@
1 2
C454 1U_0402_6.3V6K
VGA@C454
1U_0402_6.3V6K
VGA@
1
2
C461 1U_0402_6.3V6K
VGA@C461
1U_0402_6.3V6K
VGA@
1
2
C465 1U_0402_6.3V6K
VGA@C465
1U_0402_6.3V6K
VGA@
1
2
R184
4.99K_0402_1%
VGA@
R184
4.99K_0402_1%
VGA@
12
C467 0.01U_0402_25V7K
VGA@C467
0.01U_0402_25V7K
VGA@
1
2
R183
243_0402_1%
VGA@R183
243_0402_1%
VGA@
12
R193
4.99K_0402_1%
VGA@
R193
4.99K_0402_1%
VGA@
12
C469
10U_0603_6.3V6M
VGA@C469
10U_0603_6.3V6M
VGA@
1
2
96-BALL
SDRAM DDR3
U9
K4B1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
U9
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3 CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7 CK
K7
DQSU
B7
BA0
M2 BA1
N8
A2
P3 A3
N2 A4
P8 A5
P2 A6
R8 A7
R2 A8
T8 A9
R3 A10/AP
L7 A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1 NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3 A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3 A14
T7 A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C471
10U_0603_6.3V6M
VGA@C471
10U_0603_6.3V6M
VGA@
1
2
C451 1U_0402_6.3V6K
VGA@C451
1U_0402_6.3V6K
VGA@
1
2
R181
243_0402_1%
VGA@R181
243_0402_1%
VGA@
12
96-BALL
SDRAM DDR3
U11
K4B1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
U11
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3 CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7 CK
K7
DQSU
B7
BA0
M2 BA1
N8
A2
P3 A3
N2 A4
P8 A5
P2 A6
R8 A7
R2 A8
T8 A9
R3 A10/AP
L7 A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1 NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3 A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3 A14
T7 A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C445
0.1U_0402_16V4Z
VGA@
C445
0.1U_0402_16V4Z
VGA@
1
2
C472
10U_0603_6.3V6M
VGA@C472
10U_0603_6.3V6M
VGA@
1
2
R205
56_0402_1%
VGA@R205
56_0402_1%
VGA@
1 2
C453 1U_0402_6.3V6K
VGA@C453
1U_0402_6.3V6K
VGA@
1
2
C459 1U_0402_6.3V6K
VGA@C459
1U_0402_6.3V6K
VGA@
1
2
C441
0.1U_0402_16V4Z
VGA@
C441
0.1U_0402_16V4Z
VGA@
1
2
C463 1U_0402_6.3V6K
VGA@C463
1U_0402_6.3V6K
VGA@
1
2
C458 1U_0402_6.3V6K
VGA@C458
1U_0402_6.3V6K
VGA@
1
2
C449 1U_0402_6.3V6K
VGA@C449
1U_0402_6.3V6K
VGA@
1
2
R187
4.99K_0402_1%
VGA@
R187
4.99K_0402_1%
VGA@
12
C443
0.1U_0402_16V4Z
VGA@
C443
0.1U_0402_16V4Z
VGA@
1
2
C466 1U_0402_6.3V6K
VGA@C466
1U_0402_6.3V6K
VGA@
1
2
C468
10U_0603_6.3V6M
VGA@C468
10U_0603_6.3V6M
VGA@
1
2
R185
4.99K_0402_1%
VGA@
R185
4.99K_0402_1%
VGA@
12
C450 1U_0402_6.3V6K
VGA@C450
1U_0402_6.3V6K
VGA@
1
2
96-BALL
SDRAM DDR3
U12
K4B1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
U12
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3 CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7 CK
K7
DQSU
B7
BA0
M2 BA1
N8
A2
P3 A3
N2 A4
P8 A5
P2 A6
R8 A7
R2 A8
T8 A9
R3 A10/AP
L7 A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1 NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3 A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3 A14
T7 A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
C444
0.1U_0402_16V4Z
VGA@
C444
0.1U_0402_16V4Z
VGA@
1
2
C457 1U_0402_6.3V6K
VGA@C457
1U_0402_6.3V6K
VGA@
1
2
C475
10U_0603_6.3V6M
VGA@C475
10U_0603_6.3V6M
VGA@
1
2
R207
56_0402_1%
VGA@R207
56_0402_1%
VGA@
1 2
R206
56_0402_1%
VGA@R206
56_0402_1%
VGA@
1 2
C473
10U_0603_6.3V6M
VGA@C473
10U_0603_6.3V6M
VGA@
1
2
C452 1U_0402_6.3V6K
VGA@C452
1U_0402_6.3V6K
VGA@
1
2
C439
0.1U_0402_16V4Z
VGA@
C439
0.1U_0402_16V4Z
VGA@
1
2
R199
4.99K_0402_1%
VGA@
R199
4.99K_0402_1%
VGA@
12
96-BALL
SDRAM DDR3
U10
K4B1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
U10
K4B1G1646E-HC12_FBGA96
X76@
WE
L3
RAS
J3 CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7 CK
K7
DQSU
B7
BA0
M2 BA1
N8
A2
P3 A3
N2 A4
P8 A5
P2 A6
R8 A7
R2 A8
T8 A9
R3 A10/AP
L7 A11
R7
DQL0 E3
DQL1 F7
DQL2 F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7 H7
VSSQ D1
VSS A9
VSS E1
VSS B3
NC/ODT1
J1
VDD B2
VDD D9
VDDQ A1
VDDQ A8
VDDQ C1
VDDQ C9
NC/CS1
L1 NC/CE1
J9
VDDQ E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3 DML
E7
VSSQ B1
VSSQ B9
VSSQ D8
VSSQ E2
DQSU
C7
VSSQ E8
DQSL
G3
VDDQ F1
VSSQ F9
VSSQ G1
VDDQ H2
VDDQ H9
VSSQ G9
VREFCA
M8
VSS G8
VDD G7
ODT/ODT0
K1
A0
N3 A1
P7
VDD K2
A12
N7
VSS J2
VDD K8
DQU1 C3
DQU2 C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
DQU0 D7
A13
T3 A14
T7 A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD N1
VDD N9
VDD R1
VDD R9
VSS J8
VSS M1
VSS M9
VSS P1
VSS P9
VSS T1
VSS T9
VDDQ D2
R203
4.99K_0402_1%
VGA@
R203
4.99K_0402_1%
VGA@
12
R197
4.99K_0402_1%
VGA@
R197
4.99K_0402_1%
VGA@
12
R201
4.99K_0402_1%
VGA@
R201
4.99K_0402_1%
VGA@
12
C474
10U_0603_6.3V6M
VGA@C474
10U_0603_6.3V6M
VGA@
1
2
C476 0.01U_0402_25V7K
VGA@C476
0.01U_0402_25V7K
VGA@
1
2
R191
4.99K_0402_1%
VGA@
R191
4.99K_0402_1%
VGA@
12
C460 1U_0402_6.3V6K
VGA@C460
1U_0402_6.3V6K
VGA@
1
2
C462 1U_0402_6.3V6K
VGA@C462
1U_0402_6.3V6K
VGA@
1
2
R188
4.99K_0402_1%
VGA@
R188
4.99K_0402_1%
VGA@
12
C446
0.1U_0402_16V4Z
VGA@
C446
0.1U_0402_16V4Z
VGA@
1
2
R186
4.99K_0402_1%
VGA@
R186
4.99K_0402_1%
VGA@
12