Corelis PCIe-1149.1 User manual

CORELIS
PCIe-1149.1
PCIe-1149.1
High-Speed PCI Express Bus
Boundary-Scan Controller
User’s Manual
Document Part Number: 70369 REV B
Copyright 2006 - 2007 Corelis Inc.
12607 Hidden Creek Way
Cerritos, CA 90703-2146
Telephone: [phone] • Fax: [phone]

i
Preface
PRINTING HISTORY
New editions are complete revisions of the manual. Update packages, which are issued between
editions, contain additional and replacement pages to be merged into the manual by the customer.
The dates on the title page change only when a new edition is published.
A software code may be printed before the date; this indicates the version of the software product at
the time the manual or update was issued. Many product updates and fixes do not require manual
changes and, conversely, manual corrections may be done without accompanying product changes.
Therefore, do not expect a one to one correspondence between product updates and manual
updates.
Revision A, September 2006
Revision B, November 2007
GENERAL NOTICE
Information contained in this document is subject to change without notice. CORELIS shall not be
liable for errors contained herein for incidental or consequential damages in connection with the
furnishing, performance, or use of material contained in this manual. This document contains
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document may be reproduced or translated to other languages without the prior written consent of
CORELIS.
CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is
not furnished by CORELIS.
ENVIRONMENTAL NOTICE
This product must be disposed of in accordance with the WEEE directive.
TRADEMARK NOTICE
Windows is a registered trademark of Microsoft Corporation.
Other products and services named in this book are trademarks or registered trademarks of their
respective companies. All trademarks and registered trademarks in this book are the property of
their respective holders.

ii
PRODUCT WARRANTY
This CORELIS product has a warranty against defects in material and workmanship for a period of
90 days from date of shipment. During the warranty period, CORELIS will, at its option, either
repair or replace products that prove to be defective.
For warranty service or repair, this product must be returned to a service facility designated by
CORELIS. Outside CORELIS service travel areas, warranty service will be performed at the
Buyer's facility only upon CORELIS' prior agreement and Buyer shall pay CORELIS' round trip
travel expenses.
For products returned to CORELIS for warranty service, the Buyer shall prepay shipping charges to
CORELIS and CORELIS shall pay shipping charges to return the product to the Buyer. However,
the Buyer shall pay all shipping charges, duties, and taxes for products returned to CORELIS from
another country.
CORELIS warrants that its software and firmware designated by CORELIS for use with an
instrument will execute its programming instructions when properly installed on that instrument.
CORELIS does not warrant that the operation of the instrument, software, or firmware will be
uninterrupted or error-free.
The foregoing warranty shall not apply to defects resulting from improper or inadequate
maintenance by the Buyer, Buyer-supplied software or interfacing, unauthorized modification or
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NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. CORELIS SPECIFICALLY
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number will be forwarded to the customer either directly or through its authorized sales
representative.

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Table of Contents
CHAPTER 1 PRODUCT OVERVIEW..........................................................................1-1
Introduction................................................................................................................................................1-1
What Is IEEE Standard 1149.1? ................................................................................................................1-2
Features of the PCIe-1149.1 ......................................................................................................................1-3
Adjustable Voltage Interfaces................................................................................................................................ 1-4
Parallel Input/Output Ports.................................................................................................................................... 1-4
PCI Express Interface............................................................................................................................................ 1-4
Programmable Clocks............................................................................................................................................ 1-5
Features of the ScanTAP-4........................................................................................................................1-5
PCIe-1149.1 Specifications........................................................................................................................1-6
ScanTAP-4 Specifications .........................................................................................................................1-7
CHAPTER 2 PCIE-1149.1 INSTALLATION ................................................................2-1
Software Installation First! ........................................................................................................................2-2
Hardware Installation.................................................................................................................................2-2
Hardware Installation.................................................................................................................................2-3
CHAPTER 3 CONNECTING TO THE TARGET..........................................................3-1
Connecting to the Target............................................................................................................................3-1
20-Pin ScanTAP Connector.......................................................................................................................3-3
68-pin Host Connector...............................................................................................................................3-4
PCIe-1149.1 Parallel I/O Connectors.........................................................................................................3-5
CHAPTER 4 USING PCIE-1149.1 WITH SCANPLUS ................................................4-1
Hardware Setup..........................................................................................................................................4-1
Using PCIe-1149.1 with ScanPlus Tools...................................................................................................4-1
ScanTAP-4 TAP Configuration.................................................................................................................4-5
TAP Configuration - Method 1..................................................................................................................4-6
TAP Configuration - Method 2..................................................................................................................4-8
TAP Configuration - Method 3..................................................................................................................4-9
Gang Programming with ScanPlus Runner .............................................................................................4-13
Gang Programming with ScanPlus Flash Programmer............................................................................4-20
CHAPTER 5 THIRD PARTY APPLICATION INTERFACE.........................................5-1
Using PCIe-1149.1 with ScanPlus Runner Command-line .......................................................................5-1
APPENDIX A RECOMMENDED TARGET CONNECTORS ..........................................1
10-pin TAP Connector..................................................................................................................................1
Flash Programming TAP Connector.............................................................................................................4
20-pin TAP Connector..................................................................................................................................7

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APPENDIX B SELF TEST UTILITY SOFTWARE..........................................................1
Self-Test........................................................................................................................................................1

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Table of Figures
Figure 1-1. The Corelis PCIe-1149.1 Boundary-Scan Controller ........................................................................... 1-1
Figure 1-2. Test Access Port (TAP).......................................................................................................................... 1-2
Figure 1-3. PCIe-1149.1 Block Diagram................................................................................................................. 1-3
Figure 3-1. ScanTAP-4 20-pin TAP Header Connectors (top view) ........................................................................ 3-1
Figure 4-1. Controller Configuration Screen........................................................................................................... 4-1
Figure 4-2. PCIe-1149.1 Setup Screen (but ScanTAP-4 not connected).................................................................. 4-2
Figure 4-3. Successful PCIe-1149.1 With ScanTAP Setup Screen........................................................................... 4-3
Figure 4-4. Advanced Configuration Setup Screen.................................................................................................. 4-4
Figure 4-5. Controller Configuration TAP Configuration Options.......................................................................... 4-6
Figure 4-6. Typical ScanPlus Runner Test Plan ...................................................................................................... 4-9
Figure 4-7. ScanPlus Runner Pop-up Menu........................................................................................................... 4-10
Figure 4-8. Infrastructure Test Options Dialog Box.............................................................................................. 4-11
Figure 4-9. Available ScanTAP-4 Configuration................................................................................................... 4-12
Figure 4-10. ScanPlus Runner Test Plan for Gang Programming......................................................................... 4-14
Figure 4-11. ScanPlus Runner Pop-up Menu......................................................................................................... 4-15
Figure 4-12. Infrastructure Test Options Dialog Box............................................................................................ 4-16
Figure 4-13. Available ScanTAP-4 TAP Configuration......................................................................................... 4-17
Figure 4-14. Available ScanTAP-4 TAP Configuration for .fpi files...................................................................... 4-18
Figure 4-15. ScanPlus Flash Programmer Gang Programming Window.............................................................. 4-20
Figure A-1. Standard TAP connector (top view)..........................................................................................................1
Figure A-2. TAP Connector Schematic ........................................................................................................................3
Figure A-3. Boundary-scan Flash Programming 16 Pin TAP Connector (top view)...................................................4
Figure A-4. Flash Programming TAP Connector Schematics......................................................................................6
Figure A-5. Boundary-scan Flash Programming 20-Pin TAP Connector (top view) ..................................................7
Figure A-6. 20-pin TAP Connector Schematic for SPI................................................................................................10
Figure A-7. 20-pin TAP Connector Schematic for I2C ...............................................................................................11
Figure B-1. Self-Test Result for the PCIe-1149.1 when the ScanTAP-4 is NOT connected.........................................2
Figure B-2. Self-Test Results for the PCIe-1149.1 with the ScanTAP-4 Connected.....................................................3

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Table of Tables
Table 1-1. Programmable TCK Frequencies............................................................................................................ 1-5
Table 1-2. ScanTAP-4 DC Characteristics............................................................................................................... 1-7
Table 1-3. ScanTAP-4 SPI Interface DC Characteristics......................................................................................... 1-8
Table 1-4. ScanTAP-4 I2C Interface DC Characteristics ........................................................................................ 1-9
Table 3-1. ScanTAP-4 TAP Pin Assignment............................................................................................................. 3-3
Table 3-2. 68-Pin SCSI type Cable Parts ................................................................................................................. 3-4
Table 3-3. Connector P2 Parallel Output Pin Assignment....................................................................................... 3-5
Table 3-4. Connector P1 Parallel Input Pin Assignment......................................................................................... 3-6
Table 4-1. ScanPlus Runner ScanTAP-4 Configuration........................................................................................... 4-7
Table 4-2. ScanPlus Runner Naming Conventions.................................................................................................... 4-8
Table 4-3. ScanPlus Runner Naming Conventions for Gang Programming........................................................... 4-13
Table 4-4. ScanPlus Runner ScanTAP-4 Configuration......................................................................................... 4-19
Table 5-1. PCIe-1149.1 Controller Parameters....................................................................................................... 5-2
Table A-1. Signal Description and Termination...........................................................................................................2
Table A-2. Standard 10-Pin TAP Connector................................................................................................................2
Table A-3. Flash Programming TAP 16 Pin Connector...............................................................................................5
Table A-4. Signal Description and Termination...........................................................................................................5
Table A-5. Flash Programming TAP 16 Pin Connector...............................................................................................8
Table A-6. Signal Description and Termination...........................................................................................................9

Product Overview 1-1
Chapter 1
Product Overview
Introduction
The PCIe-1149.1 High-Speed PCI Express Bus boundary-scan controller is a member of the Corelis
ScanExpress™ family of high performance scan-based test, analysis, and diagnostic tools. The
PCIe-1149.1 High-Speed PCI Express (PCIe) Bus Boundary-Scan Controller card, with memory-
behind-the-pin architecture, interfaces between a host computer and any IEEE Standard 1149.1
compatible target. The PCIe-1149.1 is designed to control the operation of an IEEE Standard
1149.1 boundary-scan test path by generating the proper signals under software control to interface
with the target system. It also supports remote operation of multiple boundary-scan (JTAG) Test
Access Ports (TAPs) using any of the Corelis ScanTAP family of Multiple TAP Intelligent pods such
as the ScanTAP-4, ScanTAP-8 or ScanTAP-32. The PCIe-1149.1 is shown in Figure 1-1.
Figure 1-1. The Corelis PCIe-1149.1 Boundary-Scan Controller
The most popular Intelligent Pod is the ScanTAP-4. It connected to the PCIe-1149.1 card via a
standard SCSI-II cable and it provides up to 4 independent TAP connectors with a programmable
low-voltage-compatible interface. Each of the 4 TAP connectors contains direct access to JTAG,
I2C and SPI interfaces. It also supports simultaneous programming and verification of Flash
memory devices at continuous scan clock (TCK) speeds of up to 80 MHz. The ScanTAP pods
include direct hardware compare of expected scan results and are therefore especially suitable for
gang (parallel) testing and programming of units under test (UUTs).

The PCIe-1149.1 facilitates software-controlled boundary-scan operations per IEEE Standard
1149.1. It provides command access to the target’s Test Access Port (TAP), to verify PCB
interconnects, perform functional testing, and debug without manual probing. Furthermore, the
JTAG interface gives access to internal device functions that are not accessible via external probing,
enabling fault isolation within the device itself. The JTAG interface also enables programming
target Flash and CPLD devices, as well as downloading and uploading of data blocks to and from
various storage devices. Application software for the PCIe-1149.1 is sold separately.
What Is IEEE Standard 1149.1?
The IEEE Standard 1149.1 test bus and boundary-scan architecture enable control of an IC, board,
or system, via a standard four-signal interface. Each IEEE Standard 1149.1-compliant IC
incorporates a feature known as boundary-scan, which ensures that a JTAG controller can control
and observe each functional pin of the IC via the four-wire interface. A controller can load test,
debug, or initialization patterns serially into the appropriate IC(s) via the IEEE Standard 1149.1 test
bus. Thus, even with limited physical access, a user can observe or control IC, board, or system
functions.
Two main elements comprise the IEEE Standard 1149.1 test bus: a Test Access Port (TAP), which
interfaces internal IC logic with the external world via a four-signal (optionally five-signal) bus as
shown in Figure 1-2,and a boundary-scan architecture, which defines standard boundary cells that
drive and receive data at the IC pins. IEEE Standard 1149.1 also defines both mandatory and
optional opcodes and test features. The test bus signals are: Test Clock (TCK), Test Mode Select
(TMS), Test Data In (TDI), Test Data Out (TDO), and the optional Test Logic Reset (TRST).
The IEEE-1149.1 Test Access Port
Interface (TAP) consists of four
required signals:
Test Mode Select (TMS)
Test Clock (TCK)
Test Data In (TDI)
Test Data Out (TDO)
A fifth signal is defined as optional:
Test Reset (TRST*)
TMS
TCK
TDI
TDO
TRST*
T
A
P
Figure 1-2. Test Access Port (TAP)
1-2 Product Overview