Corvus systems Corvus Concept User manual

LIMITED WARRANTY
CORVUS SYSTEMS, Inc. warrants all its hardware and software for a perio<;i of 180 days from
the date of purchase from any authorized
Corvus Dealer. Should the product fail to be in good
working order at any time during this period, Corvus Systems will, at its option, repair
or replace
this product at no additional charge except as set forth below. Repairs will be performed
and non-
functioning
parts replaced either with new or reconditioned components to'make the product
function according to company standards and specifications. All replaced parts become the prop-
erty of Corvus Systems,
Inc. This limited warranty does not include service to repair damage to the
product resulting from accident, disaster, misuse, abuse or modifications that are unapproved by
Corvus Systems.
Limited Warranty service may
be obtained by delivering the product during the 180 day war-
ranty period to
Corvus Systems with proof of purchase date. YOU MUST CONTACT CORVUS
CUSTOMER SERVICE TO OBTAIN A "RETURN MERCHANDISE AUTHORIZATION"
PRIOR TO RETURNING THE PRODUCT. THE RMA (RETURN MERCHANDISE AUTHORI-
ZATION) NUMBER ISSl,JED
BY CORVUS CUSTOMER SERVICE MUST APPEAR ON THE
EXTERIOR OF THE SHIPPING CONTAINER. ONLY ORIGINAL OR EQUIVALENT SHIPPING
MATERIALS MUST BE USED. If this product is delivered by mail, you agree to insure the prod-
uct
or assume the risk of loss or damage in transit, to prepay shipping charges to the warranty
service location
and to use the original shipping container. Contact Corvus Systems or write to
the Corvus Systems Service Center, 2029 O'Toole, San
Jose, CA 95131 prior to shipping equipment
ALL EXPRESSED AND IMPLIED WARRANTIES FOR THIS PRODUCT INCLUDING THE
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
LIMITED IN DURATION TO A PERIOD OF 180
DAYS FROM DATE OF PURCHASE, AND NO
WARRANTIES, WHETHER EXPRESSED OR IMPLIED WILL APPLY AFTER THIS PERIOD.
SOME STATES
DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WAR-
RANTY LASTS, SO THE ABOVE LIMITATIONS
MAY NOT APPLY TO YOU.
IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED ABOVE, YOUR
SOLE
REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE. IN NO
EVENT WILL CORVUS SYSTEMS BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING
ANY LOST PROFITS, LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL
DAMAGES ARISING OUT OF THE USE OF OR INABILITY TO USE SUCH PRODUCT, EVEN
IF CORVUS SYSTEMS OR AN AUTHORIZED CORVUS SYSTEMS DEALER HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY:CLAIM
BY ANY
OTHER PARTY.
SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS, SO THE
ABOVE LIMITATIONS
OR EXCLUSIONS
MAY NOT APPLY TO YOU. '
THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU MAY ALSO HAVE
OTHER RIGHTS WHICH MAY VARY FROM STATE TO STATE.
FCC WARNING
This equipment generates, uses, and can radiate radio frequency energy and if not installed and
used in accordance with the instruction manual, may cause interference to radio communications.
As temporarily permitted
by regulation it has not been tested for compliance'with the limits for
Class A computing devices pursuant to Subpart J of Part 15 of FCC Rules, which are designed to .
provide reasonable protection against such interference in which case the user at his
own expense
will
be required to take whatever measures may be needed to correct the interference.
NOTICE
Corvus Systems, Inc. reserves the right to inake changes in the product described in this manual
at any time without notice. Revised manuals will
be published as needed and may be purchased
from authorized
Corvus Dealers.
This manual is copyrighted
and contains proprietary information. All rights re~erved. This docu-
ment may not, in whole
or in part be copied, photocopied, reproduced, translated, or reduced to
any electronic medium
or machine readable form without prior consent, in writing, from Corvus
Systems, Inc.
CORVUS SYSTEMS
2029 O'Toole Avenue
San Jose, CA 95131
Telephone: [phone]
TELEX: 278976
Copyright
©1983 by Corvus Systems, Inc.
The Corvus Concept,'" Transporter,
TW Corvus OMNINET,N Corvus Logicalc,'W Time Travel Editing,'W
EdWord,'" Constellation,N Corvus,N Corvus Systems,N Personal Workstation,N Tap Box/w Passive
Tap Box/wand Omninet Unifw are trademarks of Corvus Systems, Inc.
MIRROR® is a registered Corvus Systems trademark. Patented.

PART NO.: 7100-04701
DOCUMENT NO.: CCC/30-01l1.1
RELEASE DATE: April, 1983
CORVUS DEALER SERVICE
CORVUS SYSTEMS
CONCEPT
PERSONAL WORKSTATION
SERVICE MANUAL
This document contains three types of notations. These are, in increasing order of importance.
NOTE, CAUTION, and WARNING. The NOTE indicates some action to be taken to speed or
simplify a procedure. The CAUTION indicates that potential damage to the equipment or user
data exists, and care should be taken to avoid this. The WARNING indicates that potential
harm or injury to the service technician or operator exists, and extreme care should be taken to
avoid these.

CORVUS DEALER SERVICE
TABLE OF CONTENTS
iii

Ball'" is a trademark of Ball Inc.
Selectric'" is a
trademark of IBM Corp.
ACIDC" is a trademark of AC/DC Inc.
Tandon" is a trademark of Tandon Corp.
MACSbug'" is a
trademark of Motorola Corp.
Synertek" is a trademark of Synertek
Moss Technology is a trademark of Moss Technologies Inc.
Rockwell International is a
trademark of Rockwell International Corp.
iv

CORVUS DEALER SERVICE
TABLE OF CONTENTS
CHAPTER 1-0VI~RVIEW
1.0 Scope of Chapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
1.1 Concept Mlodules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
1.1.1 Electronics Tray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
1.1.1.1 Processor Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
1.1.1.2 Memory Board. . .. ..... . .. ........ ... ...... ......... .. .. . ..... .. . . .. .. .. 4
1.1.2 Video Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4
1.1.3 I<eyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4
1.1.4 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4
1.2 Concept Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.2.1 Operating System Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.2.2 Floppy Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.2.3 Winchester Disk Drive Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.2.4 Archival and Back-Up Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
1.2.5 Network Option. .. . . . .. . . .. .. .. ... ... ..... ... ..... .. . . ........ .. ... . .. . .. ... .. . .. 5
CHAPTER 2-FUNCTIONAL DESCRIPTION
2.0 Scope of Chapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
2.1 C:oncept Processor Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
2:.1.1 Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
2:.1.2 Bus Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
2:.1.3 Memory Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
2 .. 1.4 ROMs and Static RAM ............................................................. 10
2 .. 1.5 OMNINET ....................................................................... 11
2:.1.6 50-Pin I/O Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12
2:.1.7 Data Communication Ports ......................................................... 13
2 .. 1.8 Interrupts ........................................................................ 14
2.1.9 Memory Arbitration ............................................................... 15
2 .. 1.10 Calendar ......................................................................... 16
2.1.11 Bell, Timer, and VIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.12 Data Acknowledge ................................................................ 16
2.2 Concept Mlemory Board ...................................................................... 17
2.2.1 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.2 Horizontal Timing ................................................................. 17
2.2.3 Vertical Timing .................................................................... 18
2.2.4 RAM Timing ...................................................................... 18
2.2.5 Memory Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.6 Video Address Counter ............................................................ 18
2.2.7 Memory Multiplexing .............................................................. 18
2.2.8 Memory Array .................................................................... 18
2.2.9 Memory Buffers ................................................................... 19
2.2.10 Video Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CHAPTER 3-DISASSEMBLY
3.0 Scope of Chapter ............................................................................ 23
3.1 Installation ................................................................................. 23
3.2 Visual Inspection ............................................................................ 23
3.3 Video Monitor Removal and Disassembly .................................... , .................. 23
3.4 Keyboard Disassembly and Cleaning ........................................................... 24
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CORVUS DEALER SERVICE
3.5 Electronics Tray Disassembly and Assembly ..................................................... 24
3.6
Power Supply Removal ...................................................................... 25
CHAPTER
4-ADJUSTMENTS
4.0 Scope of Chapter ............................................................................ 29
4.1 Concept Power Supply Adjustments ........................................................... 29
4.2
Preparations for Video Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 Video Alignment and Adjustment ............................................................. 30
CHAPTER 5- TROUBLESHOOTING
5.0 Scope
of Chapter ............................................................................ 37
5.1 Levell Troubleshooting ...................................................................... 37
5.1.1 Video Monitor .................................................................... 37
5.1.2 Power Supply ..................................................................... 39
5.1.3
Power-On Self Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.4 Self Test Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.5 Boot Problems .................................................................... 42
5.2 Level 2 Troubleshooting
...................................................................... 44
5.2.1 MACSbug Installation
Procedures ................................................... 44
5.2.2 Communicating with MACSbug ..................................................... 46
5.2.3
Operating Procedures .............................................................. 46
5.2.4 MACSbug Routines
................................................................ 47
5.3 Component Level Troubleshooting ............................................................ 47
5.3.1
Proc~ssor Signal Descriptions ....................................................... 47
5.3.2
Processor Test Points .............................................................. 47
5.3.3
Memory and Video Controller Test Points ............................................ 50
Appendix A: Schematics and Assembly Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
A-I Revision 03 Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A-2 Revision 04 Schematics
.......................................................... 61
A-3 Assembly Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix B:
Troubleshooting Flow Chart ......................................................... 83
Appendix C:
Test Point Signals ................................................................... 89
C-1 Processor Board Signals ......................................................... 90
C-2 Memory Board Signals .......................................................... 95
Appendix 0:
Timing Charts ...................................................................... 99
0-1 Processor Board Timing Charts .................................................. 101
0-2 Memory Board Timing Charts ................................. , ................. 104
Appendix E:
MACSbug ........................................................................ 107
E-1 MACSbug Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
E-2 MACSbug Routines ............................................................ 111
E-3 Self Test
Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Appendix F: Maps ........... ~ ................................................................. 123
F-1 General Memory and 110 Maps .................................................. 125
F-2 ROM
Mapping of I/O Slots ...................................................... 129
F-3 VIA
General Purpose 110 Ports .................................................. 131
F-4
OMNINET .................................................................... 135
F-5
Clock/Calendar/ ALTMAP/Volume ............................................... 139
F-6 Data
Communication and Keyboard Registers ..................................... 143
Appendix G: Memory Board Jumper Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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CORVUS DEALER SERVICE
Appendix H:
Connector Descriptions ............................................................. 153
H-l 50-Pin I/O SLOT Description .................................................... 155
H-2 Data
Communication Ports Jl and J2 .............................................. 157
H-3 Board
Connectors J4, J5, and J6 ................................................... 161
H-4 Additional
Connectors .......................................................... 165
Appendix I:
Concept Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
AppendixJ: Specifications ...................................................................... 173
LIST OF ILLUSTRATIONS AND TABLES
ILLUSTRATIONS
Figure Page
1
Concept Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
2 Motorola MC68000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 9
3
Memory Mapper ............................................................................ 10
4 ROM and Static RAM Sockets ................................................................ 11
5 ADLC ..................................................................................... 12
6 Data Acknowledge Timing
................................................................... 16
7 Horizontal Timing Circuit .................................................................... 17
8
Concept Rear View .......................................................................... 23
9 Latch Screws
............................................................................... 24
10 Electronics Tray Power Connections ........................................................... 24
11
Concept Power Supply Voltage Adjustments ................................................... 29
12 CRT
Adjustment Yoke ....................................................................... 31
13 Horizontal and Vertical PCA .................................................................. 31
14 Video PC:A ................................................................................. 32
15
CORCOM Setting ........................................................................... 38
16
Monitor Voltage Test Points .................................................................. 39
17 Rev 03 Boot Switch Settings
.................................................................. 43
18 Rev 04 Boot Switch Setting ................................................................... 43
19 Rev 03 ROM
and RAM Locations .............................................................. 45
20 Rev 04 ROM and RAM Locations .............................................................. 45
TABLES
Table Page
1
I/O Address Space .......................................................................... 12
2
I/O Slot Pin Descriptions ..................................................................... 13
3
Interrupt Levels ............................................................................. 14
4
Processor Board Test Points .................................................................. 48
5
Memory and Timing Signal Locations .......................................................... 50
vii

CORVUS DEALER SERVICE
CHAPTER 1
OVERVIEW
1
------------------_._----------_ .. __ ._.

CORVUS DEALER SERVICE
CHAPTER 1
OVERVIEW
1.0 Scope of Chapter
The Corvus Concepf
M
Personal WorkstationTM is designed with service in mind. Its modular components can be
substituted during on-site servicing to minimize system down time. These modules are outlined in this chapter.
Options available to enhance the Concept are also discussed.
1.1
Concept Modules
The Concept base contains a power supply, fan, and removable electronics tray. This tray contains the Processor
Board, the Memory Board, speaker, and calendar battery. The modular design of the Concept allows easy access
and replacement of the electronic subassemblies.
1111111111111111111111111111111111111
Base
Bifurcated
Cable Keyboard
1.1.1 Electronics Tray
The
entire tray may be removed for replacement when an immediate repair is required. The Processor Board and
Memory Board may be individually substituted if time permits additional troubleshooting.
1.1.1.1 Processor Board
A Motorola
YM MC68000 Microprocessor, Boot RAMs and ROMs, OMNINET, YM and Clock Calendar are the major
components of the Processor Board. I/O circuitry is also resident on the Processor Board. Specific features include:
Microprocessor
• Motorola MC68000
• 16/32-bit
data registers
• 24-bit memory address bus
• 16-bit data bus
Input/Output
• OMNINET Network interface
• Two serial asynchronous I/O ports
• Clock and calendar backup battery
• Flexible sound generator
• Two interval timers
• Four 50-pin I/O slots
3

CORVUS DEALER SERVICE
1.1.1.2 Memory Board
The
Memory Board provides a sophisticated scheme which produces both memory timing and video timing. The
Memory Board includes:
• 256 Kbytes standard or 512 Kbytes optional memory
• Vertical and horizontal timing
• RAM timing
• Memory addressing
• Video interface
• System master clock
The 256
or 512 Kbytes is provided by 64K dynamic RAMs.
1.1.2 Video Monitor
The Concept video monitor is a Ball"" HD Series display unit. Under Direct Memory Access (DMA), approxi-
mately 55K
of main memory is ported directly to the 720 pixel bit mapped screen. The data is transmitted to the
screen at approximately 33 Mbits per second.
The
IS-inch monitor is mounted to allow the swivel or tilt of the screen for maximum operator comfort. The screen
can be operated in either a vertical (portrait) or horizontal (landscape) mode. Features of the monitor are:
• IS-inch CRT
• Bit mapped display
• Vertical tilt of +17 to -13 degrees
• Horizontal swivel of 90 degrees
• 720 pixels by 560 pixel screen
• 120 characters by 56 lines in the landscape mode
• 90 characters by 72 lines in the portrait mode
• Software generated character set
1.1.3 Keyboard
The compact keyboard is manufactured by Keytronics™ to Corvus specifications. Its features include:
• Selectric TM style alphanumeric keys
• Cursor movement keys
• IS-key numeric pad
• 10 programmable function keys
• Programmable character set
• Detachable coiled keyboard cable
1.1.4
Power Supply
The power supply, located in the base unit, is manufactured by AC/DC.TM The Power Supply provides:
• +5VDC at SA (60Hz, derate 10% for 50Hz)
•
+12VDC at 1.7A (60Hz, derate 10% for 50Hz)
•
-12VDC at 1.7A (60Hz, derate 10% for 50Hz)
The Processor and Memory Boards consume:
.6Aat5VDC
• 130 rnA at +12VDC (RS-232C)
• 170 rnA at -12VDC (RS-232C)
Available
power for shared I/O slots is:
• +5VDC at 500 rnA
• + 12VDC at 1.5A
• -12VDC at 1.3A
• -5VDC at 200 rnA
• 100/120VAC or 220/240VAC selectable
• 50Hz or 60Hz
• 200 Watts
4

CORVUS DEALER SERVICE
1.2 Concept Options
Corvus Systems offers an array of options for the Concept. These include software packages, storage devices, and
network capability. See the Service Manual for each hardware option for complete specifications.
1.2.1 Operating System Software
Some of the software packages provided on floppy diskettes for use with the Concept are:
• CCOS Operating System
• USCD P-System Operating System
• ISO Pascal with UCSD extensions
(native code complier)
• FORTRAN 77 (native code complier)
• 68000 Assembler
• EdWord TN Wordprocessor
• Corvus LogiCalc TM Electronic Spreadsheet
A complete list of current software may be obtained from the Corvus Systems Marketing Department.
1.2.2 Floppy Disk Drive
Manufactured by Tandon TN Corporation, the 8-inch Floppy Disk Drive is available with these features:
• 250 Kbytes formatted capacity
• Single-sided, single-density IBM 3740 format
• Read and write capabilities
In addition, a 51/4 inch Read-Only Disk Drive with a capacity of 140 Kbytes may be purchased from Corvus.
1.2.3 Winchester Disk Drive Options
Mass storage is provided for the Concept by a line of Winchester Disk Drives. Interface to the Concept is through a
50-pin I/O slot on the Processor Board. The drive models are:
RevS
• Model 6-5.7 Mbytes formatted
• Model 11-10.8 Mbytes formatted
• Model 20-19.7 Mbytes formatted
H-Series
• Model 11-12.1 Mbytes formatted
• Model 20-18.4 Mbytes formatted
1.2.4 Archival and Backup Options
Archival and backup storage can be accomplished with the Floppy Disk Drive or the Corvus Mirror® option. The
Mirror is used in conjunction with a video recorder to provide a copy of a Corvus Disk Drive on video tape. For
details of the Mirror, see the Mirror Service Manual.
1.2.5 Network Option
Corvus OMNINET circuitry is included on the Processor Board. The OMNINET Disk Server and related hardware
feature:
• One million bit per second transfer rate
• 64 possible network devices
• Twisted pair transmission cable
• 4000-foot network length
5

CORVUS DEALER SERVICE
CHAPTER 2
FUNCTIONAL DESCRIPTION
7

2.0 Scope of Chapter
CORVUS DEALER SERVICE
CHAPTER 2
FUNCTIONAL DESCRIPTION
In this chapter, a functional description of the Corvus Concept is presented. The two main printed circuit assem-
blies of
the Concept, the Processor Board and the Memory Board, will each be described.
2.1 Concept Processor Board
The Processor Board of the Concept can
be divided into the following sections:
• Microprocessor
• Bus Buffers
• Memory Mapper
• ROM and static RAM
.O:MNINET
• 50-Pin I/O Slots
• Data Communication Ports
• Interrupts
• Memory Arbitration
• Calendar
• Bell, Timer, and VIA
• Data Acknowledge
2.1.1 Microprocessor
The Concept is
based on the Motorola MC68000 8MHz microprocessor. It has a 16-bit bidirectional data bus, a
24-bit
address bus, and sixteen 32-bit internal registers. Its address lines are buffered to go to many locations. The
64-pin design eliminates
the need for data and address multiplexing by giving each data and address line a sepa-
rate pin.
28 FCO
Processor { ~;;';"";"'~----i
Status
20 E
MC68000 {
Peripheral ~.::......;....;..;...;..;.;;.~~
Control ----"''-'--'-'-.;...;...;,...;---t
.....
MC68000
MICROPROCESSOR
U306
A1-A23
29 through 48 and
50 through 52
D0-D15
5 through 1 and
64 through 54
-....;;...;;;...~~ .. lAsynchronous
Bus Control
-=----t .. } Bus Arbitration
Control
..... ..;;...;:,~--=...;._} Interrupt
Control
Figure 2. Motorola MC68000
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CORVUS DEALER SERVICE
2.1.2 Bus Buffers
The
address bus is buffered from the processor by three 74LS244s at locations US07, US08, U40Z Caution should
be exercised as these buffers may be damaged if shorted together. The data bus is unbuffered to the on-board
ROMs and static RAMs and is buffered to the I/O ports, OMNINET, and dynamic RAMs. If for any reason the
address or data bus becomes defective the processor will assert the HALT signal and abort all operations.
The control signals (WRITE, UPPER & LOWER
DATA STROBE, and ADDRESS STROBE) are buffered by a single
74LS244 at location U30Z The function codes lines are decoded to determine Supervisor Mode and Interrupt
Acknowledge. The Interrupt Acknowledge is connected to the Valid Peripheral Address Pin to indicate Auto Vec-
toring Interrupt Mode.
For further information on the processor, please refer to the Motorola 16-Bit Microprocessor User's Handbook.
2.1.3 Memory Mapper
The address space is divided into sections by a memory mapper PROM which examines the state of the address
bus and selects the appropriate device.
M3 12
MEMORY MAPPER
+5V
M
A21
AS
3 A20
N3
A19
6
04
13 NRAMIZl 2
A7
01
9 NROMIZl
13
N3
A12
02
10 NUl
NJ
11
10
A16
U309
03
11 NSRAM
825181 05 4 NRAMI
A10 12
10
A11
ALTMAP
NAS
08
17 NCYCRGM
07
16
A12
NSUPV 23
06
15 NIO
A13
8 NZERO 22
A14
~
10
20
A16
A17
11
+5V
Figure 3. Memory Mapper
An 825181 bipolar PROM examines the address lines to produce enable signals for I/O and memory. Additional
inputs are NZERO, ALTMAP and NSUPERVISOR. NZERO is output from a set of gates at U309 and USI0 which
detect that the lower address bits are at zero. If the higher address bits are at zero and ALTMAP is zero, ROMO will
be selected for a power-on boot. If no device is selected, CYCLE ROM is asserted to prevent the processor from
hanging up.
2.1.4
ROMs and Static RAM
There
are four 24-pin RAM sockets and two 28-pin ROM sockets mounted on the Processor Board.
10

U706
BOOT
ROM
LOW
U707
STATIC
RAM
LOW
CORVUS DEALER SERVICE
U708 U709
U710
STATIC
RAM
HIGH
Figure 4. ROM and Static RAM Sockets
U711
BOOT
ROM
HIGH
RAM sockets, locations U707 and U710, are intended to hold 2K x 8 static RAMs. These RAMs may contain system
variables, jump tables, and data stored during testing. The speed of the RAM can be accounted for by jumpers K4,
K5. (See Appendix H.)
The
ROMO sockets, locations U706 and U711, may hold ICs such as 2716s or 2732s. This ROM pair contains the
Boot Code, initial Self Test, setup data for I/O, simple keyboard map, a character set, etc. The ROMI sockets, loca-
tions U708 and U709, may hold such devices as 2716s, 2732s, 2764s, or other pin compatible ROMs. These ROMs
may be used in loading Motorola's MACSbug for bringup and diagnostic purposes or for installing the user's
firmware.
2.1.5
OMNINET
OMNINET circuitry is a self-contained unit on the Processor Board. The processor sends commands to the
OMNINET transporter circuit through the I/O bus. The processor places a byte of data on the bus and strobes
NOMNI. The data consists of three bytes containing an address where OMNINET is to find its command in mem-
ory. The processor checks the Versatile Interface Adapter, VIA, port A, bit 0 to see if the OMNINET is ready to receive
another byte of address. OMNINET has no other connection with the processor. It talks directly to memory, pre-
empting the processor by means of the Memory Arbiter. (See Section 2.1.9).
OMNINET'S 6801, U302,
and monochip, UI04, control Direct Memory Access (DMA). The Asynchronous Data
Link
Controller (ADLC) at U301 utilizes a pair of transmitters and receivers to balance the twisted pair cable,
RS-422, for
data transfer. The serial transfer rate is 1 Mbits per second. Parallel transfer by byte has a DMA rate of
125 Kbytes
per second.
When OMNINET does a DMA, it takes over the address and data buses going to the Memory Board. If the
MC68000 attempts to use memory during a DMA cycle it will be held off. Typically, there is a maximum one DMA
cycle in 8 microseconds. During this time there can be a maximum of seven MC68000 memory accesses. DMA
does not slow the MC68000 appreciably.
11