Corvus systems Personal Workstation User manual

THE CORVUS SERVICE MANuAL
CorvusConcept
*** CORVUS SYSTEMS
**

LIMITED WARRANTY
CORVUS SYSTEMS, Inc. warrants all its hardware and software for a period of 180 days from
the date of purchase from any authorized
Corvus Dealer. Should the product fail to be in good
working order at any time during this period, Corvus Systems will, at its option, repair or replace
this product at no additional charge except as set forth below. Repairs will be performed
and non-
functioning parts replaced either with
new or reconditioned components to make the product
function according to company standards and specifications. All replaced parts become the prop-
erty of Corvus Systems,
Inc. This limited warranty does not include service to repair damage to the
product resulting from accident, disaster, misuse, abuse or modifications that are unapproved by
Corvus Systems.
Limited Warranty service may be obtained by delivering the
product during the 180 day war-
ranty
period to Corvus Systems with proof of purchase date. YOU MUST CONTACT CORVUS
CUSTOMER SERVICE TO OBTAIN A"RETURN MERCHANDISE AUTHORIZATION"
PRIOR TO RETURNING THE PRODUCT. THE RMA (RETURN MERCHANDISE AUTHORI-
ZATION) NUMBER ISSUED
BY CORVUS CUSTOMER SERVICE MUST APPEAR ON THE
EXTERIOR OF THE SHIPPING CONTAINER
ONLY ORIGINAL OR EQUIVALENT SHIPPING
MATERIALS MUST
BE USED. If this product is delivered by mail, you agree to insure the prod-
uct
or assume the risk of loss or damage in transit, to prepay shipping charges to the warranty
service location
and to use the original shipping container. Contact Corvus Systems or write to
the Corvus Systems Service Center, 2029 O'Toole, San
Jose, CA 95131 prior to shipping equipment
ALL EXPRESSED AND IMPLIED WARRANTIES FOR THIS PRODUCT INCLUDING THE
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR APARTICULAR PURPOSE,
ARE
LIMITED IN DURATION TO APERIOD OF 180 DAYS FROM DATE OF PURCHASE, AND NO
WARRANTIES, WHETHER EXPRESSED OR IMPLIED WILL APPLY AFTER THIS PERIOD.
SOME STATES
DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WAR-
RANTY LASTS, SO THE ABOVE LIMITATIONS MAY NOT APPLY TO YOu.
IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED ABOVE, YOUR
SOLE
REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE. IN NO
EVENT WILL CORVUS SYSTEMS BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING
ANY LOST PROFITS, LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL
DAMAGES ARISING OUT OF THE USE OF OR INABILITY TO
USE SUCH PRODUCT, EVEN
IF CORVUS SYSTEMS OR AN AUTHORIZED CORVUS SYSTEMS DEALER HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY CLAIM
BY ANY
OTHER
PARTY.
SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS, SO THE
ABOVE LIMITATIONS
OR EXCLUSIONS
MAY NOT APPLY TO YOu.
THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU
MAY ALSO HAVE
OTHER RIGHTS WHICH
MAY VARY FROM STATE TO STATE.
FCC WARNING
This equipment generates, uses, and can radiate radio frequency energy and if not installed and
used in accordance with the instruction manual, may cause interference to radio communications.
As temporarily
permitted by regulation it has not been tested for compliance with the limits for
Class Acomputing devices pursuant to Subpart Jof Part 15 of FCC Rules, which are designed to.
provide reasonable protection against such interference in which case the user at his
own expense
will
be required to take whatever measures may be needed to correct the interference.
NOTICE
Corvus Systems, Inc. reserves the right to inake changes in the product described in this manual
at any time without notice. Revised manuals will
be published as needed and may be purchased
from authorized Corvus Dealers.
This manual is copyrighted
and contains proprietary information. All rights reserved. This docu-
ment may not, in whole or in part be copied, photocopied, reproduced, translated,
or reduced to
any electronic medium or machine readable form without prior consent, in writing, from Corvus
Systems, Inc.
CORVUS SYSTEMS
2029 O'Toole Avenue
San Jose, CA 95131
Telephone: [phone]
TELEX: 278976
Copyright
©1983 by Corvus Systems, Inc.
The Corvus Concep!,'" Transporter,'" Corvus OMNINET,
'" Corvus Logicalc,'" Time Travel Editing,'"
EdWord,'" Constellation,'" Corvus,'"
Corvus Systems,'" Personal Workstation,'" Tap Box,'" Passive
Tap
Box,'" and Omninet Unit'" are trademarks of Corvus Systems, Inc.

CORVUS DEALER SERVICE
CORVUS SYSTEMS
CONCEPT
PERSONAL WORKSTATION
SERVICE MANUAL
PART NO.: 7100-04701
DOCUMENT NO.: CCC/30-01/1.1
RELEASE DATE: April, 1983
This document contains three types of notations. These are, in increasing order of importance.
NOTE, CAUTION, and WARNING. The NOTE indicates some action to be taken to speed or
simplify a procedure. The CAUTION indicates that potential damage to the equipment or user
data exists, and care should be taken to avoid this. The WARNING indicates that potential
harm or injury to the service technician or operator exists, and extreme care should be taken to
avoid these.

CORVUS DEALER SERVICE
TABLE OF CONTENTS
iii

Ball~ is a trademark of Ball Inc.
Selectric~ is a trademark of IBM Corp.
AC/DC~ is a trademark of AC/DC Inc.
Tandon ~ is a trademark of Tandon Corp.
MACSbug~ is a trademark of Motorola Corp.
Synertek ~ is a trademark of Synertek
Moss Technology is atrademark of Moss Technologies Inc.
Rockwell International is atrademark of Rockwell International Corp.
iv

CORVUS DEALER SERVICE
TABLE OF CONTENTS
CHAPTER I-OVERVIEW
1.0 Scope of Chapter. ......................................................................... .. 3
1.1 Concept Modules. ................... .. ............................. .. ..................... .. 3
1.1.1 Electronics Tray. ................................................................. .. 3
1.1.1.1 Processor Board ....................................................... .. 3
1.1.1.2 Memory Board ........................................................ .. 4
1.1.2 Video Monitor. .................................................................. .. 4
1.1.3 Keyboard. ....................................................................... .. 4
1.1.4 Power Supply. ................................................................... .. 4
1.2 Concept Options. ......................................................................... .. 5
1.2.1 Operating System Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . .. 5
1.2.2 Floppy Disk Drive. .............................................................. .. 5
1.2.3 Winchester Disk Drive Options ................................................... .. 5
1.2.4 Archival and Back-Up Option. .................................................... .. 5
1.2.5 Network Option ................................................................ .. 5
CHAPTER 2-FUNCTIONAL DESCRIPTION
2.0 Scope of Chapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
2.1 Concept Processor Board. .................................................................. .. 9
2.1.1 Microprocessor ................................................................. .. 9
2.1.2 Bus Buffers 10
2.1.3 Memory Mapper 10
2.1.4 ROMs and Static RAM 10
2.1.5 OMNINET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
2.1.6 50-Pin I/O Slots 12
2.1.7 Data Communication Ports 13
2.1.8 Interrupts 14
2.1.9 Memory Arbitration 15
2.1.10 Calendar 16
2.1.11 Bell, Timer, and VIA. ..............................................................16
2.1.12 Data Acknowledge 16
2.2 Concept Memory Board 17
2.2.1 Oscillator 17
2.2.2 Horizontal Timing 17
2.2.3 Vertical Timing 18
2.2.4 RAM Timing 18
2.2.5 Memory Selection 18
2.2.6 Video Address Counter 18
2.2.7 Memory Multiplexing 18
2.2.8 Memory Array 18
2.2.9 Memory Buffers 19
2.2.10 Video Shift Registers 19
CHAPTER 3-DISASSEMBLY
3.0 Scope of Chapter 23
3.1 Installation 23
3.2 Visual Inspection 23
3.3 Video Monitor Removal and Disassembly 23
3.4 Keyboard Disassembly and Cleaning 24
v

CORVUS DEALER SERVICE
3.5 Electronics Tray Disassembly and Assembly :24
3.6
Power Supply Removal 25
CHAPTER 4-ADJUSTMENTS
4.0 Scope of Chapter 29
4.l Concept Power Supply Adjustments 29
4.2 Preparations for Video Adjustments 30
4.3 Video
Alignment and Adjustment 30
5.3
5.1
AppendiX E:
Appendix F:
CHAPTER 5- TROUBLESHOOTING
5.0 Scope of Chapter 37
5.1 Levell Troubleshooting 37
5.1.1 Video
Monitor 37
5.1.2 Power Supply 39
5.1.3
Power-On Self Tests 40
5.1.4 Self Test
Error Codes 41
5.1.5 Boot Problems 42
Level 2
Troubleshooting 44
5.2.1 MACSbug Installation
Procedures 44
5.2.2
Communicating with MACSbug 46
5.2.3
Operating Procedures 46
5.2.4 MACSbug Routines 47
Component Level Troubleshooting 47
5.3.1 Proct;ssor Signal Descriptions 47
5.3.2
Processor Test Points 47
5.3.3 Memory and Video Controller Test Points 50
AppendiX
A: Schematics and Assembly Drawings 53
A-I Revision 03 Schematics 55
A-2 Revision 04 Schematics
61
A-3 Assembly Drawings 73
Troubleshooting Flow Chart 83
Test Point Signals 89
C-1
Processor Board Signals 90
C-2
Memory Board Signals 95
Timing Charts 99
0-1 Processor Board Timing Charts 101
0-2 Memory Board Timing Charts 104
MACSbug 107
E-1
MACSbug Commands 109
E-2
MACSbug Routines 111
E-3 Self Test
Routines. .............................................................117
Maps '123
F-1 General Memory and I/O Maps 125
F-2 ROM Mapping of I/O Slots 129
F-3 VIA
General Purpose I/O Ports 131
F-4 OMNINET 135
F-5 Clock/Calendar/ALTMAP/Volume 139
F-6 Data
Communication and Keyboard Registers 143
Memory Board Jumper Layout 149
Appendix 0:
Appendix B:
AppendiX C:
Appendix G:
vi

AppendixH:
Appendix I:
Appendix J:
CORVUS DEALER SERVICE
Connector Descriptions 153
H-l 50-Pin I/O SLOT Description 155
H-2 Data Communication Ports Jl and J2 157
H-3 Board Connectors J4, J5, and J6 161
H-4 Additional Connectors 165
Concept Parts List 169
Specifications 173
LIST OF ILLUSTRATIONS AND TABLES
ILLUSTRATIONS
Figure Page
1 Concept Components. ..................................................................... .. 3
2Motorola MC68000. ....................................................................... .. 9
3 Memory Mapper 10
4ROM and Static RAM Sockets 11
5ADLC 12
6Data Acknowledge Timing 16
7Horizontal Timing Circuit 17
8 Concept Rear View 23
9Latch Screws 24
10 Electronics Tray Power Connections 24
11 Concept Power Supply Voltage Adjustments 29
12 CRT Adjustment Yoke 31
13 Horizontal and Vertical PCA. 31
14 Video PCA 32
15 CORCOM Setting 38
16 Monitor Voltage Test Points 39
17 Rev 03 Boot Switch Settings 43
18 Rev 04 Boot Switch Setting 43
19 Rev 03 ROM and RAM Locations 45
20 Rev 04 ROM and RAM Locations 45
TABLES
Table Page
1 I/O Address Space 12
2 I/O Slot Pin Descriptions 13
3 Interrupt Levels 14
4Processor Board Test Points 48
5 Memory and Timing Signal Locations 50
vii

CORVUS DEALER SERVICE
CHAPTER 1
OVERVIEW
1

CORVUS DEALER SERVICE
CHAPTER 1
OVERVIEW
1.0 Scope of Chapter
The Corvus Concepf" Personal WorkstationNis designed with service in mind. Its modular components can be
substituted during on-site servicing to minimize system down time. These modules are outlined in this chapter.
Options available to enhance the Concept are also discussed.
1.1 Concept Modules
The Concept base contains a power supply, fan, and removable electronics tray. This tray contains the Processor
Board, the Memory Board, speaker, and calendar battery. The modular design of the Concept allows easy access
and replacement of the electronic subassemblies.
mmnmn 111I11I1111I1 111I IIIlIIl
Base
'7
1
J
.::::::,
Video Monitor
Bifurcated Cable Keyboard
1.1.1 Electronics Tray
The entire tray may be removed for replacement when an immediate repair is required. The Processor Board and
Memory Board may be individually substituted if time permits additional troubleshooting.
1.1.1.1 Processor Board
AMotorolaNMC68000 Microprocessor, Boot RAMs and ROMs, OMNINET,N and Clock Calendar are the major
components of the Processor Board. 110 circuitry is also resident on the Processor Board. Specific features include:
Microprocessor
•Motorola MC68000
•16/32-bit
data registers
•24-bit memory address bus
•16-bit data bus
Input/Output
• OMNINET Network interface
•Two serial
asynchronous I/O ports
•Clock and calendar backup battery
•Flexible sound generator
•Two interval timers
•
Four 50-pin I/O slots
3

•100/120VAC or 220/240VAC selectable
•
50Hz or 60Hz
•200 Watts
CORVUS DEALER SERVICE
1.1.1.2 Memory Board
The
Memory Board provides asophisticated scheme which produces both memory timing and video timing. The
Memory Board includes:
•256 Kbytes
standard or 512 Kbytes optional memory
•Vertical and horizontal timing
•RAM
timing
• Memory addressing
•Video interface
•System
master clock
The 256 or 512 Kbytes is provided by 64K dynamic RAMs.
1.1.2 Video
Monitor
The Concept video monitor is aBallN HD Series display unit. Under Direct Memory Access (DMA), approxi-
mately 55K of main memory is ported directly to the 720 pixel bit mapped screen. The data is transmitted to the
screen at approximately 33 Mbits per second.
The IS-inch monitor is mounted to allow the swivel or tilt of the screen for maximum operator comfort. The screen
can be operated in either avertical (portrait) or horizontal (landscape) mode. Features of the monitor arc:
•
IS-inch CRT
•Bit mapped display
•Vertical tilt of
+17 to -13 degrees
• Horizontal swivel of 90 degrees
•720 pixels by 560 pixel screen
•120 characters by 56 lines in the landscape mode
•90 characters by 72 lines in the portrait mode
•Software generated character set
1.1.3 Keyboard
The compact keyboard is manufactured by Keytronics'· to Corvus specifications. Its features include:
•SelectricNstyle
alphanumeric keys
•
Cursor movement keys
•IS-key
numeric pad
•10 programmable function keys
•
Programmable character set
•Detachable coiled
keyboard cable
1.1.4
Power Supply
The power supply, located in the base unit, is manufactured by AC/DC.
N
The Power Supply provides:
•
+5VDC at 8A (60Hz, derate 10% for 50Hz)
•
+12VDC at 1.7A (60Hz, derate 10% for 50Hz)
• -12VDC at 1.7A (60Hz, derate 10% for 50Hz)
The Processor and Memory Boards consume:
•
6Aat 5VDC
•130 rnA
at +12VDC (RS-232C)
•170 rnA at
-12VDC (RS-232C)
Available
power for shared I/O slots is:
•
+5VDC at 500 rnA
•
+12VDC at 1.5A
•
-12VDC at 1.3A
•
-5VDC at 200 rnA
4

CORVUS DEALER SERVICE
1.2 Concept Options
Corvus Systems offers an array of options for the Concept. These include software packages, storage devices, and
network capability. See the Service Manual for each hardware option for complete specifications.
1.2.1
Operating System Software
Some of the software packages provided on floppy diskettes for use with the Concept are:
•
CCOS Operating System
•USCD P-System
Operating System
•ISO Pascal with UCSD extensions
(native code complier)
•FORTRAN 77 (native code complier)
•68000 Assembler
•EdWordNWordprocessor
•
Corvus LogiCalcNElectronic Spreadsheet
A complete list of current software may be obtained from the Corvus Systems Marketing Department.
1.2.2 Floppy Disk Drive
Manufactured by TandonNCorporation, the 8-inch Floppy Disk Drive is available with these features:
•250 Kbytes formatted capacity
•Single-sided, single-density IBM 3740 format
•Read
and write capabilities
In addition, a 51 /4 inch Read-Only Disk Drive with acapacity of 140 Kbytes may be purchased from Corvus.
1.2.3 Winchester
Disk Drive Options
Mass storage is provided for the Concept by aline of Winchester Disk Drives. Interface to the Concept is through a
50-pin
I/O slot on the Processor Board. The drive models are:
RevB
•Model 6-5.7 Mbytes formatted
•Model 11-10.8 Mbytes formatted
•Model
20-19.7 Mbytes formatted
H-Series
•Model
11-12.1 Mbytes formatted
•Model
20-18.4 Mbytes formatted
1.2.4 Archival
and Backup Options
Archival and backup storage can be accomplished with the Floppy Disk Drive or the Corvus Mirror® option. The
Mirror is used in conjunction with avideo recorder to provide a copy of a Corvus Disk Drive on video tape. For
details of
the Mirror, see the Mirror Service Manual.
1.2.5 Network Option
Corvus OMNINET circuitry is included on the Processor Board. The OMNINET Disk Server and related hardware
feature:
•
One million bit per second transfer rate
•64 possible
network devices
•Twisted
pair transmission cable
•4000-foot
network length
5

CORVUS DEALER SERVICE
CHAPTER 2
FUNCTIONAL DESCRIPTION
7

CORVUS DEALER SERVICE
CHAPTER 2
FUNCTIONAL DESCRIPTION
2.0 Scope of Chapter
In this chapter, afunctional description of the Corvus Concept is presented. The two main printed circuit assem-
blies of
the Concept, the Processor Board and the Memory Board, will each be described.
2.1 Concept Processor Board
The Processor Board of the Concept can be divided into the following sections:
•Microprocessor
•Bus Buffers
•
Memory Mapper
•ROM and static RAM
.OMNINET
•50-Pin I/O Slots
•Data
Communication Ports
• Interrupts
• Memory Arbitration
•
Calendar
•Bell, Timer, and VIA
•Data Acknowledge
2.1.1 Microprocessor
The Concept is based on the Motorola MC68000 8MHz microprocessor. It has a16-bit bidirectional data bus, a
24-bit
address bus, and sixteen 32-bit internal registers. Its address lines are buffered to go to many locations. The
64-pin design eliminates
the need for data and address multiplexing by giving each data and address line asepa-
rate pin.
9

CORVUS DEALER SERVICE
2.1.2 Bus Buffers
The address bus is buffered from the processor by three 74LS244s at locations U507, U508, U40Z Caution should
be exercised as these buffers may be damaged if shorted together. The data bus is unbuffered to the on-board
ROMs and static RAMs and is buffered to the I/O ports, OMNINET, and dynamic RAMs. If for any reason the
address or data bus becomes defective the processor will assert the HALT signal and abort all operations.
The control signals (WRITE, UPPER &LOWER DATA STROBE, and ADDRESS STROBE) are buffered by asingle
74LS244 at location U30Z The function codes lines are decoded to determine Supervisor Mode and Interrupt
Acknowledge. The Interrupt Acknowledge is connected to the Valid Peripheral Address Pin to indicate Auto Vec-
toring Interrupt Mode.
For further information on the processor, please refer to the Motorola 16-Bit Microprocessor User's Handbook.
2.1.3 Memory Mapper
The address space is divided into sections by a memory mapper PROM which examines the state of the address
bus and selects the appropriate device.
1>3 12
MEMORY MAPPER
+5V
A4
A21
MA20
N;
04
13 NRAM0
A19 6
A7
01
9
NROM0
13
02
10 NUl
I>B
A12
U399 03
11 NSRAM
A9 5
11
A16 3
10
825181 4NRAMI
05
Al0 12
10
08
17 NCYCRGM
ALTMAP
All
16
NAS
07
A12
06
15 NIO
NSUPV 23
A13
NZERO 22
A14
~
10
A16
A17 11
+5V
Figure 3.
Memory Mapper
An 82S181 bipolar PROM examines the address lines to produce enable signals for I/O and memory. Additional
inputs are NZERO, ALTMAP and NSUPERVISOR. NZERO is output from aset of gates at U309 and U510 which
detect that the lower address bits are at zero. If the higher address bits are at zero and ALTMAP is zero, RaMO will
be selected for apower-on boot. If no device is selected, CYCLE ROM is asserted to prevent the processor from
hanging up.
2.1.4 ROMs and Static RAM
There are four 24-pin RAM sockets and two 28-pin ROM sockets mounted on the Processor Board.
10

CORVUS DEALER SERVICE
U708 U709
U706
BOOT
ROM
LOW
U707
STATIC
RAM
LOW
U710
STATIC
RAM
HIGH
U711
BOOT
ROM
HIGH
Figure 4. ROM and Static RAM Sockets
RAM sockets, locations U707 and uno, are intended to hold 2K x 8 static RAMs. These RAMs may contain system
variables, jump tables, and data stored during testing. The speed of the RAM can be accounted for by jumpers K4,
K5. (See Appendix H)
The ROMO sockets, locations U706 and U711, may hold ICs such as 2716s or 2732s. This ROM pair contains the
Boot Code, initial Self Test, setup data for I/O, simple keyboard map, acharacter set, etc. The ROM1sockets, loca-
tions U708
and U709, may hold such devices as 2716s, 2732s, 2764s, or other pin compatible ROMs. These ROMs
may
be used in loading Motorola's MACSbug for bringup and diagnostic purposes or for installing the user's
firmware.
2.1.5 OMNINET
OMNINET circuitry is aself-contained unit on the Processor Board. The processor sends commands to the
OMNINET transporter circuit through the I/O bus. The processor places a byte of data on the bus and strobes
NOMNI. The data consists of three bytes containing an address where OMNINET is to find its command in mem-
ory. The processor checks
the Versatile Interface Adapter, VIA, port A, bit 0to see if the OMNINET is ready to receive
another byte of address. OMNINET has no other connection with the processor. It talks directly to memory, pre-
empting the processor by means of the Memory Arbiter. (See Section 2.1.9).
OMNINET'S 6801, U302,
and monochip, U104, control Direct Memory Access (DMA). The Asynchronous Data
Link
Controller (ADLC) at U301 utilizes a pair of transmitters and receivers to balance the twisted pair cable,
RS-422, for data transfer. The serial transfer rate is 1Mbits per second. Parallel transfer by byte has aDMA rate of
125 Kbytes per second.
When OMNINET does aDMA, it takes over the address and data buses going to the Memory Board. If the
MC68000 attempts to use memory during aDMA cycle it will be held off. Typically, there is a maximum one DMA
cycle in 8microseconds. During this time there can be a maximum of seven MC68000 memory accesses. DMA
does not slow the MC68000 appreciably.
11

CORVUS DEALER SERVICE
NRESETOM 3
FO
25
EOUT
13 +SV
TOSR
,.
+sv
2'
ROSA
23
NIRQ
TXO
RS<!
10
RSI
TXENA
11
INour
12
NSC
ADLC
Ulle
RXO
500
NRTS
22
501
21
RXC
502
20
TXC
503
19
SO,
18
27 28
2. 29
505
17
SD6
,.
SOl
MONOCHIP
IS
Ule9
NeTS
21
NCDU 28
Figure 5. ADLC
To begin the DMA of abyte, the monochip asserts a DMA request, DMAREQ. This is synchronized by the Mem-
ory Arbiter which switches the memory address and data bus from the processor to OMNINET. The Arbiter begins
a memory cycle and asserts DMAGO, indicating that OMNINET is in the process of doing aDMA. Following
DMAGO, DMAREQ is negated. When the memory cycle is complete DMAGO is negated and the monochip sets
up to accept the data into the ADLC (only on aread) and terminates the DMA cycle. Control of the memory buses
are then returned to the processor.
OMNINET
produces 20 address bits. Address zero is converted into upper and lower device select before being
sent to RAM. OMNINET ignores address bits 21 and up.
2.1.6
50-Pin I/O Slots
Four 50-pin board edge connector slots are provided to handle other local I/O, such as to a Corvus Floppy Disk
Drive or Winchester Disk System.
The
I/O address space is divided into eight blocks by U605. They are subdivided as shown in Table 1.
Block 0-4
Block 5
Block 6
Block 7
(See
I/O Slots Apendix F)
Allow reading of the NMI and IRQ lines from each of the slots on a single operation.
Allows reading
of the Clock Calendar
Allows reading or writing to the I/O Ports.
Block 7can further be subdivided into:
o
1
2
2
3
NKBP
NSRO
NVIA
NSR1
NVIA
Keyboard
Data Comm
Port 0
Data
Comm Port 1
Versatile
Interface Adapter
4
5
6
7
NCALM
NOMNI
NOMOFF
NIOSTRB
Clock calendar address and Strobe register
OMNINET Strobe
Reset OMNINET Interrupt Flip-Flop
External
I/O ROM Strobe
Table 1. I/O Address Space
12

CORVUS DEALER SERVICE
I/O slots provide access to such devices as Corvus disk systems, parallel printers etc. These slots do not support
DMA because they do not share the data and address buses with the dynamic memory. They are connected to the
interrupt structure.
Table 2gives slot
pin descriptions.
Concept
Pin Signal Name
1NIOX
2 A1
3A2
4A3
5A4
6 AS
7 A6
8 A7
9A8
10 A9
11 A10
12 A11
13 A12
14 A13
15 A14
16 A15
17 A16
18 NWRITE
19
20 NIOSTB
21
22
23
24
25 +5V
Apple II'"
Concept
Apple II'"
Equivalent Pin Signal Name
Equivalent
I/O SEL
26
GNO GNO
AO 27
OMAIN
A1 28
INTIN
A2
29
NNMI-X NMI
A3
30
NIRO-X NIRO
A4
31 NRESET RES
AS 32
NINH
A6
33
-12V -12V
A7 34
-5V
-5V
A8 35
A9
36 7MHz
A10 37
03 03
A11
38
NIM
PHIO
A12
39 USER 1
A13
40 1M PHI1
A14
41 NOEVX NOEV SLCT
A15
42
1007 07
R/W 43 1006
06
44 1005
05
I/O STROBE
45 1004 04
NROY
46 1003
03
NOMA
47 1002
02
INTOUT
48 1001 01
OMAOUT
49 1000
00
+5V 50
+12V +12V
Table 2.
I/O Slot Pin Descriptions
2.1.7
Data Communication Ports
Two RS-232C ports with independent baud rates can be used for an external terminal, modem, printer, or other
peripheral device. They share the I/O bus and interrupt structure with other I/O devices. The connection is by
10-wire, 25-pin sub miniature 'D' female shells, connected as Data Terminal Equipment. A modem eliminator cable
is necessary to
communicate with equipment other than modems.
Both serial data
ports are able to communicate at baud rates from 110 to 19200, with selectable parity and word
size. The receive and the transmit functions can be Interrupt generating or Non-Interrupt generating as selected.
The UART Baud
Generator requires a1.818MHz frequency which is obtained by dividing the 16.364MHz system
oscillator
by 9using U212 (74LS161).
Motorola's 1488
and 1489 devices, at U213, U214, U314, and U415, transmit and receive the +12 RS-232C voltages.
A470 pF capacitor is
used at each RS-232C line for speed control. The keyboard interface is driven by a Schmitt
trigger inverter, U1l5, also used to receive keyboard data.
13

CORVUS DEALER SERVICE
Three Control lines on each port are receivers: Data Set Ready (DSR), Clear to Send (CLS), and Data Carrier
Detect (DCD). These can be used for handshaking or with a modem. Three Control lines Data Terminal Ready
(DTR),
Request To Send (RTS), and Rate Select (CH) are for output. DTR and RTS are functions of the UART, con-
trolled
by setting the UART command and control registers. CH is a bit for each port on the VIA Port Busually
used for selecting between high and low speed on dual rate modems. Appendix H-2 describes the Data Communi-
cation Ports Jl and J2.
It is recommended that shielded RS-232C cables be used. If these are not available, an in-line filter is recom-
mended.
If data communication cables are strung long distances or between buildings in lightning prone areas, only
Receive Data, Transmit Data, Signal Ground and Protective Ground should be used. The first three should each be
connected to protective ground by aTranzorb or other transient energy absorber.
NOTE:
There ,is a requirement by some European PITs that the user be informed when a modem has gone off-
line. The driver may monitor the appropriate line, transmit a message to be displayed. Also required may be
logical relationships and timing between input and corresponding output control lines. As the Concept
requires no hardware relationships, PTT requirements must be fulfilled by the drivers.
2.1.8 Interrupts
Six interrupt lines are served by an Auto Vectored Interrupt mechanism. The highest priority, Non-Maskable Inter-
rupt (NMI), is not used. The two Data Com devices, the keyboard, the VIA, and OMNINET each have their own
interrupt vectors. The data communication control lines shares the lowest vector with the 50-pin bus interrupt.
Although the processor can be run without interrupts, most of the I/O devices can cause interrupts so that an effi-
cient interrupt driven operating system is created. Because 6502 I/O devices are used, which cannot produce vec-
tors,
the auto vector mode of interrupt is used. The level 7NMI is used only when the software monitor is installed
for debugging. The user cannot initiate an NMI. Interrupt Acknowledge is decoded in the following manner:
Priority Level
Signal Name
Device
7
Not Used
6NKEYINT Keyboard
5
NTIMINT
VIA Timer
4NSROINT RS-232C Porta
3
NOMINT
OMNINET
2NSR11NT RS-232C Port 1
1NIOCINT Data
Com/
50-Pin Slots
Table 3. Interrupt Levels
Note that the Data Com controls and 50-pin I/O slot interrupts share the priority one interrupt. The interrupt pri-
ority can be set to any of the seven levels. An interrupt below the current level will not be served until the inter-
rupt level is dropped to that level or below. An interrupt raises the priority level to its own level. The Return From
Interrupt sets the priority to the level just prior to the interrupt. If the priority is set to 7, no interrupt can occur,
thus allowing critical code sections to complete without fear of interruption. For further details, refer to the
Motorola MC68000 User's Manual.
The keyboard and data communication devices are 6551 UARTS from Synertek
NInc., Rockwell International,N
or
MOS Technology.N The Timer is part of a6522 Versatile Interface Adapter, VIA, from the same manufacturers.
Additional
information about these devices can be found in the Synertek Data Catalog.
1. Keyboard Interrupts
The keyboard UART, U310, acts as areceive only UART except during testing operations. Each time it
14

CORVUS DEALER SERVICE
receives a new character, it causes alevel six interrupt. Key strokes cause the keyboard software driver to
send a code to the current program. Key releases cancel automatic key repeat or remove qualifies such as a
shift
and control.
2. Timer Interrupts
Counter U313 in the VIA is used to aid timing, including the repeat key timing. This counter interrupts every
50 microseconds with a priority levelS interrupt. No other possible interrupt of the VIA are used.
3. Data
Communication Port 0
UART U311 can
be set up to interrupt on receiving or transmitting acharacter. It is intended for use with a
terminal
or modem, but can be configured for any RS-232C function. Baud rate and parity may be selected.
Handshaking is covered in section 2.1.7. Each time a character is received or has been transmitted, a priority
level 4 interrupt occurs.
4. Data Communication Port 1
The DART U312 is similar to that of the UART for Data Port o. Its primary function is driving serial printers.
It
generates a priority level 2 interrupt.
5. OMNINET
After an operation, OMNINET generates a priority level 3interrupt. OMNINET cannot tum the interrupt off;
NOMOFF must be sent at the end of the interrupt process to tum the interrupt off (U304).
2.1.9
Memory Arbitration
The dynamic memory may be accessed by the MC68000 or an OMNINET DMA. A set of flip-flops and logic arbi-
trate when both the MC68000 and OMNINET try to access memory at the same time. The Memory Board requires
RAMSEL before an access can start; RAMSEL must be negated before a new access can start. NRAMACK signals
that the data in an access has been processed.
Signal
names and their functions may be found in Chapter 5.
1. MC68000 Memory Access Without DMA Conflict
When the MC68000 produces an address in the dynamic memory range, 68K RAMSEL is asserted. It is then
presented to the J input of JK flip-flop U204-11. After the Address Select (NAS) is asserted, the Q of the JK
flip-flop U204-9 will become true at the next 16M clock. The Q(68KGO) is passed through OR Gate U203-8
to become RAMSEL. When the data has been processed by the memory, NRAMACK is asserted. NRAMACK
then goes through an OR gate to become NTACK U203-11, and finally through the data acknowledge timing
gates U411
and U510 to become NDTACK. After receiving NDTACK the MC68000 disasserts NAS, clearing
the JK flip-flop and preparing for the next memory access.
2. DMA Without MC68000 Conflict
OMNINET asserts DMAREQ (DMA request) which is applied to the J of the JK flip-flop U104-3. At the next
16M clock the JK flip-flop asserts DMAEN (DMA enable) U104-5. One 16M clock time later NDMAGO
U204-6 is asserted which sets DMAG02 U104-9. NDMAGO tells OMNINET that the requested DMA cycle
has begun, DMAG02 U104-9 switches the memory address and data buses to OMNINET.
DMAGO is passed through OR gate U203-10 to assert RAMSEL. The assertion of DMAGO causes OMNINET
to disassert DMAREQ.
When NRAMACK is asserted it clears DMAEN and DMAGO, causing OMNINET to
accept
the data (if a read was in progress) and to complete the DMA cycle. DMAG02 follows DMAGO one
16M clock later, switching the memory and data buses back to the MC68000. The disassertion of DMAGO
removes RAMACK, preparing for the next memory cycle.
3. Collisions
If aMC68000 RAMSEL occurs when DMAEN or DMAGO is true, gate U205-6 will prevent 68KGO from
occurring.
When both DMAEN and DMAG02 have been disasserted, the next 16M clock will cause 68KGO
to
be asserted and a memory cycle to begin as before.
If DMAEN is asserted while 68KGO is true, DMAGO will not be allowed to set. Moreover when NRAMACK
is
asserted it will clear DMAEN. After 68KGO is disasserted, the next 16M clock will allow DMAEN to set,
beginning aDMA access now that the conflict has been removed.
15