Creotech FMC masterFIP User manual

FMC masterFIP
Production Test Suite
User Manual
Creotech Instruments SA | Jan 2018 | Version 4.0

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Revision Table
Revision
Date
Author
Comments
4.0
31/01/2018
Eva Gousiou
Update to board version V4: changed log
folder name, ipmi part: EDA-03098-V4.
3.0
08/03/2017
Marek Gumiński
Update to board version V3: removed ADC
tests, modified EXT_SYNC tests.
2.0
16/11/2016
Evangelia Gousiou
Changes for V2 version of the board (removed
EXT_SYNC_TST)
1.0
11/07/2016
Marek Gumiński
Implemented CERN suggestions
0.1
01/06/2016
Marek Gumiński
Initial version.

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Table of content
1. Introduction.................................................................................................................................... - 3 -
2. FMC masterFIP Board Functionality ............................................................................................... - 9 -
3. PTS Functionality Tests ................................................................................................................. - 10 -
4. Log files retrieval .......................................................................................................................... - 11 -
5. Custom cable preparation ............................................................................................................ - 12 -
6. First Time Setup............................................................................................................................ - 13 -
7. Testing Procedure......................................................................................................................... - 15 -
8. Common Causes of Test Failure ................................................................................................... - 17 -

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1. Introduction
Welcome to the Production Test Suite for the FMC masterFIP board –FMC masterFIP PTS.
The FMC masterFIP Production Test Suite (PTS) is an extension of the original PTS which allows to
perform functionality tests on FMC masterFIP boards after manufacturing. The original PTS was intended
for testing boards designed for the Open Hardware Repository, but it proved to be adaptable to other
boards. It assures that the boards comply with a minimum set of quality rules, in terms of soldering,
mounting and fabrication process of the Printed Circuit Boards (PCB).
It is important to note that the FMC masterFIP PTS covers only to the functionality tests of the boards
and does not cover any verification or validation tests of the design. This document describes the FMC
masterFIP PTS components and its use.
Figure 1: FMC masterFIP PTS view

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The main elements of the PTS are listed in Table 1.
Table 1: FMC masterFIP PTS elements
Item
Comments
Computer
A computer based on motherboard with 4 line PCIe slots is required
Monitor
Keyboard, Mouse
Barcode reader
With USB connection to the computer
ESD wrist strap
With banana type connection to the computer chassis
PCIe extender cable
Two spacers and four screws to fix the PCIe extender board to the
computer case
SPEC board
Four spacers and height screws are used to fix the board to the
computer case
FMC masterFIP
Board under test
1x LEMO cable
Any length, min 2 ns recommended
1x LEMO –Dsub9 custom cable
Schematic shown in Figure 9, picture of real component in Figure 6
1x LEMO –miniDsub9 custom
cable
Schematic shown in Figure 9, picture of real component in Figure 6
nanoFIPDiag
nanoFIPdiag version must match FMC masterFIP under test speed
version.
http://www.ohwr.org/projects/nanofipdiag/wiki
USB relay box 1
FMC Fine Delay version. USB cable provided
http://www.ohwr.org/projects/usb-relay-box1/wiki
Documentation
This user guide plus the one-page testing procedure
In terms of software, the computer is equipped with the following:
Table 2: PTS software requirements
Ubuntu Linux 14.04.00 LTS
Python 2.7
The user login is:
Table 3: Computer login
Username
user
Password
baraka
Note that after the software installation the computer should be disconnected from the network and no
updates should be allowed.

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The following paragraphs provide an overview of the required items.
The FMC masterFIP mezzanine board is tested while mounted on a SPEC carrier board, as Figure 2 shows.
The SPEC carrier board provides access to the PCIe interface of the computer. The computer hosts the
FMC masterFIP PTS software which provides the automated testing environment.
Figure 2: SPEC-DAC-DDS combination
To facilitate the testing setup, the SPEC carrier is fixed on the computer’s box and a PCIe extender cable
is used.
Figure 3: SPEC connected to the PCIe extender

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The Relay Box (fine delay version) is controlled by PTS software in order to automate cable
reconnections.
Figure 4: USB relay box 1
The nanoFIPdiag is used to verify the WorldFIP bus communication by answering to WorldFIP question
frames. Note that the nanoFIPdiag speed version should match the version of the masterFIP under test.
Figure 5 nanoFIPdiag

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Custom cables are used to connect the FMC masterFIP to the nanoFIPdiag via the USB relay box.
Figure 6 Custom cables
One standard Lemo00-Lemo00 cable is also required. Any length may be used.

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The test setup is shown on Figure 7.
Figure 7: Test setup connections. LEMO-LEMO cable is marked red. Custom LEMO-miniDsub9 is marked blue. Custom
LEMO-Dsub9 is marked green.
The complete duration of the test is around five minutes.
In brief, the operator needs to:
omount the FMC masterFIP board onto the SPEC carrier
oconnect the cables between the FMC masterFIP, the USB relay box and the nanoFIPdiag
orun the software
oat certain points of the tests an intervention needs to be done by the operator (e.g.: scan the
board’s barcode, check the font panel LED); the interventions are explicitly signaled by the FMC
masterFIP PTS software and this manual.
At the end of the functionality tests the operator receives a PASS/FAIL notification. In case of a FAILED
board, information is provided on the failing components.
All test results are automatically saved in a folder on the computer.
A board is considered to have passed the PTS testing if it has successfully completed all the functionality
tests.
For a FAILED board, you can repeat the test only one more time! If a board FAILs twice, please report to
the CERN responsible.

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2. FMC masterFIP Board Functionality
FMC masterFIP is an interface card for the WorldFIP network in an LPC FMC form-factor.
WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems.
Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for
the exchange of data between their sensors and actuators and the control and supervision level. With
Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.
Figure 8: Bottom, top and front views of the masterFIP board
The FMC masterFIP mezzanine board is tested while mounted on a SPEC carrier board. The SPEC provides
FPGA logic, power supplies, memories, clocking resources and interface to the PCIe bus. The mezzanine
houses all the WorldFIP specific parts (FielDrive, FieldTR).
There are four different versions of masterFIP boards that correspond to the four different WorldFIP
speeds: 31.25 Kbps, 1 Mbps, 2.5 Mbps and 5 Mbps. One can visually distinguish the version by checking
the on the resistor indicators on the bottom side of the board as Figure 8 shows.

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3. PTS Functionality Tests
The PTS consists of a set of six independent tests, each one checking a different part of the FMC
masterFIP board. Table 4 gives a short description of each one of them. Note that the same firmware is
used for all the tests, loaded at test00.
Table 4: List of tests
Test
Short Description
Operator's
Intervention
00
Loads firmware, tests mezzanine presence, verify speed version
Yes
01
Test front panel LED’s
Yes
02
Test WordFIP transmission and FieldDrive control/status lines
No
03
External Sync input/output tests.
No
04
1-Wire Digital thermometer (DS18B20U) communication test.
No
05
EEPROM (24AA64T) communication test. Writing IPMI data.
No

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4. Log files retrieval
Log files with detailed descriptions of the tests are automatically generated and archived in a .zip file
called: <timestamp>_zip_run_<run id>_ FmcMasterFip_<serial number>.zip.
The log files need to be delivered to CERN after completing the tests for all of the boards. To do so, please
follow the instructions below:
oPlug the USB memory key in to the computer.
oWait until Ubuntu mounts automatically the device.
oUsing the file explorer navigate to ~/Desktop/masterFIP_log/fmcmasterfip directory.
oSelect all the .zip files, right click and select copy.
oUsing the file explorer, click on the USB device that appeared on the left column, right click
and selecting paste.
oClick on the eject button on the left of the file explorer window and remove the USB key.
oTransfer the data to another computer with Internet access.
Finally, send the .zip file by email to the responsible of tests at CERN.

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5. Custom cable preparation
Before first setup dedicated cables must be prepared. Cable schematics are shown below. Cable length
is not important, as long as it is sufficient to connect to the test setup.
Note that for the PTS, as lengths are very small, there is no need to use the WorldFIP-protocol-specified
cable.
The following schematics are made with following markings:
yellow box –connector (type is given inside the box)
green box –pins of Dsub connector
red box –150 Ohm through-hole resistor
black wire –coaxial cable (about 30cm)
blue wire –shield of coaxial cable
Resistors (used for termination) should be soldered close to the Dsub connectors.
Figure 9 Schematic design of custom cables used by FMC MasterFIP PTS .

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6. First Time Setup
The following list explains how to setup the FMC masterFIP environment for the first time.
1) Make sure that the computer is switched off.
2) Remove the screws and open the computer cover. Confirm that the USB relay box is mounted on
the upper side of the computer cover.
Figure 10: Top side of the computer cover
3) Screw the SPEC board on the top side of the computer cover, as Figure 11 shows. Connect one side
of the PCIe extender cable to the SPEC. Pass the other side of the cable through the dedicated cut
of the computer cover.
Figure 11: SPEC mounted on the computer cover

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4) Plug the other side of the PCIe extender cable into a PCIe x4 (or higher) computer slot, as indicated
in Figure 12. Mount the computer cover back to close the computer box. Make sure the screws are
back on their place.
Figure 12: PCIe slot for the extender cable
5) Mount the FMC masterFIP board on the FMC connector of the SPEC board.
6) Plug the USB cable (connector A) into an available USB slot of the provided computer.
7) Plug the barcode-reader into an available USB slot of the computer.
8) Connect the monitor, keyboard and mouse to the computer.
9) Start the PC.
10) Install the FMC masterFIP test environment through the following commands. Please note that the
test environment may be installed in any path. The installation sequence then makes sure that the
top directory is called fmcmasterfip.
# test environment may be installed in any path
cd ~
# clone pts repository
git clone git://ohwr.org/cern-fip/masterfip/masterfip-tst.git fmcmasterfip
# enter in the directory
cd fmcmasterfip
# run install script
sudo ./install.sh
The install.sh script:
omakes sure that top directory is called fmcmasterfip
oinstalls all required linux packages
oclones git submodules
obuilds software and kernel modules
overifies if modules may be correctly loaded
ocreates test shortcut on desktop
11) Please make sure that the installation script ended with the following message:
Installation successful!
Creating desktop shortcut

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7. Testing Procedure
Place the ESD strap on your wrist.
Put the barcode sticker on the Bottom side of the FMC
masterFIP under test, in the position indicated with the white
square.
Mount the FMC masterFIP under-test on the SPEC board.
Connect the FMC masterFIP with the USB relay box and the nanoFIPdiag using the provided cables, as
in Figure 7. Note that the nanoFIPdiag speed version should match the masterFIP speed version.
Connecting Dsub9-LEMO cable:
oconnect the Dsub9 plug to the nanoFIPdDiag
oconnect the Positive LEMO plug to CH5 of the USB Relay Box
oconnect the Negative LEMO plug to CH3 of the USB Relay Box
Connecting miniDsub9-LEMO cable:
oconnect the miniDsub9 plug to the FMC masterFIP
oconnect the Positive LEMO plug to AWG IN of the USB Relay Box
oconnect the Negative LEMO plug to SYNC of the USB Relay Box
Connecting LEMO-LEMO cable:
oconnect CH1 of the USB Relay Box to the Trigger port of the FMC masterFIP

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Switch ON the computer.
Verify that the “Pwr” LED on the SPEC board is ON. This
will confirm that the SPEC board is properly plugged.
If the LED is OFF there is a problem with the power
supply lines.
After the computer has finished with the booting procedure:
Start the test by double clicking “PTSmasterFIP” icon
on the desktop.
New terminal window will appear.
When asked, type the password: “baraka” and [ENTER]
The program asks for the barcode of the board.
Check that the cursor is on the terminal, press the
button/trigger on the barcode reader.
The code will appear on the terminal. Press [ENTER].
The program will ask for a second barcode, in case the
manufacturer has a different serial number system.
Scan the second barcode and press [ENTER], or if there is
none, just press [ENTER].
The program will automatically execute tests 00 to 05.
Tests 00 and 01 ask for the user‘s intervention.
Test 00 will ask the operator to verify the FMC
masterFIP speed version by visually checking which of
R47, R48, R52, R53 resistors is mount.
Test 01 will ask the operator to verify if LED’s of FMC
masterFIP front panel are blinking one-by-one.
At the end the operator is informed of the results of all the tests
and is asked if he wants to repeat the whole process.
If no error has occurred, type [n] and then [ENTER].
In case of error, you could repeat the tests once by
typing [y] and [ENTER].
When prompted to switch off computer:
Type [y] and confirm with [ENTER].

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8. Common Causes of Test Failure
Once the testing has finished, all the errors will be listed on the screen. Usually, the error message is self-
explanatory. If you need detailed information, the test log files can be found in
/home/user/Desktop/masterFIP_log/fmcmasterfip.
Common problems with software setup
Please refer to the following paragraphs regarding issues that might affect each test.
USB calibration box not detected:
Verify that the USB cable is well connected between the PC and the box itself.
Verify with lsmod that the cp210x driver is mounted in the kernel.
Make sure you are using the Ubuntu version 14.04.00 LTS.
SPEC board with FMC masterFIP was not detected
Verify that the SPEC board is well connected to the PCIe port and the Pwr LED is ON.
Verify with lsmod that the SPEC and FMC drivers were properly mounted in the kernel.
Figure 13: modules that should be present after the ./install.sh

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Functionality test
Test 00
Firmware loading
FMC presence
Verification of speed version
oUser is asked to visually verify mounting of resistors R47, R48, R52 and R53 that are used
to indicate the speed version
oMounting is compared with speed identification detected by FPGA on the SPEC board
oUser is asked to verify if detected speed version matches the expected one
Possible errors:
More than one SPEC was found
oMake sure that only one SPEC device is mounted in the test PC.
No SPEC device was found
SPEC enumeration failed
oMake sure that SPEC device was mounted properly.
oMake sure that all software was successfully build.
oMake sure that all drivers were loaded successfully.
Firmware loader failure
No access to masterfip core
Wrong bitstream type loaded
oMake sure that installation procedure was done according to specification
FMC slot NOT populated
oMake sure that FMC board is mounted correctly
oCheck FMC soldering
Resistors mount
oAccording to the operator’s visual verification some resistors are not mount but are
detected by SPEC FPGA
oMight be caused by human error or shorting of traces leading to speed indicating
resistors
Test 01
Test01 verifies soldering of the FMC masterFIP front panel LED’s. The user is asked to visually verify if all
LED’s are blinking one after the other.
Possible errors:
Some LED’s may be constantly on or off.
oMake sure that LED’s are mounted correctly.
oMake sure the FMC connector is well soldered.

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Test 02
This test performs SSSB231 FieldDrive (IC14) tests. The following points are tested one-by-one as
described below.
FIP communication
oThe masterFIP sends a request frame asking for the presence of the nanoFIPdiag
(ID_DAT(147F)).
oThe PTS waits for the response RP_DAT and verifies that all the bytes of the frame
received by the masterFIP match the expected ones.
CD_N line
oThe CD_N line is expected to be inactive during bus idle. The test samples 10 times the
fd_rxcdn_i FPGA pin.
oThe CD_N line is expected to be active during frame reception. For this test the masterFIP
sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with an RP_DAT; the
fd_rxcdn_i line is expected to be active during the RP_DAT frame reception. In the FPGA
a counter is counting the transitions (falling edges) of the fd_rxcdn_i line. The test
expects to find the counter increased by two by the end of the RP_DAT frame.
TX_ERR line
oThe TX_ERR line is expected to be inactive when there is no transmission. The test
samples 10 times the fd_txer_i FPGA pin.
oThe TX_ERR line is expected to be inactive during normal frame transmission. For this
test the masterFIP sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with
an RP_DAT. The fd_txer_i line is expected to be inactive during this transmission and
reception. In the FPGA a counter is counting the transitions (rising edges) of the fd_txer_i
line. The test expects to find the counter at zero.
oThe TX_ERR line is expected to be active when the TXD line is stuck low or high. For this
test we set the fd_txd_o line to output a constant zero. At the same time we monitor
the counter that counts the fd_txer_i transitions and expect it increased.
WDG_N line
oThe WDG_N line is expected to be inactive when there is no transmission. The test
samples 10 times the fd_wdgn_i FPGA pin.
oThe WDG_N line is expected to be inactive during normal frame transmission. For this
test the masterFIP sends an ID_DAT(147F) which triggers the nanoFIPdiag to reply with
an RP_DAT. The fd_wdgn_i line is expected to be inactive during this transmission and
reception. In the FPGA a counter is counting the transitions (falling edges) of the
fd_wdgn_i line. The test expects to find the counter at zero.
oThe WDG_N line is expected to be active upon the transmission/reception of a very long
frame. For this test we trigger the transmission of a 1024 bytes frame. At the same time
we monitor the counter counting fd_wdgn_i transitions and expect it increased.